電子情報通信学会   アナログRF研究専門委員会実行委員  

2013.4 - 2017.3   

  Asian Solid State Circuits Conference, Program Committee  

2012.4 - 2017.11   

Ultralow-power class-c complementary colpitts crystal oscillator

Zule Xu, Noritoshi Kimura, Kenichi Okada, Masaya Miyahara

IEEE Solid-State Circuits Letters   3   274 - 277   2020

A 50.1-Gb/s 60-GHz CMOS Transceiver for IEEE 802.11ay With Calibration of LO Feedthrough and I/Q Imbalance.

Jian Pang, Shotaro Maki, Seitarou Kawai, Noriaki Nagashima, Yuuki Seo, Masato Dome, Hisashi Kato, Makihiko Katsuragi, Kento Kimura, Satoshi Kondo, Yuki Terashima, Hanli Liu, Teerachot Siriburanon, Aravind Tharayil Narayanan, Nurul Fajri, Tohru Kaneko, Toru Yoshioka, Bangan Liu, Yun Wang 0008, Rui Wu, Ning Li 0009, Korkut Kaan Tokgoz, Masaya Miyahara, Atsushi Shirane, Kenichi Okada

IEEE J. Solid State Circuits   54 ( 5 )   1375 - 1390   2019

An IoT Sensor Node SoC with Dynamic Power Scheduling for Sustainable Operation in Energy Harvesting Environment.

Yuji Yano, Seiya Yoshida, Shintaro Izumi, Hiroshi Kawaguchi, Tetsuya Hirose, Masaya Miyahara, Teruki Someya, Kenichi Okada, Ippei Akita, Yoshihiko Kurui, Hideyuki Tomizawa, Masahiko Yoshimoto

IEEE Asian Solid-State Circuits Conference(A-SSCC)   267 - 270   2019

Type-I Digital Ring-Based PLL Using Loop Delay Compensation and ADC-Based Sampling Phase Detector.

Zule Xu, Anugerah Firdauzi, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa

IEICE Trans. Electron.   102-C ( 7 )   520 - 529   2019

A 12.8-ns-Latency DDFS MMIC With Frequency, Phase, and Amplitude Modulations in 65-nm CMOS.

Abdel Martinez Alonso, Masaya Miyahara, Akira Matsuzawa

IEEE J. Solid State Circuits   53 ( 10 )   2840 - 2849   2018

A 64μs Start-Up 26/40MHz Crystal Oscillator with Negative Resistance Boosting Technique Using Reconfigurable Multi-Stage Amplifier.

Masaya Miyahara, Yukiya Endo, Kenichi Okada, Akira Matsuzawa

2018 IEEE Symposium on VLSI Circuits   115 - 116   2018

A 7GS/s Complete-DDFS-Solution in 65nm CMOS. Reviewed

Abdel Martinez Alonso, Masaya Miyahara, Akira Matsuzawa

IEICE Trans. Electron.   101-C ( 4 )   206 - 217   2018

SAR+ΔΣ ADCs with open-loop integrator using dynamic amplifier.

Akira Matsuzawa, Masaya Miyahara

IEICE Electron. Express   15 ( 5 )   2018

A 72.4dB-SNDR 20MHz-Bandwidth Continuous-Time ΔΣ ADC with High-Linearity Gm-Cells. Reviewed

Tohru Kaneko, Yuya Kimura, Masaya Miyahara, Akira Matsuzawa

IEICE Trans. Electron.   101-C ( 4 )   197 - 205   2018

SAR+ΔΣ ADC with open-loop integrator using dynamic amplifier. Reviewed

Akira Matsuzawa, Masaya Miyahara

Proceedings of International Conference on ASIC   2017-   24 - 27   2017

24.9 A 128-QAM 60GHz CMOS transceiver for IEEE802.11ay with calibration of LO feedthrough and I/Q imbalance. Reviewed

Jian Pang, Shotaro Maki, Seitarou Kawai, Noriaki Nagashima, Yuuki Seo, Masato Dome, Hisashi Kato, Makihiko Katsuragi, Kento Kimura, Satoshi Kondo, Yuki Terashima, Hanli Liu, Teerachot Siriburanon, Aravind Tharayil Narayanan, Nurul Fajri, Tohru Kaneko, Toru Yoshioka, Bangan Liu, Yun Wang 0008, Rui Wu, Ning Li 0009, Korkut Kaan Tokgoz, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa

2017 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE (ISSCC)   424 - 425   2017

An 84 dB dynamic range 62.5-625 kHz bandwidth clock-scalable noise-shaping SAR ADC with open-loop integrator using dynamic amplifier. Reviewed

Masaya Miyahara, Akira Matsuzawa

Proceedings of the Custom Integrated Circuits Conference   2017-   1 - 4   2017

A Wide Bandwidth Current Mode Filter Technique Using High Power Efficiency Current Amplifiers with Complementary Input. Reviewed

Tohru Kaneko, Yuya Kimura, Masaya Miyahara, Akira Matsuzawa

IEICE Trans. Electron.   100-C ( 6 )   539 - 547   2017

High Resolution Mixed-Domain Delta-Sigma Time-to-Digital Converter Using Compensated Charge-Pump Integrator. Reviewed

Anugerah Firdauzi, Zule Xu, Masaya Miyahara, Akira Matsuzawa

IEICE Trans. Electron.   100-C ( 6 )   548 - 559   2017

64-QAM 60-GHz CMOS Transceivers for IEEE 802.11ad/ay. Reviewed

Rui Wu, Ryo Minami, Yuuki Tsukui, Seitaro Kawai, Yuuki Seo, Shinji Sato, Kento Kimura, Satoshi Kondo, Tomohiro Ueno, Nurul Fajri, Shoutarou Maki, Noriaki Nagashima, Yasuaki Takeuchi, Tatsuya Yamaguchi, Ahmed Musa, Korkut Kaan Tokgoz, Teerachot Siriburanon, Bangan Liu, Yun Wang 0008, Jian Pang, Ning Li 0009, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa

IEEE J. Solid State Circuits   52 ( 11 )   2871 - 2891   2017

A high-speed DDFS MMIC with frequency, phase and amplitude modulations in 65nm CMOS. Reviewed

Abdel Martinez Alonso, Masaya Miyahara, Akira Matsuzawa

2017 IEEE Asian Solid-State Circuits Conference, A-SSCC 2017 - Proceedings   2017-   181 - 184   2017

Ultra-high-data-rate 60-GHz CMOS transceiver for future radio access network.

Rui Wu, Ryo Minami, Yuuki Tsukui, Seitaro Kawai, Yuuki Seo, Shinji Sato, Kento Kimura, Satoshi Kondo, Tomohiro Ueno, Nurul Fajri, Shoutarou Maki, Noriaki Nagashima, Yasuaki Takeuchi, Tatsuya Yamaguchi, Ahmed Musa, Korkut Kaan Tokgoz, Teerachot Siriburanon, Bangan Liu, Yun Wang 0008, Jian Pang, Ning Li 0009, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa

12th IEEE International Conference on ASIC(ASICON)   1025 - 1028   2017

A 7GS/s direct digital frequency synthesizer with a two-times interleaved RDAC in 65nm CMOS. Reviewed

Abdel Martinez Alonso, Masaya Miyahara, Akira Matsuzawa

ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference   151 - 154   2017

Synthesis and Automatic Layout of Resistive Digital-to-Analog Converter Based on Mixed-Signal Slice Cell Reviewed

Mitsutoshi Sugawara, Kenji Mori, Zule Xu, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa

IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E99A ( 12 )   2435 - 2443   2016.12

A Design of Op-Amp Free SAR-VCO Hybrid ADC with 2nd-Order Noise Shaping in 65nm CMOS Technology Reviewed

Yu Hou, Zhijie Chen, Masaya Miyahara, Akira Matsuzawa

IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E99A ( 12 )   2473 - 2482   2016.12

A 3.6 GHz Low-Noise Fractional-N Digital PLL Using SAR-ADC-Based TDC Reviewed

Zule Xu, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa

IEEE JOURNAL OF SOLID-STATE CIRCUITS   51 ( 10 )   2345 - 2356   2016.10

A 9-bit 1.8 GS/s 44 mW Pipelined ADC Using Linearized Open-Loop Amplifiers Reviewed

Lilan Yu, Masaya Miyahara, Akira Matsuzawa

IEEE JOURNAL OF SOLID-STATE CIRCUITS   51 ( 10 )   2210 - 2221   2016.10

A 10-bit 6.8-GS/s Direct Digital Frequency Synthesizer Employing Complementary Dual-Phase Latch-Based Architecture Reviewed

Abdel Martinez Alonso, Masaya Miyahara, Akira Matsuzawa

IEICE TRANSACTIONS ON ELECTRONICS   E99C ( 10 )   1200 - 1210   2016.10

A 74.9 dB SNDR 1 MHz bandwidth 0.9 mW delta-sigma time-to-digital converter using charge pump and SAR ADC Reviewed

Anugerah Firdauzi, Zule Xu, Masaya Miyahara, Akira Matsuzawa

Proceedings - IEEE International Symposium on Circuits and Systems   2016-   57 - 60   2016.7

A 2.2 GHz-242 dB-FOM 4.2 mW ADC-PLL Using Digital Sub-Sampling Architecture Reviewed

Teerachot Siriburanon, Satoshi Kondo, Kento Kimura, Tomohiro Ueno, Satoshi Kawashima, Tohru Kaneko, Wei Deng, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa

IEEE JOURNAL OF SOLID-STATE CIRCUITS   51 ( 6 )   1385 - 1397   2016.6

A 9.35-ENOB, 14.8 fJ/conv.-step Fully-Passive Noise-Shaping SAR ADC. Reviewed

Zhijie Chen, Masaya Miyahara, Akira Matsuzawa

IEICE Trans. Electron.   99-C ( 8 )   963 - 973   2016

A 76-dB-DR 6.8-mW 20-MHz Bandwidth CT Delta Sigma ADC with a High-linearity Gm-C Filter Reviewed

Tohru Kaneko, Yuya Kimura, Koji Hirose, Masaya Miyahara, Akira Matsuzawa

ESSCIRC CONFERENCE 2016   253 - 256   2016

A 2nd Order Fully-Passive Noise-Shaping SAR ADC with Embedded Passive Gain Reviewed

Zhijie Chen, Masaya Miyahara, Akira Matsuzawa

2016 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC)   309 - 312   2016

A Stability-Improved Single-Opamp Third-Order Sigma Delta Modulator by Using a Fully-Passive Noise-Shaping SAR ADC and Passive Adder Reviewed

Zhijie Chen, Masaya Miyahara, Akira Matsuzawa

ESSCIRC CONFERENCE 2016   249 - 252   2016

Fully Passive Noise Shaping Techniques in a Charge-Redistribution SAR ADC. Reviewed

Zhijie Chen, Masaya Miyahara, Akira Matsuzawa

IEICE Trans. Electron.   99-C ( 6 )   623 - 631   2016

Highly Linear Open-Loop Amplifiers Using Nonlinearity Cancellation and Gain Adapting Techniques. Reviewed

Lilan Yu, Masaya Miyahara, Akira Matsuzawa

IEICE Trans. Electron.   99-C ( 6 )   641 - 650   2016

A 2 GHz 3.1 mW Type-I Digital Ring-Based PLL Reviewed

Zule Xu, Anugerah Firdauzi, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa

ESSCIRC CONFERENCE 2016   205 - 208   2016

An LO-Buffer-Less 60-GHz CMOS Transmitter with Oscillator Pulling Mitigation Reviewed

Rui Wu, Jian Pang, Yuuki Seo, Kento Kimura, Seitaro Kawai, Shinji Sato, Satoshi Kondo, Tomohiro Ueno, Nurul Fajri, Yasuaki Takeuchi, Tatsuya Yamaguchi, Ahmed Musa, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa

2016 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC)   109 - 112   2016

A 74.9 dB SNDR 1 MHz Bandwidth 0.9 mW Delta-Sigma Time-to-Digital Converter Using Charge Pump and SAR ADC Reviewed

Anugerah Firdauzi, Zule Xu, Masaya Miyahara, Akira Matsuzawa

2016 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)   57 - 60   2016

A 9-bit 500-MS/s 6.0-mW Dynamic Pipelined ADC Using Time-Domain Linearized Dynamic Amplifiers Reviewed

Lilan Yu, Masaya Miyahara, Akira Matsuzawa

2016 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC)   65 - 68   2016

An Op-amp Free SAR-VCO Hybrid ADC with Second-Order Noise Shaping Reviewed

Yu Hou, Zhijie Chen, Masaya Miyahara, Akira Matsuzawa

2016 IEEE INTERNATIONAL CONFERENCE ON ELECTRON DEVICES AND SOLID-STATE CIRCUITS (EDSSC)   387 - 390   2016

Ultralow-Voltage High-Speed Flash ADC Design Strategy Based on FoM-Delay Product Reviewed

James Lin, Ibuki Mano, Masaya Miyahara, Akira Matsuzawa

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS   23 ( 8 )   1518 - 1527   2015.8

An Ultra-Low-Voltage 160 MS/s 7 Bit Interpolated Pipeline ADC Using Dynamic Amplifiers Reviewed

James Lin, Daehwa Paik, Seungjong Lee, Masaya Miyahara, Akira Matsuzawa

IEEE JOURNAL OF SOLID-STATE CIRCUITS   50 ( 6 )   1399 - 1411   2015.6

A Circuit Technique for Enhancing Gain of Complementary Input Operational Amplifier with High Power Efficiency Reviewed

Tohru Kaneko, Masaya Miyahara, Akira Matsuzawa

IEICE TRANSACTIONS ON ELECTRONICS   E98C ( 4 )   315 - 321   2015.4

An All-Digital Reconfigurable Time-Domain ADC for Low-Voltage Sensor Interface in 65 nm CMOS Technology Reviewed

Yu Hou, Takamoto Watanabe, Masaya Miyahara, Akira Matsuzawa

IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E98A ( 2 )   466 - 475   2015.2

Sub-Picosecond Resolution and High-Precision TDC for ADPLLs Using Charge Pump and SAR-ADC Reviewed

Zule Xu, Seungjong Lee, Masaya Miyahara, Akira Matsuzawa

IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E98A ( 2 )   476 - 484   2015.2

A Novel Direct Digital Frequency Synthesizer Employing Complementary Dual-Phase Latch-Based Architecture Reviewed

Abdel Martinez Alonso, Masaya Miyahara, Akira Matsuzawa

PROCEEDINGS OF 2015 IEEE 11TH INTERNATIONAL CONFERENCE ON ASIC (ASICON)   2015

A 9-bit 1.8-GS/s Pipelined ADC Using Linearized Open-Loop Amplifiers Reviewed

Lilan Yu, Masaya Miyahara, Akira Matsuzawa

2015 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC)   229 - 232   2015

A 3.6 GHz Fractional-N Digital PLL Using SAR-ADC-Based TDC with-110 dBc/Hz In-Band Phase Noise Reviewed

Zule Xu, Masaya Miyahara, Akira Matsuzawa

2015 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC)   321 - 324   2015

An Ultra-Low-Voltage, Wide Signal Swing, and Clock-Scalable Dynamic Amplifier Using a Common-Mode Detection Technique Reviewed

James Lin, Masaya Miyahara, Akira Matsuzawa

IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E97A ( 12 )   2400 - 2410   2014.12

A 0.8 ps-LSB, 10-bit, 0.018 mm2 Time-to-Digital Converter Reviewed

Zule Xu, Mitsutoshi Sugawara, Masaya Miyahara, Akira Matsuzawa

Internatioal Conference on Solid State Devices and Materials (SSDM)   2014.9

A 7-bit 1-GS/s Flash ADC with Background Calibration Reviewed

Sanroku Tsukamoto, Masaya Miyahara, Akira Matsuzawa

IEICE TRANSACTIONS ON ELECTRONICS   E97C ( 4 )   298 - 307   2014.4

Picosecond Resolution Time-to-Digital Converter Using G(m)-C Integrator and SAR-ADC Reviewed

Zule Xu, Masaya Miyahara, Akira Matsuzawa

IEEE TRANSACTIONS ON NUCLEAR SCIENCE   61 ( 2 )   852 - 859   2014.4

Injection Locked Charge-Pump PLL with a Replica of the Ring Oscillator Reviewed

Jeonghoon Han, Masaya Miyahara, Akira Matsuzawa

IEICE TRANSACTIONS ON ELECTRONICS   E97C ( 4 )   316 - 324   2014.4

A Compact, Low-Power and Low-Jitter Dual-Loop Injection Locked PLL Using All-Digital PVT Calibration Reviewed

Ahmed Musa, Wei Deng, Teerachot Siriburanon, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa

IEEE JOURNAL OF SOLID-STATE CIRCUITS   49 ( 1 )   50 - 60   2014.1

A 64-QAM 60GHz CMOS Transceiver with 4-Channel Bonding Reviewed

Kenichi Okada, Ryo Minami, Yuuki Tsukui, Seitaro Kawai, Yuuki Seo, Shinji Sato, Satoshi Kondo, Tomohiro Ueno, Yasuaki Takeuchi, Tatsuya Yamaguchi, Ahmed Musa, Rui Wu, Masaya Miyahara, Akira Matsuzawa

2014 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE DIGEST OF TECHNICAL PAPERS (ISSCC)   57   346 - +   2014

A Dual-loop Injection-locked PLL with All-digital Background Calibration System for On-chip Clock Generation Reviewed

Wei Deng, Ahmed Musa, Teerachot Siriburanon, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa

2014 19TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC)   21 - 22   2014

Extension method of tolerance to voltage and temperature variations in an injection-locked PLL Reviewed

Jeonghoon Han, Masaya Miyahara, Akira Matsuzawa

IEICE ELECTRONICS EXPRESS   11 ( 9 )   20140127   2014

A 2.2GS/s 7b 27.4mW Time-Based Folding-Flash ADC with Resistively Averaged Voltage-to-Time Amplifiers Reviewed

Masaya Miyahara, Ibuki Mano, Masaaki Nakayama, Kenichi Okada, Akira Matsuzawa

2014 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE DIGEST OF TECHNICAL PAPERS (ISSCC)   57   388 - +   2014

A 12-bit Interpolated Pipeline ADC Using Body Voltage Controlled Amplifier Reviewed

Hyunui Lee, Masaya Miyahara, Akira Matsuzawa

IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E96A ( 12 )   2508 - 2515   2013.12

A 12b 50/70 MS/s 2.2/4.6 mW 0.03mm2 CMOS SAR ADC for a frequency, performance, and power scalable ADC Reviewed

S. Lee, H. Kawaraguchi, T. Hirato, Masaya Miyahara, A. Matsuzawa

Internatioal Conference on Solid State Devices and Materials (SSDM)   2013.9

A Low-Noise High-Dynamic Range Charge Sensitive Amplifier for Gas Particle Detector Pixel Readout LSIs Reviewed

Fei Li, Masaya Miyahara, Akira Matsuzawa

IEICE TRANSACTIONS ON ELECTRONICS   E96C ( 6 )   903 - 911   2013.6

Design of Interpolated Pipeline ADC Using Low-Gain Open-Loop Amplifiers Reviewed

Hyunui Lee, Masaya Miyahara, Akira Matsuzawa

IEICE TRANSACTIONS ON ELECTRONICS   E96C ( 6 )   838 - 849   2013.6

A Time-Domain Architecture and Design Method of High Speed A-to-D Converters with Standard Cells Reviewed

Masao Takayama, Shiro Dosho, Noriaki Takeda, Masaya Miyahara, Akira Matsuzawa

IEICE TRANSACTIONS ON ELECTRONICS   E96C ( 6 )   813 - 819   2013.6

A 6 bit, 7 mW, 700 MS/s Subranging ADC Using CDAC and Gate-Weighted Interpolation Reviewed

Hyunui Lee, Yusuke Asada, Masaya Miyahara, Akira Matsuzawa

IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E96A ( 2 )   422 - 433   2013.2

Full Four-Channel 6.3-Gb/s 60-GHz CMOS Transceiver With Low-Power Analog and Digital Baseband Circuitry Reviewed

Kenichi Okada, Keitarou Kondou, Masaya Miyahara, Masashi Shinagawa, Hiroki Asada, Ryo Minami, Tatsuya Yamaguchi, Ahmed Musa, Yuuki Tsukui, Yasuo Asakura, Shinya Tamonoki, Hiroyuki Yamagishi, Yasufumi Hino, Takahiro Sato, Hironori Sakaguchi, Naoki Shimasaki, Toshihiko Ito, Yasuaki Takeuchi, Ning Li, Qinghong Bu, Rui Murakami, Keigo Bunsen, Kota Matsushita, Makoto Noda, Akira Matsuzawa

IEEE JOURNAL OF SOLID-STATE CIRCUITS   48 ( 1 )   46 - 65   2013.1

A 6-bit Subranging ADC with Single CDAC Interpolation Reviewed

Hyunui Lee, Masaya Miyahara, Akira Matsuzawa

2013 IEEE INTERNATIONAL CONFERENCE OF ELECTRON DEVICES AND SOLID-STATE CIRCUITS (EDSSC)   2013

A digitally-calibrated 20-Gb/s 60-GHz direct-conversion transceiver in 65-nm CMOS Reviewed

Seitaro Kawai, Ryo Minami, Yuki Tsukui, Yasuaki Takeuchi, Hiroki Asada, Ahmed Musa, Rui Murakami, Takahiro Sato, Qinghong Bu, Ning Li, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa

Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium   137 - 140   2013

A 1ps-Resolution Integrator-Based Time-to-Digital Converter Using a SAR-ADC in 90nm CMOS Reviewed

Zule Xu, Masaya Miyahara, Akira Matsuzawa

2013 IEEE 11TH INTERNATIONAL NEW CIRCUITS AND SYSTEMS CONFERENCE (NEWCAS)   16 - 19   2013

A 12-bit Interpolated Pipeline ADC using Body Voltage Controlled Amplifier Reviewed

Hyunui Lee, Masaya Miyahara, Akira Matsuzawa

2013 IEEE 11TH INTERNATIONAL NEW CIRCUITS AND SYSTEMS CONFERENCE (NEWCAS)   2013

A 12-bit Interpolated Pipeline ADC Using Body Voltage Controlled Amplifier Reviewed

LEE Hyunui, MIYAHARA Masaya, MATSUZAWA Akira

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   96 ( 12 )   2508 - 2515   2013

Design of CMOS low-noise analog circuits for particle detector pixel readout LSIs Reviewed

Fei Li, Masaya Miyahara, Akira Matsuzawa

IEICE Transactions on Electronics   E96-C ( 4 )   568 - 576   2013

A 83-dB SFDR 10-MHz Bandwidth Continuous-Time Delta-Sigma Modulator Employing a One-Element-Shifting Dynamic Element Matching Reviewed

Hong Phuc Ninh, Masaya Miyahara, Akira Matsuzawa

IEICE TRANSACTIONS ON ELECTRONICS   E95C ( 6 )   1017 - 1025   2012.6

An Analysis on a Dynamic Amplifier and Calibration Methods for a Pseudo-Differential Dynamic Comparator Reviewed

PAIK Daehwa, MIYAHARA Masaya, MATSUZAWA Akira

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   95 ( 2 )   456 - 470   2012.2

A 83-dB SFDR 10-MHz Bandwidth Continuous-Time Delta-Sigma Modulator Employing a One-Element-Shifting Dynamic Element Matching Reviewed

NINH Hong Phuc, MIYAHARA Masaya, MATSUZAWA Akira

IEICE Transactions on Electronics   95 ( 6 )   1017 - 1025   2012

A 0.5 V, 420 MSps, 7-bit Flash ADC Using All-Digital Time-Domain Delay Interpolation Reviewed

James Lin, Ibuki Mano, Masaya Miyahara, Akira Matsuzawa

2012 IEEE INTERNATIONAL CONFERENCE ON ELECTRON DEVICES AND SOLID STATE CIRCUIT (EDSSC)   2012

An 84 mW 0.36 mm 2 analog baseband circuits for 60 GHz wireless transceiver in 40 nm CMOS Reviewed

Masaya Miyahara, Hironori Sakaguchi, Naoki Shimasaki, Akira Matsuzawa

Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium   495 - 498   2012

Qpix v.1: A high speed 400-pixels readout LSI with 10-bit 10 MSps pixel ADCs Reviewed

Fei Li, Vu Minh Khoa, Masaya Miyahara, Akira Matsuzawa

NUCLEAR INSTRUMENTS & METHODS IN PHYSICS RESEARCH SECTION A-ACCELERATORS SPECTROMETERS DETECTORS AND ASSOCIATED EQUIPMENT   650 ( 1 )   101 - 105   2011.9

Qpix v.1: A high speed 400-pixels readout LSI with 10-bit 10 MSps pixel ADCs

Fei Li, Vu Minh Khoa, Masaya Miyahara, Akira Matsuzawa

NUCLEAR INSTRUMENTS & METHODS IN PHYSICS RESEARCH SECTION A-ACCELERATORS SPECTROMETERS DETECTORS AND ASSOCIATED EQUIPMENT   650 ( 1 )   101 - 105   2011.9

A 10b 320 MS/s 40 mW Open-Loop Interpolated Pipeline ADC Reviewed

Masaya Miyahara, Hyunui Lee, Daehwa Paik, Akira Matsuzawa

IEEE Symposium on VLSI Circuits   126 - 127   2011.6

A 15.5 dB, wide signal swing, dynamic amplifier using a common-mode voltage detection technique Reviewed

James Lin, Masaya Miyahara, Akira Matsuzawa

Proceedings - IEEE International Symposium on Circuits and Systems   21 - 24   2011

An analysis on a pseudo-differential dynamic comparator with load capacitance calibration Reviewed

Daehwa Paik, Masaya Miyahara, Akira Matsuzawa

Proceedings of International Conference on ASIC   461 - 464   2011

A 83-dB SFDR 10-MHz bandwidth continuous-time Delta-Sigma modulator employing a one-element-shifting dynamic element matching Reviewed

Hong Phuc Ninh, Masaya Miyahara, Akira Matsuzawa

2011 IEEE International Symposium on Radio-Frequency Integration Technology, RFIT 2011   109 - 112   2011

A time-domain architecture and design method of high speed A-to-D converters with standard cells Reviewed

Masao Takayama, Shiro Dosho, Noriaki Takeda, Masaya Miyahara, Akira Matsuzawa

2011 Proceedings of Technical Papers: IEEE Asian Solid-State Circuits Conference 2011, A-SSCC 2011   353 - 356   2011

An 8-bit 600-MSps Analog-to-Digital Converter for FWA

Daehwa Paik, Masaya Miyahara, Akira Matsuzawa

G-COE PICE International Symposium   124 - 125   2010.12

A 0.5 V, 1.2 mW, 160 fJ, 600 MS/s 5 bit Flash ADC

James Lin, Kei Yoshihara, Masaya Miyahara, Akira Matsuzawa

International Workshop on Millimeter Wave Wireless Technology and Applications   120 - 121   2010.12

An Injection-locked Ring Oscillator for an ADC and a DAC embedded in a 38GHz-band FWA System

Jeonghoon HAN, Masaya Miyahara, Akira Matsuzaw

International Workshop on Millimeter Wave Wireless Technology and Applications   126 - 127   2010.12

Designing of a 10MHz BW 77dB SNDR 8.1mW Continuous-Time Delta-Sigma Modulator With a Proposed Low Power, Rail-to-Rail Output Swing OPAMP

Hong Phuc NINH, Ngoc Huy Dong TA, Masaya Miyahara, Akira MATSUZAWA

International Workshop on Millimeter Wave Wireless Technology and Applications   118 - 119   2010.12

An Ultra-Low >Power Wireless Communication Circuit for Medical Telemetry Applications

Toshiaki Yamagishi, Kenichi Matsunaga, Masaya Miyahara, Akira Matsuzawa

International Workshop on Millimeter Wave Wireless Technology and Applications   2010.12

A new particle detector LSI, Qpix: Integrating high speed ADC for each pixel Reviewed

Akira Matsuzawa, Vu Minh Khoa, Fei Li, Masaya Miyahara, Takashi Kurashina

NUCLEAR INSTRUMENTS & METHODS IN PHYSICS RESEARCH SECTION A-ACCELERATORS SPECTROMETERS DETECTORS AND ASSOCIATED EQUIPMENT   623 ( 1 )   477 - 479   2010.11

Designing of a 10MHz BW 77dB SNDR 8.1mW Continuous-Time Delta-Sigma Modulator With a Proposed Low Power, Rail-to-Rail Output Swing OPAMP

Hong Phuc NINH, Ngoc Huy Dong TA, Masaya Miyahara, Akira MATSUZAWA

IEICE Integrated Circuits and Devices in Vietnam (IEICE-ICDV)   2010.8

An 8-Bit 600-MSps Flash ADC Using Interpolating and Background Self-Calibrating Techniques Reviewed

PAIK Daehwa, ASADA Yusuke, MIYAHARA Masaya, MATSUZAWA Akira

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   93 ( 2 )   402 - 414   2010.2

A 0.5 V, 1.2 mW, 160 fJ, 600 MS/s 5 bit flash ADC Reviewed

Masaya Miyahara, James Lin, Kei Yoshihara, Akira Matsuzawa

2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010   177 - 180   2010

Asynchronous Differential Capacitance-to-Digital Converter for Capacitive Sensors Reviewed

Tuan Minh Vo, Yasuhide Kuramochi, Masaya Miyahara, Takashi Kurashina, Akira Matsuzawa

SASIMI   2009.3

A 6bit, 7mW, 250fJ, 700MS/s Subranging ADC Reviewed

Yusuke Asada, Kei Yoshihara, Tatsuya Urano, Masaya Miyahara, Akira Matsuzawa

2009 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC)   141 - 144   2009

A Low-Offset Latched Comparator Using Zero-Static Power Dynamic Offset Cancellation Technique Reviewed

Masaya Miyahara, Akira Matsuzawa

2009 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC)   233 - 236   2009

A Performance Model for the Design of Pipelined ADCs with Consideration of Overdrive Voltage and Slewing Reviewed

MIYAHARA Masaya, MATSUZAWA Akira

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   91 ( 2 )   469 - 475   2008.2

A Low-Noise Self-Calibrating Dynamic Comparator for High-Speed ADCs Reviewed

Masaya Miyahara, Yusuke Asada, Daehwa Paik, Akira Matsuzawa

2008 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE   269 - 272   2008

The Effects of Switch Resistances on Pipelined ADC Performances and the Optimization for the Settling Time Reviewed

MIYAHARA Masaya, MATSUZAWA Akira

IEICE technical report   107 ( 163 )   35 - 40   2007.7

The Effects of Switch Resistances on Pipelined ADC Performances and the Optimization for the Settling Time Reviewed

MIYAHARA Masaya, MATSUZAWA Akira

IEICE Trans. Electron., C   90 ( 6 )   1165 - 1171   2007.6

A Low-Power Mixed-Domain Delta-Sigma Time-to-Digital Converter Using Charge-Pump and SAR ADC (情報センシング)

FIRDAUZI Anugerah, XU Zule, MIYAHARA Masaya, MATSUZAWA Akira

映像情報メディア学会技術報告 = ITE technical report   40 ( 24 )   9 - 14   2016.8

42Gb/s 60GHz CMOS Transceiver for IEEE 802.11ay Reviewed

Rui Wu, Seitaro Kawai, Yuuki Seo, Nurul Fajri, Kento Kimura, Shinji Sato, Satoshi Kondo, Tomohiro Ueno, Teerachot Siriburanon, Shoutarou Maki, Bangan Liu, Yun Wang, Noriaki Nagashima, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa

2016 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE (ISSCC)   59   248 - U343   2016

C-12-31 Study of calibration of resistance mismatch in Resistor DAC

Xia Yuan, Miyahara Masaya, Matsuzawa Akira

Proceedings of the Society Conference of IEICE   2015 ( 2 )   71 - 71   2015.8

C-12-17 Consideration of common-mode voltage stabilization of complementary-input Gm-cell for wide bandwidth filter

Kimura Yuya, Kaneko Tohru, Yokomizo Shinya, Miyahara Masaya, Matsuzawa Akira

Proceedings of the Society Conference of IEICE   2015 ( 2 )   57 - 57   2015.8

C-12-32 Study of Low-noise Dynamic Comparator using Cross-Coupling Connection

Endo Yukiya, Miyahara Masaya, Matsuzawa Akira

Proceedings of the Society Conference of IEICE   2015 ( 2 )   72 - 72   2015.8

A-1-28 Delta-Sigma Time to Digital Converter Using Charge Pump and SAR ADC

Firdauzi Anugerah, Xu Zule, Miyahara Masaya, Matsuzawa Akira

Proceedings of the IEICE General Conference   2015   28 - 28   2015.2

C-12-35 A Comparison of Current-steering DAC and Resistor DAC in Low Power Supply Voltage

Kawashima Satoshi, Miyahara Masaya, Matsuzawa Akira

Proceedings of the IEICE General Conference   2015 ( 2 )   96 - 96   2015.2

C-12-1 Consideration of Enhancing Linearity Technique for Wideband Variable Gain Amplifer

Kaneko Tohru, Miyahara Masaya, Matsuzawa Akira

Proceedings of the IEICE General Conference   2015 ( 2 )   62 - 62   2015.2

A 9.35-ENOB, 14.8 fJ/conv.-step Fully-Passive Noise-Shaping SAR ADC Reviewed

Zhijie Chen, Masaya Miyahara, Akira Matsuzawa

2015 SYMPOSIUM ON VLSI CIRCUITS (VLSI CIRCUITS)   64   2015

An HCI-Healing 60GHz CMOS Transceiver Reviewed

Rui Wu, Seitaro Kawai, Yuuki Seo, Kento Kimura, Shinji Sato, Satoshi Kondo, Tomohiro Ueno, Nurul Fajri, Shoutarou Maki, Noriaki Nagashima, Yasuaki Takeuchi, Tatsuya Yamaguchi, Ahmed Musa, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa

2015 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE DIGEST OF TECHNICAL PAPERS (ISSCC)   58   350 - +   2015

A 2.2GHz-242dB-FOM 4.2mW ADC-PLL Using Digital Sub-Sampling Architecture Reviewed

Teerachot Siriburanon, Satoshi Kondo, Kento Kimura, Tomohiro Ueno, Satoshi Kawashima, Tohru Kaneko, Wei Deng, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa

2015 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE DIGEST OF TECHNICAL PAPERS (ISSCC)   58   440 - U623   2015

5G from Tokyo Institute of Technology Point of View-For Realization of Millimeter-wave Heterogeneous Networks-

阪口啓, TRAN Gia Khanh, 荒木純道, 安藤真, 広川二郎, 府川和彦, CHANG Yuyuan, 高田潤一, 齋藤健太郎, 松澤昭, 岡田健一, 宮原正也

電子情報通信学会技術研究報告   115 ( 233(RCS2015 156-189) )   2015

Investigation of Frequency Characteristic of High Linearity Gm-Cell with Level Shifter

KANEKO Tohru, YOKOMIZO Shinya, MIYAHARA Masaya, MATSUZAWA Akira

IEICE technical report. Computer systems   114 ( 346 )   79 - 84   2014.12

C-12-27 Consideration of High Linearity Gm cell for wide bandwidth Gm-C filter

Yokomizo Shinya, Kaneko Tohru, Miyahara Masaya, Matsuzawa Akira

Proceedings of the Society Conference of IEICE   2014 ( 2 )   79 - 79   2014.9

C-12-15 Quasi-3D Pixel Readout LSIs for Gaseous Particle Detectors with Folding Integration Technique

Nagashio Akira, Sengendo K. P., Miyahara Masaya, Matsuzawa Akira

Proceedings of the Society Conference of IEICE   2014 ( 2 )   67 - 67   2014.9

A Varactor-Less and Dither-Less LC-Digitally Controlled Oscillator with 9-bit Fine Bank, 0.26 mm2 Area, and 6.7 kHz Frequency Resolution Reviewed

Zule Xu, Mitsutoshi Sugawara, Kenji Mori

Internatioal Conference on Solid State Devices and Materials (SSDM)   2014.9

A 0.5-to-1 V 9-bit 15-to-90 MS/s Digitally Interpolated Pipelined-SAR ADC Using Dynamic Amplifier Reviewed

James Lin, Zule Xu, Masaya Miyahara, Akira Matsuzawa

2014 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC)   85 - 88   2014

A Dual-loop Injection-locked PLL with All-digital Background Calibration System for On-chip Clock Generation Reviewed

Wei Deng, Ahmed Musa, Teerachot Siriburanon, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa

2014 19TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC)   21 - 22   2014

Radio Receiver Front-End Using Time-Based All-Digital ADC (TAD) Reviewed

Tomohito Terasawa, Yuji Kamiya, Hiroyuki Kawashima, Kenichiro Imai, Masanobu Suzuki, Takamoto Watanabe, Nobuyuki Taguchi, Manabu Sawada, Yu Hou, Yoshiyuki Hirooka, Ninh Hong Phuc, Masaya Miyahara, Akira Matsuzawa

2014 21ST IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS (ICECS)   471 - 473   2014

All-Digital 0.016mm(2) Reconfigurable Sensor-ADC Using 4CKES-TAD in 65nm Digital CMOS Reviewed

Takamoto Watanabe, Yu Hou, Masaya Miyahara, Akira Matsuzawa

2014 21ST IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS (ICECS)   21 - 24   2014

A 0.84ps-LSB 2.47mW time-to-digital converter using charge pump and SAR-ADC Reviewed

Zule Xu, Seungjong Lee, Masaya Miyahara, Akira Matsuzawa

Proceedings of the Custom Integrated Circuits Conference   1 - 4   2013.11

Radio Receiver Front-End Using Time-Based ADC

TERASAWA Tomohito, KAMIYA Yuji, KAWASHIMA Hiroyuki, IMAI Kenichirou, SUZUKI Masanobu, WATANABE Takamoto, TAGUCHI Nobuyuki, SAWADA Manabu, Hou YU, HIROOKA Yoshiyuki, Ninh HongPHUC, MIYAHARA Masaya, MATSUZAWA Akira

IEICE technical report   113 ( 266 )   49 - 54   2013.10

Consideration of High Linearity Amplifier with Complementary Input

Kaneko Tohru, Miyahara Masaya, Matsuzawa Akira

Proceedings of the Society Conference of IEICE   2013 ( 2 )   85 - 85   2013.9

Study of low power consumption in a low noise dynamic comparator

Kawashima Satoshi, Miyahara Masaya, Matsuzawa Akira

Proceedings of the Society Conference of IEICE   2013 ( 2 )   74 - 74   2013.9

C-12-58 A Dual-Loop Injection-Locked PLL with All-Digital PVT Calibration System

Wei Deng, Musa Ahmed, Siributanon Teerachot, Miyahara Masaya, Okada Kenichi, Matsuzawa Akira

Proceedings of the IEICE General Conference   2013 ( 2 )   129 - 129   2013.3

C-12-47 Enhancing DC Gain of Op-Amp with Complementary lnput

Kaneko Tohru, Miyahara Masaya, Matsuzawa Akira

Proceedings of the IEICE General Conference   2013 ( 2 )   118 - 118   2013.3

4.4 Dependable ADC Technology(4. Variations in Device Characteristics,<Special Survey>Dependable VLSI System)

MATSUZAWA Akira, MIYAHARA Masaya

The Journal of Reliability Engineering Association of Japan   35 ( 8 )   449 - 449   2013

A 0.022mm2 970μW dual-loop injection-locked PLL with -243dB FOM using synthesizable all-digital PVT calibration circuits Reviewed

Wei Deng, Ahmed Musa, Teerachot Siriburanon, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa

Digest of Technical Papers - IEEE International Solid-State Circuits Conference   56   248 - 249   2013

A 0.55 V 7-bit 160 MS/s Interpolated Pipeline ADC Using Dynamic Amplifiers Reviewed

James Lin, Daehwa Paik, Seungjong Lee, Masaya Miyahara, Akira Matsuzawa

2013 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC)   1 - 4   2013

Ultra-Low-Voltage Dynamic Amplifier

LIN James, MIYAHARA Masaya, MATSUZAWA Akira

Technical report of IEICE. ICD   112 ( 365 )   71 - 71   2012.12

C-12-25 Consideration of comparators offset calibration method using MOM capacitor under low voltage operation

Mano Ibuki, Miyahara Masaya, Matsuzawa Akira

Proceedings of the Society Conference of IEICE   2012 ( 2 )   98 - 98   2012.8

A full 4-channel 6.3Gb/s 60GHz direct-conversion transceiver with low-power analog and digital baseband circuitry Reviewed

Kenichi Okada, Keitarou Kondou, Masaya Miyahara, Masashi Shinagawa, Hiroki Asada, Ryo Minami, Tatsuya Yamaguchi, Ahmed Musa, Yuuki Tsukui, Yasuo Asakura, Shinya Tamonoki, Hiroyuki Yamagishi, Yasufumi Hino, Takahiro Sato, Hironori Sakaguchi, Naoki Shimasaki, Toshihiko Ito, Yasuaki Takeuchi, Ning Li, Qinghong Bu, Rui Murakami, Keigo Bunsen, Kota Matsushita, Makoto Noda, Akira Matsuzawa

Digest of Technical Papers - IEEE International Solid-State Circuits Conference   55   218 - 219   2012

A Study on High Resolution SAR ADC

ASAZAWA Toyoki, TSUNOKAWA Yoshihiro, MIYAHARA Masaya, MATSUZAWA Akira

Technical report of IEICE. ICD   111 ( 352 )   109 - 109   2011.12

High Linearity Open-loop Amplifier for Interpolated Pipeline ADC

HIROOKA Yoshiyuki, LEE Hyunui, MIYAHARA Masaya, MATSUZAWA Akira

Technical report of IEICE. ICD   111 ( 352 )   111 - 111   2011.12

C-12-9 A 0.5V 6-bit 500MS/s Flash ADC using Delay Time Interpolation Technique

Mano Ibuki, Miyahara Masaya, Matsuzawa Akira

Proceedings of the Society Conference of IEICE   2011 ( 2 )   84 - 84   2011.8

C-12-8 An Influence of Parasitic Capacitors on a Performance of Interpolated Pipeline ADC

Lee Hyunui, Miyahara Masaya, Matsuzawa Akira

Proceedings of the Society Conference of IEICE   2011 ( 2 )   83 - 83   2011.8

C-12-7 A High-Speed Clock-Scalable Dynamic Amplifier for Mixed-Signal Applications

Lin James, Miyahara Masaya, Matsuzawa Akira

Proceedings of the Society Conference of IEICE   2011 ( 2 )   82 - 82   2011.8

C-12-19 Setting accuracy and mismatch measurement of MOM capacitors

Tsunokawa Yoshihiro, Lee Hyunui, Miyahara Masaya, Matsuzawa Akira

Proceedings of the Society Conference of IEICE   2011 ( 2 )   94 - 94   2011.8

C-12-40 A Research on Influence of Parasitic Capacitors upon the Performance of a SAR ADC

Lee Seungjong, Paik Daehwa, Miyahara Masaya, Matsuzawa Akira

Proceedings of the IEICE General Conference   2011 ( 2 )   112 - 112   2011.2

C-12-41 THE INTERPOLATION USING DELAY OF COMPARATORS

Mano Ibuki, Miyahara Masaya, Matsuzawa Akira

Proceedings of the IEICE General Conference   2011 ( 2 )   113 - 113   2011.2

A 15.5 dB, Wide Signal Swing, Dynamic Amplifier Using a Common-Mode Voltage Detection Technique Reviewed

James Lin, Masaya Miyahara, Akira Matsuzawa

2011 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)   21 - 24   2011

C-12-8 A Low-kickback and Low-noise Comparator

Yamagishi Toshiaki, Miyahara Masaya, Matsuzawa Akira

Proceedings of the Society Conference of IEICE   2010 ( 2 )   69 - 69   2010.8

C-12-7 A Study of comparator offset calibration using body biasing technique

Asazawa Toyoki, Yamagishi Toshiaki, Miyahara Masaya, Matsuzawa Akira

Proceedings of the Society Conference of IEICE   2010 ( 2 )   68 - 68   2010.8

C-12-6 Study of Influence on SAR ADC by Range of Input Signal

Lee Hyunui, Miyahara Masaya, Matsuzawa Akira

Proceedings of the Society Conference of IEICE   2010 ( 2 )   67 - 67   2010.8

CS-2-2 Low FoM technology for ultra-high speed ADCs

Matsuzawa Akira, Miyahara Masaya

Proceedings of the IEICE General Conference   2010 ( 1 )   "S - 48"-"S-49"   2010.3

Thermal Noise Effects Caused by Settling Time Optimization in Switched-Capacitor Circuits

HUY Dong Ta Ngoc, MIYAHARA Masaya, MATSUZAWA Akira

IEICE technical report   109 ( 214 )   81 - 86   2009.9

An 8-bit 600-MSps Flash ADC Using Interpolating and Background Self-Calibrating Techniques

PAIK Daehwa, ASADA Yusuke, MIYAHARA Masaya, MATSUZAWA Akira

IEICE technical report   109 ( 214 )   99 - 104   2009.9

C-12-57 Noise Effects Caused by Settling Time Optimization in Switched-Capacitor Circuit

Dong Ta Ngoc Huy, Miyahara Masaya, Matsuzawa Akira

Proceedings of the Society Conference of IEICE   2009 ( 2 )   121 - 121   2009.9

C-12-60 Analysis of Body Bias on ADCs for Low Supply Voltage Operation

Ngoc Nguyen Thi Bich, Yoshihara Kei, Miyahara Masaya, Okada Kenichi, Matsuzawa Akira

Proceedings of the Society Conference of IEICE   2009 ( 2 )   124 - 124   2009.9

C-12-63 Study on RC Delay on Reference Circuits Used for Flash-typed ADCs

Paik Daehwa, Miyahara Masaya, Okada Kenichi, Matsuzawa Akira

Proceedings of the IEICE General Conference   2009 ( 2 )   151 - 151   2009.3

BCI-1-9 Recent technology trend of ultra-high speed ADCs and DACs

Matsuzawa Akira, Miyahara Masaya

Proceedings of the IEICE General Conference   2009 ( 1 )   "SS - 26"-"SS-27"   2009.3

Thermal Noise Effects Caused by Settling Time Optimization in Switched-Capacitor Circuits

Huy Dong Ta Ngoc, Miyahara Masaya, Matsuzawa Akira

ITE Technical Report   33 ( 0 )   81 - 86   2009

A 6bit, 7mW, 250fJ, 700MS/s Subranging ADC

Yusuke Asada, Kei Yoshihara, Tatsuya Urano, Masaya Miyahara, Akira Matsuzawa

2009 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC)   141 - 144   2009

C-12-21 A 6.5μW Inverter Based Self Biasing Transceiver

Yamagishi Toshiaki, Matsunaga Kenichi, Dong Ta Ngoc Huy, Miyahara Masaya, Matsuzawa Akira

Proceedings of the Society Conference of IEICE   85 - 85   2009

Development of baseband processing SoC with ultrahigh-speed QAM modem and broadband radio system for demonstration experiment thereof Reviewed

Kazuya Kojima, Yasuhiro Toriyama, Toru Taniguchi, Masaya Miyahara, Akira Matsuzawa

2009 16th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2009   687 - 690   2009

An 8-bit 600-MSps Flash ADC Using Interpolating and Background Self-Calibrating Techniques

PAIK Daehwa, ASADA Yusuke, MIYAHARA Masaya, MATSUZAWA Akira

ITE Technical Report   33 ( 0 )   99 - 104   2009

CK-2-12 Ultra-high speed and low power ADCs and DACs

Matsuzawa Akira, Miyahara Masaya

Proceedings of the Society Conference of IEICE   2008 ( 1 )   "SS - 22"   2008.9

C-12-23 Study of Comparing Double-Tail Latch-Type Comparator with Conventional Comparator Using Pre-Amplifier

Urano Tatsuya, Asada Yusuke, Miyahara Masaya, Okada Kenichi, Matsuzawa Akira

Proceedings of the Society Conference of IEICE   2008 ( 2 )   92 - 92   2008.9

C-12-18 Study of Influence on A/D Converter by Comparator Noise

Yoshihara Kei, Asada Yusuke, Miyahara Masaya, Okada Kenichi, Matsuzawa Akira

Proceedings of the Society Conference of IEICE   2008 ( 2 )   87 - 87   2008.9

C-12-19 Analysis of Parasitic Capacitances Effect in A Capacitive DAC used in SAR ADC

Khoa Vu Minh, Miyahara Masaya, Okada Kenichi, Matsuzawa Akira

Proceedings of the Society Conference of IEICE   88 - 88   2008

C-12-22 Study of High Speed Encoder Using in Flash A/D Converter

Asada Yusuke, Miyahara Masaya, Okada Kenichi, Matsuzawa Akira

Proceedings of the Society Conference of IEICE   2007 ( 2 )   77 - 77   2007.8

The effects of switch resistances on pipelined ADC performances and the optimization for the settling time

ITE technical report   31 ( 34 )   35 - 40   2007.7

A study on the multi-bit-pipelined A/D converter

ENDOU Hiroki, MIYAHARA Masaya, MATSUZAWA Akira

ITE technical report   30 ( 38 )   17 - 22   2006.7

A study on the multi-bit-pipelined A/D converter

ENDOU Hiroki, MIYAHARA Masaya, MATSUZAWA Akira

IEICE technical report   106 ( 189 )   17 - 22   2006.7

A Study on the Effect of CMOS Scaling in Analog Circuit Performance : The Effect of Design Rule on CMOS OPamps and Pipeline ADCs

MIYAHARA Masaya, KURASHINA Takashi, MATSUZAWA Akira

Technical report of IEICE. ICD   105 ( 185 )   25 - 30   2005.7

素子の微細化がアナログCMOS回路に及ぼす影響についての研究--CMOS演算増幅器及びパイプライン型ADC性能のデザインルール依存性

宮原 正也, 倉科 隆, 松澤 昭

映像情報メディア学会技術報告   29 ( 41 )   25 - 30   2005.7

A Study on a pipeline ADC : Basic requirements for capacitance and OP amp

MIYAHARA Masaya, MATSUZAWA Akira

ITE technical report   28 ( 38 )   7 - 12   2004.7

A Study on a pipeline ADC : Basic requirements for capacitance and OP amp

MIYAHARA Masaya, MATSUZAWA Akira

Technical report of IEICE. ICD   104 ( 175 )   7 - 12   2004.7

A Study on Low-Power Design of Crystal Oscillator

MIYAHARA Masaya, ISHIKAWA Masayuki

2004 ( 26 )   47 - 51   2004.3

A 0.5-to-1 V 9-bit 15-to-90 MS/s Digitally Interpolated Pipelined-SAR ADC Using Dynamic Amplifier

James Lin, Zule Xu, Masaya Miyahara, Akira Matsuzawa

2014 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC)  2014  IEEE

A Dual-loop Injection-locked PLL with All-digital Background Calibration System for On-chip Clock Generation

Wei Deng, Ahmed Musa, Teerachot Siriburanon, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa

2014 19TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC)  2014  IEEE

素子の微細化がアナログCMOS回路に及ぼす影響についての研究--CMOS演算増幅器及びパイプライン型ADC性能のデザインルール依存性

宮原 正也, 倉科 隆, 松澤 昭

映像情報メディア学会技術報告  2005.7 

A Study on a pipeline ADC : Basic requirements for capacitance and OP amp

MIYAHARA Masaya, MATSUZAWA Akira

Technical report of IEICE. ICD  2004.7 

A Study on a pipeline ADC : Basic requirements for capacitance and OP amp

MIYAHARA Masaya, MATSUZAWA Akira

ITE technical report  2004.7 

A Study on Low-Power Design of Crystal Oscillator

MIYAHARA Masaya, ISHIKAWA Masayuki

電気学会研究会資料. ECT, 電子回路研究会  2004.3 

A study on the multi-bit-pipelined A/D converter

ENDOU Hiroki, MIYAHARA Masaya, MATSUZAWA Akira

ITE technical report  2006.7 

The effects of switch resistances on pipelined ADC performances and the optimization for the settling time

宮原 正也, 松澤 昭

ITE technical report  2007.7 

A Study on the Effect of CMOS Scaling in Analog Circuit Performance : The Effect of Design Rule on CMOS Opamps and Pipeline ADCs

MIYAHARA Masaya, Kurashina Takashi, MATSUZAWA Akira

Technical report of IEICE. ICD  2005.7 

A study on the multi-bit-pipelined A/D converter

ENDOU Hiroki, MIYAHARA Masaya, MATSUZAWA Akira

Technical report of IEICE. ICD  2006.7 

CK-2-12 Ultra-high speed and low power ADCs and DACs

Matsuzawa Akira, Miyahara Masaya

Proceedings of the Society Conference of IEICE  2008.9 

C-12-19 Analysis of Parasitic Capacitances Effect in A Capacitive DAC used in SAR ADC

Khoa Vu Minh, Miyahara Masaya, Okada Kenichi, Matsuzawa Akira

Proceedings of the Society Conference of IEICE  2008.9 

CK-2-12 Ultra-high speed and low power ADCs and DACs

Matsuzawa Akira, Miyahara Masaya

Proceedings of the Society Conference of IEICE  2008.9 

C-12-23 Study of Comparing Double-Tail Latch-Type Comparator with Conventional Comparator Using Pre-Amplifier

Urano Tatsuya, Asada Yusuke, Miyahara Masaya, Okada Kenichi, Matsuzawa Akira

Proceedings of the Society Conference of IEICE  2008.9 

The Effects of Switch Resistances on Pipelined ADC Performances and the Optimization for the Settling Time

Miyahara Masaya, Matsuzawa Akira

Technical report of IEICE. ICD  2007.7 

C-12-22 Study of High Speed Encoder Using in Flash A/D Converter

Asada Yusuke, Miyahara Masaya, Okada Kenichi, Matsuzawa Akira

Proceedings of the Society Conference of IEICE  2007.8 

BCI-1-9 Recent technology trend of ultra-high speed ADCs and DACs

Matsuzawa Akira, Miyahara Masaya

Proceedings of the IEICE General Conference  2009.3 

BCI-1-9 Recent technology trend of ultra-high speed ADCs and DACs

Matsuzawa Akira, Miyahara Masaya

Proceedings of the IEICE General Conference  2009.3 

BCI-1-9 Recent technology trend of ultra-high speed ADCs and DACs

Matsuzawa Akira, Miyahara Masaya

Proceedings of the IEICE General Conference  2009.3 

C-12-63 Study on RC Delay on Reference Circuits Used for Flash-typed ADCs

Paik Daehwa, Miyahara Masaya, Okada Kenichi, Matsuzawa Akira

Proceedings of the IEICE General Conference  2009.3 

C-12-18 Study of Influence on A/D Converter by Comparator Noise

Yoshihara Kei, Asada Yusuke, Miyahara Masaya, Okada Kenichi, Matsuzawa Akira

Proceedings of the Society Conference of IEICE  2008.9 

Thermal Noise Effects Caused by Settling Time Optimization in Switched-Capacitor Circuits

Huy Dong Ta Ngoc, Miyahara Masaya, Matsuzawa Akira

Technical report of IEICE. ICD  2009.9 

C-12-60 Analysis of Body Bias on ADCs for Low Supply Voltage Operation

Ngoc Nguyen Thi Bich, Yoshihara Kei, Miyahara Masaya, Okada Kenichi, Matsuzawa Akira

Proceedings of the Society Conference of IEICE  2009.9 

An 8-bit 600-MSps Flash ADC Using Interpolating and Background Self-Calibrating Techniques

PAIK Daehwa, ASADA Yusuke, MIYAHARA Masaya, MATSUZAWA Akira

Technical report of IEICE. ICD  2009.9 

C-12-21 A 6.5μW Inverter Based Self Biasing Transceiver

Yamagishi Toshiaki, Matsunaga Kenichi, Dong Ta, Ngoc Huy, Miyahara Masaya, Matsuzawa Akira

Proceedings of the Society Conference of IEICE  2009.9 

C-12-57 Noise Effects Caused by Settling Time Optimization in Switched-Capacitor Circuit

Dong Ta, Ngoc Huy, Miyahara Masaya, Matsuzawa Akira

Proceedings of the Society Conference of IEICE  2009.9 

C-12-7 A Study of comparator offset calibration using body biasing technique

Asazawa Toyoki, Yamagishi Toshiaki, Miyahara Masaya, Matsuzawa Akira

Proceedings of the Society Conference of IEICE  2010.8 

C-12-8 A Low-kickback and Low-noise Comparator

Yamagishi Toshiaki, Miyahara Masaya, Matsuzawa Akira

Proceedings of the Society Conference of IEICE  2010.8 

CS-2-2 Low FoM technology for ultra-high speed ADCs

Matsuzawa Akira, Miyahara Masaya

Proceedings of the IEICE General Conference  2010.3 

C-12-6 Study of Influence on SAR ADC by Range of Input Signal

Lee Hyunui, Miyahara Masaya, Matsuzawa Akira

Proceedings of the Society Conference of IEICE  2010.8 

Thermal Noise Effects Caused by Settling Time Optimization in Switched-Capacitor Circuits

Huy Dong Ta Ngoc, Miyahara Masaya, Matsuzawa Akira

ITE Technical Report  2009.10 

An 8-bit 600-MSps Flash ADC Using Interpolating and Background Self-Calibrating Techniques

PAIK Daehwa, ASADA Yusuke, MIYAHARA Masaya, MATSUZAWA Akira

ITE Technical Report  2009.10 

C-12-7 A High-Speed Clock-Scalable Dynamic Amplifier for Mixed-Signal Applications

Lin James, Miyahara Masaya, Matsuzawa Akira

Proceedings of the Society Conference of IEICE  2011.8 

C-12-8 An Influence of Parasitic Capacitors on a Performance of Interpolated Pipeline ADC

Lee Hyunui, Miyahara Masaya, Matsuzawa Akira

Proceedings of the Society Conference of IEICE  2011.8 

C-12-40 A Research on Influence of Parasitic Capacitors upon the Performance of a SAR ADC

Lee Seungjong, Paik Daehwa, Miyahara Masaya, Matsuzawa Akira

Proceedings of the IEICE General Conference  2011.2 

C-12-41 THE INTERPOLATION USING DELAY OF COMPARATORS

Mano Ibuki, Miyahara Masaya, Matsuzawa Akira

Proceedings of the IEICE General Conference  2011.2 

High Linearity Open-loop Amplifier for Interpolated Pipeline ADC(Poster Session)

HIROOKA Yoshiyuki, LEE Hyunui, MIYAHARA Masaya, MATSUZAWA Akira

Technical report of IEICE. ICD  2011.12 

C-12-25 Consideration of comparators offset calibration method using MOM capacitor under low voltage operation

Mano Ibuki, Miyahara Masaya, Matsuzawa Akira

Proceedings of the Society Conference of IEICE  2012.8 

High Linearity Open-loop Amplifier for Interpolated Pipeline ADC

HIROOKA Yoshiyuki, LEE Hyunui, MIYAHARA Masaya, MATSUZAWA Akira

電子情報通信学会技術研究報告. ICD, 集積回路  2011.12 

A Study on High Resolution SAR ADC(Poster Session)

ASAZAWA Toyoki, TSUNOKAWA Yoshihiro, MIYAHARA Masaya, MATSUZAWA Akira

Technical report of IEICE. ICD  2011.12 

C-12-19 Setting accuracy and mismatch measurement of MOM capacitors

Tsunokawa Yoshihiro, Lee Hyunui, Miyahara Masaya, Matsuzawa Akira

Proceedings of the Society Conference of IEICE  2011.8 

A Study on High Resolution SAR ADC

ASAZAWA Toyoki, TSUNOKAWA Yoshihiro, MIYAHARA Masaya, MATSUZAWA Akira

電子情報通信学会技術研究報告. ICD, 集積回路  2011.12 

検出器のスマート化を目指したネットワーク・アナログデジタルコンバータ(ADC-SiTCP)チップの開発

濱田英太郎, 石綿将邦, 岩瀬和也, 岸下徹一, 佐藤一至, 田中真伸, 宮原正也

日本物理学会秋季大会  2019.9 

高輝度LHC-ATLAS 実験に向けたTGC 検出器の前段読み出し回路の開発

稲熊勇人, 宮原正也

日本物理学会秋季大会  2019.9 

高輝度LHC-ATLAS実験に向けた TGC検出器のタイミング調整用 ASIC量産品の性能評価

山田敏大, 戸本誠, 堀井泰之, 加納勇也, 稲熊勇人, 佐々木修, 田中真伸, 内田智久, 宮原正也, 池野正弘, 他ATLAS日本トリガーグループ

日本物理学会年次大会  2020.3 

高輝度LHC-ATLAS 実験に向けたTGC検出器のタイミング調整用ASICの量産品検査システム構築

山田敏大, 戸本誠, 堀井泰之, 加納勇也, 佐々木修, 田中真伸, 宮原正也, 池野正弘, 他ATLAS日本トリガーグループ

日本物理学会秋季大会  2020.9 

C-12-9 A 0.5V 6-bit 500MS/s Flash ADC using Delay Time Interpolation Technique

Mano Ibuki, Miyahara Masaya, Matsuzawa Akira

Proceedings of the Society Conference of IEICE  2011.8 

Study of low power consumption in a low noise dynamic comparator

Kawashima Satoshi, Miyahara Masaya, Matsuzawa Akira

Proceedings of the Society Conference of IEICE  2013.9 

C-12-47 Enhancing DC Gain of Op-Amp with Complementary lnput

Kaneko Tohru, Miyahara Masaya, Matsuzawa Akira

Proceedings of the IEICE General Conference  2013.3 

C-12-58 A Dual-Loop Injection-Locked PLL with All-Digital PVT Calibration System

Wei Deng, Musa Ahmed, Siributanon Teerachot, Miyahara Masaya, Okada Kenichi, Matsuzawa Akira

Proceedings of the IEICE General Conference  2013.3 

C-12-27 Consideration of High Linearity Gm cell for wide bandwidth Gm-C filter

Yokomizo Shinya, Kaneko Tohru, Miyahara Masaya, Matsuzawa Akira

Proceedings of the Society Conference of IEICE  2014.9 

Investigation of Frequency Characteristic of High Linearity Gm-Cell with Level Shifter

KANEKO Tohru, YOKOMIZO Shinya, MIYAHARA Masaya, MATSUZAWA Akira

IEICE technical report. Computer systems  2014.11 

C-12-15 Quasi-3D Pixel Readout LSIs for Gaseous Particle Detectors with Folding Integration Technique

Nagashio Akira, Sengendo K. P, Miyahara Masaya, Matsuzawa Akira

Proceedings of the Society Conference of IEICE  2014.9 

Radio Receiver Front-End Using Time-Based ADC

TERASAWA Tomohito, KAMIYA Yuji, KAWASHIMA Hiroyuki, IMAI Kenichirou, SUZUKI Masanobu, WATANABE Takamoto, TAGUCHI Nobuyuki, SAWADA Manabu, Hou YU, HIROOKA Yoshiyuki, Ninh HongPHUC, MIYAHARA Masaya, MATSUZAWA Akira

IEICE technical report  2013.10 

4.4 Dependable ADC Technology(4. Variations in Device Characteristics,<Special Survey>Dependable VLSI System)

MATSUZAWA Akira, MIYAHARA Masaya

The journal of Reliability Engineering Association of Japan  2013.12 

Consideration of High Linearity Amplifier with Complementary Input

Kaneko Tohru, Miyahara Masaya, Matsuzawa Akira

Proceedings of the Society Conference of IEICE  2013.9 

ダイナミック動作型積分器を用いたスケーラブルADCの開発

宮原 正也

第8回SOIPIX研究会  2017.6 

C-12-31 Study of calibration of resistance mismatch in Resistor DAC

Xia Yuan, Miyahara Masaya, Matsuzawa Akira

Proceedings of the Society Conference of IEICE  2015.8 

C-12-32 Study of Low-noise Dynamic Comparator using Cross-Coupling Connection

Endo Yukiya, Miyahara Masaya, Matsuzawa Akira

Proceedings of the Society Conference of IEICE  2015.8 

A-1-28 Delta-Sigma Time to Digital Converter Using Charge Pump and SAR ADC

Firdauzi Anugerah, Xu Zule, Miyahara Masaya, Matsuzawa Akira

Proceedings of the IEICE General Conference  2015.2 

C-12-17 Consideration of common-mode voltage stabilization of complementary-input Gm-cell for wide bandwidth filter

Kimura Yuya, Kaneko Tohru, Yokomizo Shinya, Miyahara Masaya, Matsuzawa Akira

Proceedings of the Society Conference of IEICE  2015.8 

C-12-1 Consideration of Enhancing Linearity Technique for Wideband Variable Gain Amplifer

Kaneko Tohru, Miyahara Masaya, Matsuzawa Akira

Proceedings of the IEICE General Conference  2015.2 

C-12-35 A Comparison of Current-steering DAC and Resistor DAC in Low Power Supply Voltage

Kawashima Satoshi, Miyahara Masaya, Matsuzawa Akira

Proceedings of the IEICE General Conference  2015.2 

荷電粒子検出器用ASICの性能評価

山村晴菜, 中野英一, 宇野彰二, 宮原正也

日本物理学会秋季大会  2019.9 

IoTを支える低電力アナログ・デジタル集積回路技術 Invited

電子情報通信学会 総合大会 2019  2019.3 

先端CMOS プロセスを用いたデータコンバータ回路技術のトレンドとその応用 Invited

宮原 正也

日本学術振興会 放射線エレクトロニクスの最前線第186委員会  2019.7 

IoT社会を支える超高速起動・低消費電力水晶発振回路の開発

宮原 正也

第4回TIA光・量子計測シンポジウム  2019.3 

IoT社会を支える超高速起動・低消費電力水晶発振回路の開発

宮原 正也

SATテクノロジー・ショーケース 2019  2019.3 

IoTで変わる社会と最先端技術 Invited

宮原 正也

総合研究大学院大学社会連携事業 「科学と技術をまなぶ」  2019.2 

高輝度 LHC-ATLAS実験に向けたTGC検出器の読み出し回路の放射線対策

稲熊 勇人, 戸本 誠, 堀井 泰之, 川口 智美, 伊藤 秀一, 麻田 春香, 佐々木 修, 田中 真伸, 内田 智久, 宮原 正也, 池野 正弘, 他ATLAS日本トリガーグループ

日本物理学会春季大会,  2019.3 

A 64μs Start-Up 26/40MHz Crystal Oscillator with Negative Resistance Boosting Technique Using Reconfigurable Multi-Stage Amplifier Invited

2018.7 

高輝度 LHC-ATLAS実験に向けた TGC検出器の読み出し回路に搭載するASICの動作検証

伊藤秀一, 戸本誠, 堀井泰之, 稲熊勇人, 佐々木修, 田中真伸, 内田智久, 宮原正也, 池野正弘, 他ATLAS日本トリガーグループ

日本物理学会秋季大会  2018.8 

アナデジ混載集積回路開発時の不良及び対策事例紹介

宮原 正也

第47回 集積回路リテラシー研究会  2017.11 

集積回路研究会優秀若手研究ポスター賞

2009   電子情報通信学会   医療用超低電力センサーテレメトリーLSIの開発

LSIとシステムのワークショップ ICD 優秀ポスターアワード

電子情報通信学会   医療用超低電力センサーテレメトリーLSIの開発

全知を目指すセンサ読み出し集積回路技術に関する研究

2016.10 - 2021.3

日本学術振興会  卓越研究員事業 

A study of adaptive circuits for an energy harvesting power supply system

Grant number：25630140  2013.4 - 2015.3

Japan Society for the Promotion of Science  Grants-in-Aid for Scientific Research Grant-in-Aid for Challenging Exploratory Research  Grant-in-Aid for Challenging Exploratory Research

MIYAHARA Masaya

消費電力１０万分の１の圧力センサー読み出し回路開発－ バッテリーレス，ワイヤレスセンサーネットワークの実現に道開く Newspaper, magazine

日刊工業新聞  2009.10