Updated on 2026/10/23
CMOS/スピントロニクス融合技術を用いた新しい低消費電力技術を開発
2012/12/11
Languages： Japanese
東京工業大学の菅原聡准教授，周藤悠介特任助教，山本修一郎助教らの研究グループは，神奈川科学技術アカデミーと共同で，CMOS/スピントロニクス融合技術を応用した擬似スピンMOSFETを用いて構成できる不揮発性SRAM（NV-SRAM）および不揮発性フリップフロップ(NV-FF)の開発を行った．高精度回路シミュレーションから，擬似スピンMOSFETを用いたこれら記憶回路の優位性・有用性と，不揮発性パワーゲーティング（NVPG）と呼ばれる究極のスタンバイ（待機時）電力削減アーキテクチャへ応用した場合の効果と設計指針を明らかにした．この研究成果は，１２月１０日から米国サンフランシスコで開催される米国IEEE学会主催の電子デバイス技術に関する世界最高峰の国際会議IEDMで発表する．
Doctor of Engineering ( Tokyo Institute of Technology )
Manufacturing Technology (Mechanical Engineering, Electrical and Electronic Engineering, Chemical Engineering) / Electron device and electronic equipment
Life Science / Medical systems
Manufacturing Technology (Mechanical Engineering, Electrical and Electronic Engineering, Chemical Engineering) / Measurement engineering
東京工業大学大学院 理工学研究科 電子物理工学専攻
1994.4 - 1999.3
Country： Japan
Tokyo Institute of Technology School of Engineering
1990.4 - 1994.3
Country： Japan
Institute of Science Tokyo Institute of Integrated Research Specially Appointed Lecturer
2024.10
JOB CORPORATION headquarters Representative Director & President
2022.12
Tokyo Institute of Technology Specially Appointed Lecturer
2013.4 - 2024.9
JOB CORPORATION Research and Development Department Senior Manager
2013.4 - 2022.12
Tokyo Institute of Technology Assistant Professor
2007.4 - 2013.3
-:東京工業大学 助手
1999.4 - 2007.3
-:Tokyo Institute of Technology Research Associate
1999
応用物理学会
IEEE
IEEE
電子情報通信学会
Spin Injection Behavior of CoFe/MgO/Si Tunnel Contacts: Effects of Radical Oxygen Annealing Reviewed
Taiju Akushichi, Yota Takamura, Yusaku Shiotsu, Shuu’ichirou Yamamoto, Satoshi Sugahara
Journal of Electronic Materials 52 ( 10 ) 6902 - 6910 2023.8
Proposal of a new ultralow-voltage-retention SRAM (ULVR-SRAM) cell
Ito Katsutoshi, Shiotsu Yusaku, Yamamoto Shuu'ichirou, Sugahara Satoshi
JSAP Annual Meetings Extended Abstracts 2022.2 2746 - 2746 2022.8
Proposal and performance prediction of a BNN accelerator using ULVR-SRAM
Shiotsu Yusaku, Yamamoto Shuu'ichirou, Sugahara Satoshi
JSAP Annual Meetings Extended Abstracts 2021.2 2648 - 2648 2021.8
Design and analysis of an 8kB ULVR-SRAM macro for near-threshold voltage operations
Hara Takumi, shiotsu yusaku, Yamamoto Shuu'ichirou, sugahara Satoshi
JSAP Annual Meetings Extended Abstracts 2021.2 2647 - 2647 2021.8
Design and analysis of ULVR-SRAM using automatic body-bias control
Hara Takumi, Saito Shuhei, Shiotsu Yusaku, Sugahara Satoshi, Yamamoto Shuu'ichirou
JSAP Annual Meetings Extended Abstracts 2021.2 2646 - 2646 2021.8
Power-gating performance of caches using ultralow-voltage-retention SRAM
Yoshida Hayato, Shiotsu Yusaku, Sugahara Satoshi, Yamamoto Shuu'ichiro
JSAP Annual Meetings Extended Abstracts 2021.1 2351 - 2351 2021.2
Design of ULVR-SRAM cell for near-threshold voltage operation
Hara Takumi, Yamamoto Shuu'ichirou, Shiotsu Yusaku, Sugahara Satoshi, Yoshida Hayato
JSAP Annual Meetings Extended Abstracts 2021.1 2349 - 2349 2021.2
Ultralow-Voltage Retention SRAM With a Power Gating Cell Architecture Using Header and Footer Power-Switches
Hayato Yoshida, Yusaku Shiotsu, Daiki Kitagata, Shuu'ichirou Yamamoto, Satoshi Sugahara
IEEE OPEN JOURNAL OF CIRCUITS AND SYSTEMS 2 520 - 533 2021
Design and analysis of a new ultralow-voltage-retention SRAM cell
Kitagata Daiki, Yoshida Hayato, Shiotsu Yusaku, Yamamoto Shuu'ichirou, Sugahara Satoshi
JSAP Annual Meetings Extended Abstracts 2020.2 1847 - 1847 2020.8
Design and analysis of 8kB SRAM macro using a new ultralow-voltage-retention architecture
Shiotsu Yusaku, Kitagata Daiki, Yamamoto Shuu'ichirou, Sugahara Satoshi
JSAP Annual Meetings Extended Abstracts 2020.2 1848 - 1848 2020.8
Proactive useless data flush architecture for nonvolatile SRAM using magnetic tunnel junctions
Daiki Kitagata, Shuu'ichirou Yamamoto, Satoshi Sugahara
IEICE ELECTRONICS EXPRESS 17 ( 5 ) 2020.3
Design and analysis of virtually nonvolatile SRAM cell for near-threshold voltage operation.
Hara Takumi, Yoshida Hayato, Kitagata Daiki, Yamamoto Shuu'ichirou, Sugahara Satoshi
JSAP Annual Meetings Extended Abstracts 2020.1 2720 - 2720 2020.2
Power-gating performance of SRAM using various retention techniques
Hara Takumi, Yoshida Hayato, Yamamoto Shuu'ichirou, Sugahara Satoshi, Kitagata Daiki
JSAP Annual Meetings Extended Abstracts 2019.2 3110 - 3110 2019.9
Performance of nonvolatile power-gating using VNR-SRAM and NV-SRAM
Kitagata Daiki, Yoshida Hayato, Yamamoto Shuu'ichirou, Sugahara Satoshi
JSAP Annual Meetings Extended Abstracts 2019.2 3108 - 3108 2019.9
Nonvolatile power-gating using NV-SRAM based on the proactive flash of useless data
Sugahara Satoshi, Yamamoto Shuu'ichirou, Kitagata Daiki
JSAP Annual Meetings Extended Abstracts 2019.2 3111 - 3111 2019.9
Design and energy-efficient architectures for nonvolatile static random access memory using magnetic tunnel junctions
Daiki Kitagata, Shuu'ichirou Yamamoto, Satoshi Sugahara
JAPANESE JOURNAL OF APPLIED PHYSICS 58 2019.4
Design and analysis of virtually nonvolatile retention SRAM using dual power-switches
Yoshida Hayato, Yamamoto Shuu'ichiro, Kitagata Daiki, Sugahara Satoshi
JSAP Annual Meetings Extended Abstracts 2019.1 2806 - 2806 2019.2
Low-leakage design of a new piezoelectronic transistor and its SRAM application
Shiotsu Yusaku, Funakubo Hiroshi, Yamamoto Shuu'ichiro, Sugahara Satoshi, Kurosawa Minoru Kuribayashi
JSAP Annual Meetings Extended Abstracts 2019.1 2807 - 2807 2019.2
Design and analysis of virtually nonvolatile retention SRAM using dual-mode inverters
Yoshida Hayato, Kitagata Daiki, Yamamoto Shuu'ichiro, Sugahara Satoshi
JSAP Annual Meetings Extended Abstracts 2018.2 2936 - 2936 2018.9
Energy performance of nonvolatile SRAM using hierarchical store-free shutdown architecture
Kitagata Daiki, Sugahara Satoshi, Yamamoto Shuu'ichirou
JSAP Annual Meetings Extended Abstracts 2018.1 3205 - 3205 2018.3
Static-power reduction ability of nonvolatile SRAM with magnetic tunnel junctions
Kitagata Daiki, Yamamoto Shuu'ichirou, Sugahara Satoshi
JSAP Annual Meetings Extended Abstracts 2017.2 2988 - 2988 2017.8
Analysis of break-even time for nonvolatile SRAM with SOTB technology Reviewed
Daiki Kitagata, Yusuke Shuto, Shuu'ichirou Yamamoto, Satoshi Sugahara
2017 IEEE ELECTRON DEVICES TECHNOLOGY AND MANUFACTURING CONFERENCE (EDTM) 72 - 74 2017
Design and implementation of nonvolatile power-gating SRAM using SOTB technology Reviewed
Yusuke Shuto, Shuu'Ichirou Yamamoto, Satoshi Sugahara
Proceedings of the International Symposium on Low Power Electronics and Design 338 - 343 2016.8
Spin-Transistor Technology for Spintronics/CMOS Hybrid Logic Circuits and Systems Reviewed
Satoshi Sugahara, Yusuke Shuto, Shuu'ichirou Yamamoto
Nanomagnetic Devices and Phenomena for Energy-Efficient Computing 65 - 90 2016.2
New power-gating architectures using nonvolatile retention: Comparative study of nonvolatile power-gating (NVPG) and normally-off architectures for SRAM Reviewed
Yusuke Shuto, Shuu'ichirou Yamamoto, Satoshi Sugahara
2016 INTERNATIONAL CONFERENCE ON MICROELECTRONIC TEST STRUCTURES (ICMTS) 136 - 141 2016
Energy performance of nonvolatile power-gating SRAM using SOTB technology Reviewed
Yusuke Shuto, Shuu'ichirou Yamamoto, Satoshi Sugahara
ESSCIRC CONFERENCE 2016 95 - 98 2016
Energy performance of nonvolatile power-gating SRAM using SOTB technology Reviewed
Yusuke Shuto, Shuu'ichirou Yamamoto, Satoshi Sugahara
2016 46TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE (ESSDERC) 87 - 90 2016
Nonvolatile power-gating architecture for SRAM using SOTB technology Reviewed
Y. Shuto, S. Yamamoto, S. Sugahara
2016 IEEE SILICON NANOELECTRONICS WORKSHOP (SNW) 166 - 167 2016
Quantitative comparison of power-gating architectures for FinFET-based nonvolatile SRAM using spintronics retention technology Reviewed
Yusuke Shuto, Shuu'Ichirou Yamamoto, Satoshi Sugahara
2015 4th Berkeley Symposium on Energy Efficient Electronic Systems, E3S 2015 - Proceedings 2015.11
Field-effect spin-transistors Reviewed
Satoshi Sugahara, Yota Takamura, Yusuke Shuto, Shuu'ichirou Yamamoto
Handbook of Spintronics 1243 - 1279 2015.9
Quantitative comparison of power-gating architectures for nonvolatile SRAM
Shuto Yusuke, Yamamoto Shuu'ichirou, Sugahara Satoshi
JSAP Annual Meetings Extended Abstracts 2015.2 2750 - 2750 2015.8
Comparative study of power-gating architectures for nonvolatile FinFET-SRAM using spintronics-based retention technology Reviewed
Yusuke Shuto, Shuu'ichirou Yamamoto, Satoshi Sugahara
2015 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE) 866 - 871 2015
FinFET-based pseudo-spin-MOSFET and its nonvolatile SRAM application
Shuto Yusuke, Yamamoto Shuu'ichirou, Sugahara Satoshi
JSAP Annual Meetings Extended Abstracts 2014.1 2859 - 2859 2014.3
Near-threshold voltage operation of a nonvolatile SRAM cell based on pseudo-spin-FinFET architecture Reviewed
Y. Shuto, S. Yamamoto, S. Sugahara
2014 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) 2014
0.5V operation and performance of nonvolatile SRAM cell based on pseudo-spin-FinFET architecture Reviewed
Yusuke Shuto, Shuu'ichirou Yamamoto, Satoshi Sugahara
2014 INTERNATIONAL CONFERENCE ON SIMULATION OF SEMICONDUCTOR PROCESSES AND DEVICES (SISPAD) 305 - 308 2014
Comparative study of power-gating architectures for nonvolatile SRAM cells based on spintronics technology Reviewed
Yusuke Shuto, Shuu'ichirou Yamamoto, Satoshi Sugahara
2014 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS) 699 - 702 2014
Nonvolatile flip-flop based on pseudo-spin-transistor architecture and its nonvolatile power-gating applications for low-power CMOS logic Reviewed
Shuu'ichirou Yamamoto, Yusuke Shuto, Satoshi Sugahara
EUROPEAN PHYSICAL JOURNAL-APPLIED PHYSICS 63 ( 1 ) 2013.7
擬似スピンMOSFETを用いた不揮発性デュアルポートSRAMセルの提案とNVPG応用
山本 修一郎, 周藤 悠介, 菅原 聡
応用物理学会学術講演会講演予稿集 2013.1 2739 - 2739 2013.3
ナノCMOS技術を用いた擬似スピンMOSFETおよび不揮発性SRAMセルの性能と設計
山本 修一郎, 菅原 聡, 周藤 悠介
応用物理学会学術講演会講演予稿集 2013.1 2738 - 2738 2013.3
FinFET-based pseudo-spin-transistor: Design and performance Reviewed
Yusuke Shuto, Shuu'Ichirou Yamamoto, Satoshi Sugahara
2013 IEEE International Semiconductor Conference Dresden - Grenoble: Technology, Design, Packaging, Simulation and Test, ISCDG 2013 2013
Nonvolatile Power-Gating Field-Programmable Gate Array Using Nonvolatile Static Random Access Memory and Nonvolatile Flip-Flops Based on Pseudo-Spin-Transistor Architecture with Spin-Transfer-Torque Magnetic Tunnel Junctions Reviewed
Shuu'ichirou Yamamoto, Yusuke Shuto, Satoshi Sugahara
JAPANESE JOURNAL OF APPLIED PHYSICS 51 ( 11 ) 2012.11
擬似スピンMOSFETを用いた不揮発性SRAM:スリープモード動作とその応用
周藤 悠介, 山本 修一郎, 菅原 聡
応用物理学会学術講演会講演予稿集 2012.2 2797 - 2797 2012.8
Evaluation and Control of Break-Even Time of Nonvolatile Static Random Access Memory Based on Spin-Transistor Architecture with Spin-Transfer-Torque Magnetic Tunnel Junctions Reviewed
Yusuke Shuto, Shuu'ichirou Yamamoto, Satoshi Sugahara
JAPANESE JOURNAL OF APPLIED PHYSICS 51 ( 4 ) 2012.4
Static noise margin and power-gating efficiency of a new nonvolatile SRAM cell based on pseudo-spin-transistor architecture Reviewed
Yusuke Shuto, Shuu'ichirou Yamamoto, Satoshi Sugahara
2012 4TH IEEE INTERNATIONAL MEMORY WORKSHOP (IMW) 2012
Analysis of static noise margin and power-gating efficiency of a new nonvolatile SRAM cell using pseudo-spin-MOSFETs Reviewed
Yusuke Shuto, Shuu'ichirou Yamamoto, Satoshi Sugahara
2012 IEEE Silicon Nanoelectronics Workshop, SNW 2012 2012
Nonvolatile flip-flop using pseudo-spin-transistor architecture and its power-gating applications Reviewed
Shuu'Ichirou Yamamoto, Yusuke Shuto, Satoshi Sugahara
IEEE 2012 International Semiconductor Conference Dresden-Grenoble, ISCDG 2012 17 - 20 2012
Nonvolatile power-gating FPGA based on pseudo-spin-transistor architecture with spin-transfer-torque MTJs Reviewed
Shuu'ichirou Yamamoto, Yusuke Shuto, Satoshi Sugahara
Materials Research Society Symposium Proceedings 1430 55 - 60 2012
Nonvolatile delay flip-flop using spin-transistor architecture with spin transfer torque MTJs for power-gating systems Reviewed
S. Yamamoto, Y. Shuto, S. Sugahara
ELECTRONICS LETTERS 47 ( 18 ) 1027 - U1562 2011.9
Nonvolatile delay flip-flop based on spin-transistor architecture and its power-gating applications Reviewed
Shuu'ichirou Yamamoto, Satoshi Sugahara
Japanese Journal of Applied Physics 49 ( 9 ) 2010.9
擬似スピンMOSFETを用いた不揮発性SRAM：ストア時の書き込み電流制御
周藤 悠介, 菅原 聡, 山本 修一郎
応用物理学会学術講演会講演予稿集 2010.2 1825 - 1825 2010.8
擬似スピンMOSFETを用いた不揮発性SRAMと不揮発性DFFのFPGA応用
山本 修一郎, 周藤 悠介, 菅原 聡
応用物理学会学術講演会講演予稿集 2010.2 1824 - 1824 2010.8
擬似スピンMOSFETを用いた不揮発性SRAM：セルリーク電流とBETの削減
周藤 悠介, 山本 修一郎, 菅原 聡
応用物理学会学術講演会講演予稿集 2010.2 2696 - 2696 2010.8
不揮発性メモリ素子を用いた不揮発性/ばらつき補償SRAM技術
菅原 聡, 山本 修一郎, 周藤 悠介
応用物理学会学術講演会講演予稿集 2010.2 169 - 169 2010.8
Nonvolatile static random access memory using resistive switching devices: Variable-transconductance metal-oxide-semiconductor field-effect-transistor approach Reviewed
Shuu'ichirou Yamamoto, Yusuke Shuto, Satoshi Sugahara
Japanese Journal of Applied Physics 49 ( 4 ) 0402091 - 0402093 2010.4
Yusuke Shuto, Yusuke Shuto, Ryosho Nakane, Ryosho Nakane, Wenhong Wang, Wenhong Wang, Hiroaki Sukegawa, Hiroaki Sukegawa, Shuu'ichirou Yamamoto, Shuu'ichirou Yamamoto, Masaaki Tanaka, Masaaki Tanaka, Koichiro Inomata, Koichiro Inomata, Satoshi Sugahara, Satoshi Sugahara
Applied Physics Express 3 2010.1
Nonvolatile static random access memory based on spin-transistor architecture Reviewed
Yusuke Shuto, Shuu'Ichirou Yamamoto, Satoshi Sugahara
Journal of Applied Physics 105 ( 7 ) 2009
Nonvolatile SRAM (NV-SRAM) Using Functional MOSFET Merged with Resistive Switching Devices Reviewed
Shuu'ichirou Yamamoto, Yusuke Shuto, Satoshi Sugahara
PROCEEDINGS OF THE IEEE 2009 CUSTOM INTEGRATED CIRCUITS CONFERENCE 531 - + 2009
ATOMIC LAYER MOCVD OF OXIDE SUPERCONDUCTORS AND DIELECTRICS
High-Temperature Superconductors and Novel Inorganic Materials, NATO ASI Series 3 (eds. by G. Van Tendeloo, E.V. Antipov and S.N. Putilin, Kluwer Academic, Dordorecht) 1999
ATOMIC LAYER MOCVD OF OXIDE SUPERCONDUCTORS AND DIELECTRICS
High-Temperature Superconductors and Novel Inorganic Materials, NATO ASI Series 3 (eds. by G. Van Tendeloo, E.V. Antipov and S.N. Putilin, Kluwer Academic, Dordorecht) 1999
Critical Current Density of YBCO Ultra Thin Films Prepared by Atomic Layer MOCVD
Advances in Superconductivity VII (eds. by K.Ysmafuji and T.Morishita Springer, Tokyo) 1995
Critical Current Density of YBCO Ultra Thin Films Prepared by Atomic Layer MOCVD
Advances in Superconductivity VII (eds. by K.Ysmafuji and T.Morishita Springer, Tokyo) 1995
Design of nonvolatile SRAM using FinFETs for low-voltage operation
山崎修, 塩津勇作, 山本修一郎, 菅原聡
応用物理学会秋季学術講演会講演予稿集(CD-ROM) 83rd 2022
Power-gating performance of ultralow-voltage-retention SRAM for near-threshold-voltage operation
加藤豪人, 塩津勇作, 山本修一郎, 菅原聡
応用物理学会秋季学術講演会講演予稿集(CD-ROM) 83rd 2022
Power-gating performance and architecture of ultralow-voltage-retention SRAM
矢野広気, 塩津勇作, 山本修一郎, 菅原聡
応用物理学会春季学術講演会講演予稿集(CD-ROM) 69th 2022
Energy-efficient operation at energy minimum point for ultralow-voltage-retention SRAM
塩津勇作, 山本修一郎, 菅原聡
応用物理学会春季学術講演会講演予稿集(CD-ROM) 68th 2021
Design methodology of a new piezoelectronic transistor
Shiotsu Yusaku, Yamamoto Shuu'ichiro, Funakubo Hiroshi, Kurosawa Minoru Kuribayashi, Sugahara Satoshi
JSAP Annual Meetings Extended Abstracts 2018.2 2950 - 2950 2018.9
Piezoelectronic magnetoresistive-device and its low-voltage MRAM application
Takamura Yota, Yamamoto Shu'ichiro, Funakubo Hiroshi, Kurosawa Minoru K., Nakagawa Shigeki, Sugahara Satoshi
JSAP Annual Meetings Extended Abstracts 2018.1 3210 - 3210 2018.3
Design of a new piezoelectronic transistor and its device and circuit performances
Shiotsu Yusaku, Yamamoto Shuu'ichiro, Shuto Yusuke, Hunakubo Hiroshi, Kurosawa Minoru, Sugahara Satoshi
JSAP Annual Meetings Extended Abstracts 2018.1 3209 - 3209 2018.3
北形 大樹, 周藤 悠介, 菅原 聡, 山本 修一郎
電子情報通信学会技術研究報告 = IEICE technical report : 信学技報 117 ( 9 ) 51 - 56 2017.4
周藤 悠介, 山本 修一郎, 菅原 聡
電子情報通信学会技術研究報告 = IEICE technical report : 信学技報 112 ( 169 ) 65 - 70 2012.8
Nonvolatile Static Random Access Memory Using Magnetic Tunnel Junctions with Current-Induced Magnetization Switching Architecture
Shuu'ichirou Yamamoto, Satoshi Sugahara
JAPANESE JOURNAL OF APPLIED PHYSICS 48 ( 4 ) 043001/1-7 2009.4
Nonvolatile SRAM architecture using MOSFET-based spin-transistors
Yusuke Shuto, Shuu'ichirou Yamamoto, Satoshi Sugahara
J. Appl. Phys. 105 07C933/1-3 2009
Nonvolatile SRAM and flip-flop architectures using magnetic tunnel junctions with current-induced magnetization switching technology
Shuu'ichirou Yamamoto, Satoshi Sugahara
Jpn. J. Appl. Phys. 48 ( 4 ) 043001-1-7 2009
スピン機能CMOSによる不揮発性高機能・高性能ロジック
山本修一郎, 周藤悠介, 菅原聡
スピントロニクスの基礎と材料・応用技術の最前線 ( 27章 ) 319 - 330 2009
スピン機能MOSFETによる不揮発性ロック 不揮発性パワーゲーティング・ロジックへの応用 不揮発性SRAM/フリップフロップの可能性を検証
菅原聡, 周藤悠介, 山本修一郎
46 - 49 2009
マスタ・スレーブ型マルチプロセッサにおける動的可変優先度バス制御方式とその評価
三宅康夫, 山本修一郎, 前島英雄
電子情報通信学会論文誌 J92-C ( 5 ) 166 - 175 2009
Nonvolatile Static Random Access Memory (NV-SRAM) Using Magnetic Tunnel Junctions with Current-Induced Magnetization Switching Architecture
S. Yamamoto, S. Sugahara
Jpn. J. Appl. Phys. 48 ( 4 ) 043001/1-7 2009
Nonvolatile SRAM architecture using MOSFET-based spin-transistors
Yusuke Shuto, Shuu'ichirou Yamamoto, Satoshi Sugahara
J. Appl. Phys. 105 07C933/1-3 2009
Nonvolatile SRAM and flip-flop architectures using magnetic tunnel junctions with current-induced magnetization switching technology
Shuu'ichirou Yamamoto, Satoshi Sugahara
Jpn. J. Appl. Phys. 48 ( 4 ) 043001-1-7 2009
Fabrication and characterization of 1 k-bit 1T2C-type ferroelectric memory cell array
HS Kim, S Yamamoto, T Ishikawa, T Fuchikami, H Ohki, H Ishiwara
JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS 44 ( 4B ) 2715 - 2721 2005.4
Improved data disturbance effects in 1T2C-type ferroelectric memory array
HS Kim, S Yamamoto, H Ishiwara
JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS 43 ( 5A ) 2558 - 2563 2004.5
Improved data disturbance effects in 1T2C-type ferroelectric memory array
HS Kim, S Yamamoto, H Ishiwara
JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS 43 ( 5A ) 2558 - 2563 2004.5
Fabrication and Characterization of 1k-bit 1T2C-Type Ferroelectric Memory Cell Array
Shuu'ichirou Yamamoto
Extended Abstract of the 2004 International Conference on Solid State Devices and Materials 54 - 55 2004
Improvement of data readout disturbance effect in 1T2C-type ferroelectric memory
HS Kim, S Yamamoto, H Ishiwara
INTEGRATED FERROELECTRICS 67 271 - 280 2004
Fabrication of 1K-bit 1T2C-type ferroelectric memory cell array
S Yamamoto, T Ishikawa, T Fuchikami, HS Kim, K Aizawa, BE Park, T Furukawa, H Ohki, S Kikuchi, H Hoko, H Ishiwara
INTEGRATED FERROELECTRICS 67 281 - 286 2004
Improvement of data readout disturbance effect in 1T2C-type ferroelectric memory
Hyun-Soo Kim, Shuu'ichirou Yamamoto, Hiroshi Ishiwara
Integrated Ferroelectrics 67 271 - 280 2004
Improvement of Data Readout Disturbance Effects in 1T2C-Type Ferroelectric Memory Array
Shuu'ichirou Yamamoto
Symposium Abstracts (The 16th International Symposium on Integrated Ferroelectrics) 2004
1T2C型強誘電体メモリアレイにおけるV/4データ書き込み法の提案
山本修一郎
第51回応用物理学関係連合講演会講演予稿集 2 625 2004
Improvement of Data Readout Disturbance Effects in 1T2C-Type Ferroelectric Memory Array
Shuu'ichirou Yamamoto
Symposium Abstracts (The 16th International Symposium on Integrated Ferroelectrics) 2004
Fabrication and Characterization of 1k-bit 1T2C-Type Ferroelectric Memory Cell Array
Shuu'ichirou Yamamoto
Extended Abstract of the 2004 International Conference on Solid State Devices and Materials 54 - 55 2004
Proposal of a planar 8F(2) 1T2C-type ferroelectric memory cell
S Yamamoto, HS Kim, H Ishiwara
JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS 42 ( 4B ) 2059 - 2062 2003.4
強誘電体を用いたCMOS不揮発性ラッチ回路の消費電力の評価
山本修一郎, 石原宏
第50回応用物理学関係連合講演会 ( 30a-R-11 ) 2003
SPICEによる1T2C型強誘電体メモリアレイの動作解析
石川徹, 山本修一郎, 石原宏
第50回応用物理学関係連合講演会講演予稿集 2 609 2003
強誘電体を用いた不揮発性ＣＭＯＳラッチ回路の特性評価
タンブンイー, 斉藤亮平, 山本修一郎, 石原宏
第64回応用物理学会学術講演会講演予稿集 2 475 2003
Fabrication of 1T2C-Type Ferroelectric Memory Array with Sense Amplifiers
Shuu'ichirou Yamamoto
Journal of Conference Abstracts 8 ( 1 ) 363 2003
1Ｔ2Ｃ型強誘電体メモリセルに対する読み出しディスターブの低減法
金豕ォ季, 山本修一郎, 石原宏
第64回応用物理学会学術講演会講演予稿集 2 476 2003
Fabrication of 1T2C-Type Ferroelectric Memory Cell Array
Book of Abstracts (15th International Conference on Integrated Ferroelectrics) 242 2003
Operation Simulation of an 8F^2^ 1T2C-Type Ferroelectric Memory Array with a Revised Data Writing Method
Book of Abstracts (15th International Conference on Integrated Ferroelectrics) 228 2003
Analysis and Improvement of Data Disturbance Effect in 1T2C type Ferroelectric Memory Cell
KIM Hyun-Soo, YAMAMOTO Shuu'ichirou, ISHIWARA Hiroshi
Technical report of IEICE. SDM 102 ( 732 ) 19 - 24 2003
1Ｔ2Ｃ型強誘電体メモリアレイの読み出し回路の設計と評価
山本修一郎
第64回応用物理学会学術講演会講演予稿集 2 476 2003
Fabrication of 1T2C-Type Ferroelectric Memory Cell Array
Book of Abstracts (15th International Conference on Integrated Ferroelectrics) 242 2003
Operation simulation of an 8F21T2C-type ferroelectric memory array with a revised data writing method
Hyun-Soo Kim, Shuu'ichirou Yamamoto, Hiroshi Ishiwara
Integrated Ferroelectrics 56 1045 - 1054 2003
Fabrication of 1T2C-Type Ferroelectric Memory Array with Sense Amplifiers
Shuu'ichirou Yamamoto
Journal of Conference Abstracts 8 ( 1 ) 363 2003
1T2C型強誘電体メモリアレイに対するデータ書き込みディスターブの低減法
金豕ォ季, 山本修一郎, 石原宏
第50回応用物理学関係連合講演会講演予稿集 2 609 2003
強誘電体を用いた不揮発性CMOSラッチ回路の消費電力の評価
山本修一郎
第50回応用物理学関係連合講演会講演予稿集 2 609 2003
Operation Simulation of an 8F^2^ 1T2C-Type Ferroelectric Memory Array with a Revised Data Writing Method
Book of Abstracts (15th International Conference on Integrated Ferroelectrics) 228 2003
Low-temperature synthesis of SrBi2Ta2O9 thin films with Bi2SiO5-containing seed layers
XS Wang, S Yamamoto, H Ishiwara
JAPANESE JOURNAL OF APPLIED PHYSICS PART 2-LETTERS 41 ( 12B ) L1492 - L1494 2002.12
A novel data writing method in a 1T2C-type ferroelectric memory
Hiroshi Ishiwara, Shuu'ichirou Yamamoto
Facta Universitatis (Nis) - Elec. Energ. 15 ( 1 ) 81 - 92 2002
Analysis of non-volatile latch circuits with ferroelectric-gate field effect transistors for low power and low voltage operation
S Yamamoto, S Inoue, H Ishiwara
2002 23RD INTERNATIONAL CONFERENCE ON MICROELECTRONICS, VOLS 1 AND 2, PROCEEDINGS 2 589 - 592 2002
Proposal of a planar 8F^2^ 1T2C-type ferroelectric memory cell
Shuu'ichirou Yamamoto Hyun-Soo Kim, Hiroshi Ishiwara
Extended Abstract of the 2002 International Conference on Solid State Devices and Materials 622 - 623 2002
A novel data writing method in a 1T2C-type ferroelectric memory
H Ishiwara, S Yamamoto
2002 23RD INTERNATIONAL CONFERENCE ON MICROELECTRONICS, VOLS 1 AND 2, PROCEEDINGS 2 517 - 520 2002
1T2C型強誘電体の高集積化とSPICEによる動作解析
金■玄秀, 山本修一郎, 石原宏
第63回応用物理学会学術講演会講演予稿集 2 448 2002
1T2C型強誘電体メモリアレイにおける書込み・読出しデータディスターブ低減法
山本修一郎, 金, 玄秀 石原宏
第63回応用物理学会学術講演会講演予稿集 2 448 2002
不揮発性強誘電体ラッチ回路の新構成法と低電圧動作解析
山本修一郎, 井上進, 石原宏
電子情報通信学会技術報告 101 ( 719 ) 1 - 6 2002
Proposal of a planar 8F^2^ 1T2C-type ferroelectric memory cell
Shuu'ichirou Yamamoto Hyun-Soo Kim, Hiroshi Ishiwara
Extended Abstract of the 2002 International Conference on Solid State Devices and Materials 622 - 623 2002
A novel data writing method in a 1T2C-type ferroelectric memory
Hiroshi Ishiwara, Shuu'ichirou Yamamoto
Facta Universitatis (Nis) - Elec. Energ. 15 ( 1 ) 81 - 92 2002
FETのゲート容量を考慮した1T2C型強誘電体メモリの新規書込み法の提案と動作解析
山本修一郎, 石原宏
第49回応用物理学関係連合講演会講演予稿集 2 544 2002
A novel data writing method in a 1T2C-type ferroelectric memory
H. Ishiwara, S. Yamamoto
2002 23rd International Conference on Microelectronics, MIEL 2002 - Proceedings 2 517 - 520 2002
A novel simulation program with integrated circuit emphasis (SPICE) model of ferroelectric capacitors using Schmitt trigger circuit
S Yamamoto, T Kato, H Ishiwara
JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS 40 ( 4B ) 2928 - 2934 2001.4
High quality ultrathin La<inf>2</inf>O<inf>3</inf> films for high-k gate insulator
Shun Ichiro Ohmi, Chihiro Kobayashi, Koji Aizawa, Shuu'ichirou Yamamoto, Eisuke Tokumitsu, Hiroshi Ishiwara, Hiroshi Iwai
European Solid-State Device Research Conference 235 - 238 2001.1
Atomic layer-by-layer MOCVD of complex metal oxides and in situ process monitoring
S Yamamoto, S Oda
CHEMICAL VAPOR DEPOSITION 7 ( 1 ) 7 - 18 2001.1
強誘電体キャパシタシミュレーション支援LSIの設計
山本修一郎, 平山智久, 石原宏
電子情報通信学会2001年総合大会講演講演論文集・エレクトロニクス２ 128 2001
強誘電体ゲートFETを用いた不揮発性ラッチ回路の動作解析
井上進, 山本修一郎, 石原宏
第48回応用物理学関係連合講演会講演予稿集 2 549 2001
強誘電体を用いた不揮発性CMOSラッチ回路の新構成法と低電圧動作解析
山本修一郎, 石原宏
第62回応用物理学会学術講演会講演予稿集 2 381 2001
1T2C型強誘電体メモリの周辺回路の設計
平山智久, 山本修一郎, 石原宏
電子情報通信学会2001年エレクトロニクスソサイエティ大会講演論文集２ 97 2001
シュミットトリガ回路を用いた回路要素並列型強誘電体SPICEモデルの構築
山本修一郎, 石原宏
第60回応用物理学会学術講演会講演予稿集 447 2000
HSPICE Simulation of Transistor-type Ferroelectric Memory
Extended Abstracts (The 47th Spring Meeting,2000) 541 2000
Building of Parallel-element Ferroelectric Capacitor Model Using Schmitt Trigger Circuit
Extended Abstracts (The 61th Autumn Meeting, 2000) 447 2000
A Novel SPICE Model of Ferroelectric Capacitors Using Schmitt Trigger Circuit
Shuu'ichirou Yamamoto, Takumi Kato, Hiroshi Ishiwara
Extended Abstract of the 2000 International Conference on Solid State Devices and Materials 270 - 271 2000
A Novel SPICE Model of Ferroelectric Capacitors Using Schmitt Trigger Circuit
Shuu'ichirou Yamamoto, Takumi Kato, Hiroshi Ishiwara
Extended Abstract of the 2000 International Conference on Solid State Devices and Materials 270 - 271 2000
HSPICEによるトランジスタ型強誘電体メモリの動作解析
加藤匠, 高原淳, 山本修一郎, 小笠原悟, 徳光永輔, 石原宏
第47回応用物理学関係連合講演会予稿集 541 2000
Reproducible growth of metalorganic chemical vapor deposition derived YBa2Cu3Ox thin films using ultrasonic gas concentration analyzer
S Yamamoto, K Nagata, S Sugai, A Sengoku, Y Matsukawa, T Hattori, S Oda
JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS 38 ( 8 ) 4727 - 4732 1999.8
Reproducible growth of metalorganic chemical vapor deposition derived YBa2Cu3Ox thin films using ultrasonic gas concentration analyzer
S Yamamoto, K Nagata, S Sugai, A Sengoku, Y Matsukawa, T Hattori, S Oda
JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS 38 ( 8 ) 4727 - 4732 1999.8
In situ growth monitoring during metalorganic chemical vapor deposition of YBa2Cu3Ox thin films by spectroscopic ellipsometry
S Yamamoto, S Sugai, Y Matsukawa, A Sengoku, H Tobisaka, T Hattori, S Oda
JAPANESE JOURNAL OF APPLIED PHYSICS PART 2-LETTERS 38 ( 6AB ) L632 - L635 1999.6
In situ growth monitoring during metalorganic chemical vapor deposition of YBa2Cu3Ox thin films by spectroscopic ellipsometry
S Yamamoto, S Sugai, Y Matsukawa, A Sengoku, H Tobisaka, T Hattori, S Oda
JAPANESE JOURNAL OF APPLIED PHYSICS PART 2-LETTERS 38 ( 6AB ) L632 - L635 1999.6
強誘電体の過渡応答SPICEモデル(II)
加藤匠, 山本修一郎, 石原宏
第47回応用物理学関係連合講演会講演予稿集 461 1999
atomic controlled interface of superconductors
Shuu'ichirou Yamamoto, Shunri Oda
Extended Abstracts of Special Session for Superconducting Devices 25 - 30 1998
原子層レベルで制御する超伝導界面
超伝導素子研究開発プロジェクト完了報告会紀要 25 - 30 1998
Anomalous current-voltage characteristics along the c-axis in YBaCuO thin films prepared by MOCVD and AFM lithography
S Yamamoto, A Kawaguchi, S Oda
PHYSICA C 293 ( 1-4 ) 244 - 248 1997.12
Anomalous current-voltage characteristics along the c-axis in YBaCuO thin films prepared by MOCVD and AFM lithography
S Yamamoto, A Kawaguchi, S Oda
PHYSICA C 293 ( 1-4 ) 244 - 248 1997.12
Atomic layer-by-layer epitaxy of oxide superconductors by MOCVD
S Yamamoto, A Kawaguchi, K Nagata, T Hattori, S Oda
APPLIED SURFACE SCIENCE 112 30 - 37 1997.3
Junction formation in YBaCuO thin films by scanning probe technologies
S Yamamoto, T Watanabe, S Oda
JOURNAL OF LOW TEMPERATURE PHYSICS 106 ( 3-4 ) 423 - 432 1997.2
Preparation of thin films of YBa2Cu3Ox with a smooth surface by atomic layer MOCVD
S Yamamoto, A Kawaguchi, S Oda
MATERIALS SCIENCE AND ENGINEERING B-SOLID STATE MATERIALS FOR ADVANCED TECHNOLOGY 41 ( 1 ) 87 - 92 1996.10
Preparation of thin films of YBa2Cu3Ox with a smooth surface by atomic layer MOCVD
S Yamamoto, A Kawaguchi, S Oda
MATERIALS SCIENCE AND ENGINEERING B-SOLID STATE MATERIALS FOR ADVANCED TECHNOLOGY 41 ( 1 ) 87 - 92 1996.10
ATOMIC LAYER-BY-LAYER MOCVD OF OXIDE SUPERCONDUCTORS
S ODA, S YAMAMOTO, A KAWAGUCHI
JOURNAL DE PHYSIQUE IV 5 ( C5 ) 379 - 390 1995.6
SUPERCONDUCTIVITY AND SURFACE-MORPHOLOGY OF YBCO THIN-FILMS PREPARED BY METALORGANIC CHEMICAL-VAPOR-DEPOSITION
S ODA, H ZAMA, S YAMAMOTO
IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY 5 ( 2 ) 1801 - 1804 1995.6
Atomic Layer-by-Layer MOCVD of Oxide Superconductors
Shunri Oda Shuu'ichirou Yamamoto, Atsushi Kawaguchi
Journal de Physique IV C5 379 - 390 1995
STM/AFM Fabricated Junctions of YBaCuO Films
Shuu'ichirou Yamamoto, Hideaki Suzuki Tomotaka Watanabe, Atsushi Kawaguchi, Takeo Hattori, Shunri Oda
Extended Abstracts of 5th International Superconductive Electronics Conference 93 - 95 1995
STM/AFM Fabricated Junctions of YBaCuO Films
Shuu'ichirou Yamamoto, Hideaki Suzuki Tomotaka Watanabe, Atsushi Kawaguchi, Takeo Hattori, Shunri Oda
Extended Abstracts of 5th International Superconductive Electronics Conference 93 - 95 1995
Atomic layer controlled metalorganic chemical vapor deposition of superconducting YBa2Cu3Ox films
Shunri Oda, Hideaki Zama, Shuuichirou Yamamoto
Journal of Crystal Growth 145 ( 1-4 ) 232 - 236 1994.12
ATOMIC LAYER CONTROLLED METALORGANIC CHEMICAL-VAPOR-DEPOSITION OF SUPERCONDUCTING YBA2CU3OX FILMS
S ODA, H ZAMA, S YAMAMOTO
JOURNAL OF CRYSTAL GROWTH 145 ( 1-4 ) 232 - 236 1994.12
Atomic Layer Metalorganic Chemical Vapor Deposition of YBa_2_Cu_3_O_X_ with In Situ Optical Reflectance Measurement
Shunri Oda Hideaki Zama, Shuu'ichirou Yamamoto
Proceedings of the 7th Topical Meeting on Crystal Growth Mechanism 285 - 290 1994
Atomic Layer Metalorganic Chemical Vapor Deposition of YBa_2_Cu_3_O_X_ with In Situ Optical Reflectance Measurement
Shunri Oda Hideaki Zama, Shuu'ichirou Yamamoto
Proceedings of the 7th Topical Meeting on Crystal Growth Mechanism 285 - 290 1994
Nonvolatile power-gating microprocessor concepts using nonvolatile SRAM and flip-flop
International Symposium on Silicon Nano Devices in 2030 2009
Fabrication and characterization of pseudo-spin-MOSFETs
Intl. Conf. Silicon Nano Devices in 2030 2009
Nonvolatile power-gating microprocessor concepts using nonvolatile SRAM and flip-flop
International Symposium on Silicon Nano Devices in 2030 2009
擬似スピンMOSFETを用いた不揮発性SRAM：電源遮断動作消費電力の評価
平成21年秋季 第70回応用物理学会学術講演会 2009
Nonvolatile SRAM(NV-SRAM) Using Functional MOSFET Merged with Resistive Switching Devices
Proceedings of IEEE 2009 Custom Integrated Circuits Conference (CICC) 2009
Analysis and design of nonvolatile SRAM using spintronics technology
Non-volatile Memory Technology Symposium 2009 (NVMTS09) 2009
擬似スピンMOSFETを用いた不揮発性DFF：バルーンDFFとの比較
第70回応用物理学会学術講演会 2009
Spin-RAM/ReRAM技術を用いた機能MOSFETとその不揮発性SRAM/フリップフロップへの応用
平成21年秋季 第70回応用物理学会学術講演会 2009
Analysis and Design of Nonvolatile SRAM Using MOSFET-Based Spin-Transistors
Intermag 2009 2009
マイクロプロセッサにおけるエマージングメモリデバイスへの期待
第70回応用物理学会学術講演会 2009
ノンポーラ型抵抗変化素子のSPICEモデル
第56回応用物理学関連連合講演会 2009
抵抗変化素子を用いたFunctional MOSFET/CMOS
第56回応用物理学関連連合講演会 2009
Nonvolatile delay flip-flop using magnetic tunnel junctions with current-induced magnetization switching architecture
IEEE International Magnetics Conference 2009
スピン注入磁化反転MTJを用いた不揮発性Dフリップフロップ
第56回応用物理学関係連合講演会 2009
擬似スピンMOSFETを用いた不揮発性SRAMの提案と解析
第13回半導体スピン工学の基礎と応用(PASPS-13) 2009
ノンポーラ型抵抗変化素子を用いた不揮発性SRAM
第56回応用物理学関連連合講演会 2009
Pseudo-spin-MOSFETを用いた不揮発性SRAM：情報ストア動作解析
第56回応用物理学関連連合講演会 2009
Variability-Tolerant CMOS Gates Using Functional MOSFETs with Resistive Switching Devices
Extended Abstracts of the 2009 International Conference on Solid State Devices and Materials 2009
Analysis and Design of Nonvolatile SRAM Using MOSFET-Based Spin-Transistors
Intermag 2009 2009
Nonvolatile delay flip-flop using magnetic tunnel junctions with current-induced magnetization switching architecture
IEEE International Magnetics Conference 2009
Variability-Tolerant CMOS Gates Using Functional MOSFETs with Resistive Switching Devices
Extended Abstracts of the 2009 International Conference on Solid State Devices and Materials 2009
Analysis and design of nonvolatile SRAM using spintronics technology
Non-volatile Memory Technology Symposium 2009 (NVMTS09) 2009
Nonvolatile SRAM(NV-SRAM) Using Functional MOSFET Merged with Resistive Switching Devices
Proceedings of IEEE 2009 Custom Integrated Circuits Conference (CICC) 2009
Fabrication and characterization of pseudo-spin-MOSFETs
Intl. Conf. Silicon Nano Devices in 2030 2009
Operating analysis of pseudo-spin-MOSFETs using MTJ with current-induced magnetization switching
The 55th Spring Meeting, 2008; The Japan Society of Applied Physics and Related Scieties 2008
スピン機能MOSFETによるスピントランジスタ・エレクトロニクス
応用物理学会応用電子物性分科会・スピントロニクス研究会共同主催研究会 2008
スピン機能MOSFETを用いた不揮発性高機能・高性能ロジック
応用物理学会応用電子物性分科会・スピントロニクス研究会例会 2008
Analysis and design of nonvolatile SRAM using magnetic tunnel junctions with current-induced magnetization switching technology
53rd Annual Conference on Magnetism and Magnetic Materials (MMM2008) 2008
Novel nonvolatile SRAM architecture using MOSFET-based spin-transistors
53rd Annual Conference on Magnetism and Magnetic Materials (MMM2008) 2008
スピン注入磁化反転MTJを用いた不揮発性SRAM：通常動作時消費電力の削減
第69回応用物理学会学術講演会 2008
スピン注入磁化反転MTJを用いた不揮発性SRAM：Vhalfの影響
第55回応用物理学会関連連合講演会 2008
スピンMOSFET を用いたスピントランジスタ・エレクトロニクス
第69回応用物理学会学術講演会 2008
マスタ・スレーブ型マルチプロセッサにおける動的可変優先度バス制御方式とその評価
2008年電子情報通信学会エレクトロニクスソサイエティ大会 2008
スピン注入磁化反転MTJを用いた不揮発性SRAM：仮想接地セルアーキテクチャ
第55回応用物理学会関連連合講演会 2008
スピン注入磁化反転MTJを用いたpseudo-spin-MOSFETの動作解析
第55回応用物理学関係連合講演会 2008
Analysis and design of nonvolatile SRAM using magnetic tunnel junctions with current-induced magnetization switching technology
53rd Annual Conference on Magnetism and Magnetic Materials (MMM2008) 2008
Novel nonvolatile SRAM architecture using MOSFET-based spin-transistors
53rd Annual Conference on Magnetism and Magnetic Materials (MMM2008) 2008
Application of pseudo spin-MOSFET/spin-MOSFET for non-volatile SRAM/latch circuits
The 68th Autumn Meeting, 2007; The Japan Society of Applied Physics 2007
Proposal and theoretical analysis of pseudo spin-MOSFETs using MTJ devices
The 68th Autumn Meeting, 2007; The Japan Society of Applied Physics 2007
Nonvolatile SRAM and flip-flop architectures using magnetic tunnel junctions with current-induced magnetization switching technology
52nd Annual Conf. on Magnetism and Magnetic Materials 2007
強磁性トンネル接合を用いたpseudo spin-MOSFETの提案と理論解析
第68回応用物理学会学術講演会 2007
Nonvolatile SRAM and flip-flop architectures using magnetic tunnel junctions with current-induced magnetization switching technology
52nd Annual Conf. on Magnetism and Magnetic Materials 2007
スピン注入磁化反転MTJを用いた不揮発性SRAM/ラッチ回路
第68回応用物理学会学術講演会 2007
pseudo spin-MOSFET/spin-MOSFETの不揮発性SRAM/ラッチ回路への応用
第68回応用物理学会学術講演会 2007
Non-volatile SRAM/latch circuits using MTJ devices with spin transfer torque magnetization switching
The 68th Autumn Meeting, 2007; The Japan Society of Applied Physics 2007
1T2C型強誘電体メモリアレイの作製と評価
第65回応用物理学会学術講演会講演予稿集 2004
research and development of next generation ferro-electric memory
Grant type：Competitive
次世代強誘電体メモリの研究開発
Grant type：Competitive
