応用物理学会   理事  

2016.3 - 2018.3   

SSDM   論文委員長  

2016   

VLSI Symposium on Technology   General Chair  

2015   

  VLSI Symposium on Technology, Program Chair  

2013   

IEC TC91国内委員会   委員長  

2012.4   

応用物理学会シリコンテクノロジー分科会   幹事長  

2011.4 - 2013.3   

日本学術振興会シリコン超集積システム第165委員会   委員長  

2009.11 - 2022.3   

IEDM   Executive Committee Member  

2003 - 2009   

IEEE Electron Device Society   Elected AdCom Member  

2001 - 2006   

電子情報通信学会シリコンデバイス・材料研究会   委員  

1999   

Reliability improvement of InGaO x FETs by adding Zn in atomic layer deposition process

Kota Sakai, Kaito Hikake, Sung-hun Kim, Yuki Itoya, Takuya Saraya, Toshiro Hiramoto, Masaharu Kobayashi

Japanese Journal of Applied Physics   2025.10

Nanosheet oxide semiconductor FETs with ALD InZnO x compared to InGaO x

Sung-Hun Kim, Kaito Hikake, Zhuo Li, Yuki Itoya, Kota Sakai, Takuya Saraya, Toshiro Hiramoto, Masaharu Kobayashi

Japanese Journal of Applied Physics   2025.3

Demonstration of superior UIS robustness of 3300 V scaled IGBT by non-proportional scaling methods

Xiang Zhou, Wataru Saito, Toshiro Hiramoto

Japanese Journal of Applied Physics   2025.3

Enhanced reliability of ferroelectric Hf0.5Zr0.5O2 capacitors by bottom electrode surface oxidation

Yuki Itoya, Takuya Saraya, Toshiro Hiramoto, Masaharu Kobayashi

Japanese Journal of Applied Physics   2025.2

Indexing Current–Voltage Characteristics Using a Hash Function

T. Tanamoto, S. Furukawa, R. Kitahara, T. Mizutani, K. Ono, T. Hiramoto

IEEE Transactions on Electron Devices   2025

Gate Voltage Dependence of MOSFET Random Telegraph Noise Amplitude at Room and Cryogenic Temperatures

Kiyoshi Takeuchi, Tomoko Mizutani, Takuya Saraya, Hiroshi Oka, Takahiro Mori, Masaharu Kobayashi, Toshiro Hiramoto

IEEE Journal of the Electron Devices Society   2025

Cryogenic threshold voltage and on-current variability comparative analysis of same-fab 65 nm bulk and fully depleted silicon-on-insulator metal–oxide–semiconductor field-effect transistors

Zihao Liu, Tomoko Mizutani, Kiyoshi Takeuchi, Takuya Saraya, Hiroshi Oka, Takahiro Mori, Masaharu Kobayashi, Toshiro Hiramoto

Japanese Journal of Applied Physics   2024.12

High-Field Transport and Statistical Variability of Nanosheet Oxide Semiconductor FETs With Channel Length Scaling

Xingyu Huang, Kaito Hikake, Sung-Hun Kim, Kota Sakai, Zhuo Li, Tomoko Mizutani, Takuya Saraya, Toshiro Hiramoto, Takanori Takahashi, Mutsunori Uenuma, Yukiharu Uraoka, Masaharu Kobayashi

IEEE Transactions on Electron Devices   2024.12

Robust reverse bias safe operating area and improved electrical performance in 3300 V non-proportionally scaled insulated gate bipolar transistors

Xiang Zhou, Munetoshi Fukui, Kiyoshi Takeuchi, Takuya Saraya, Wataru Saito, Toshiro Hiramoto

Japanese Journal of Applied Physics   2024.2

Oxide-semiconductor channel ferroelectric field-effect transistors for high-density memory applications: 3D NAND operation and the potential impact of in-plane polarization

Junxiang Hao, Xiaoran Mei, Takuya Saraya, Toshiro Hiramoto, Masaharu Kobayashi

Japanese Journal of Applied Physics   2024.1

A Nanosheet Oxide Semiconductor FET Using ALD InGaOx Channel for 3-D Integrated Devices

Kaito Hikake, Zhuo Li, Junxiang Hao, Chitra Pandy, Takuya Saraya, Toshiro Hiramoto, Takanori Takahashi, Mutsunori Uenuma, Yukiharu Uraoka, Masaharu Kobayashi

IEEE Transactions on Electron Devices   1 - 7   2024

Energy-Efficient Annealing Process of Ferroelectric Hf0.5Zr0.5O2 Capacitor Using Ultraviolet-LED for Green Manufacturing

Hirotaka Yamada, Satoru Furue, Takehiko Yokomori, Yuki Itoya, Takuya Saraya, Toshiro Hiramoto, Masaharu Kobayashi

IEEE Journal of the Electron Devices Society   2024

Superior Turn-Off dV/dt Controllability From Suppression of Dynamic Avalanche in 3300V Scaled IGBTs

Xiang Zhou, Munetoshi Fukui, Kiyoshi Takeuchi, Takuya Saraya, Toshiro Hiramoto

IEEE Journal of the Electron Devices Society   2024

A Nanosheet Oxide Semiconductor FET Using ALD InGaOx Channel and InSnOx Electrode with Normally-off Operation, High Mobility and Reliability for 3D Integrated Devices

Kaito Hikake, Zhuo Li, Junxiang Hao, Chitra Pandy, Takuya Saraya, Toshiro Hiramoto, Takanori Takahashi, Mutsunori Uenuma, Yukiharu Uraoka, Masaharu Kobayashi

2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)   2023.6

Device modeling of oxide–semiconductor channel antiferroelectric FETs using half-loop hysteresis for memory operation

Xingyu Huang, Yuki Itoya, Zhuo Li, Takuya Saraya, Toshiro Hiramoto, Masaharu Kobayashi

Japanese Journal of Applied Physics   2023.4

MOSFET series resistance extraction at cryogenic temperatures

Kiyoshi Takeuchi, Tomoko Mizutani, Takuya Saraya, Hiroshi Oka, Takahiro Mori, Masaharu Kobayashi, Toshiro Hiramoto

Japanese Journal of Applied Physics   2023.4

Pixel-Parallel Three-Layer Stacked CMOS Image Sensors Using Double-Sided Hybrid Bonding of SOI Wafers

Masahide Goto, Yuki Honda, Masakazu Nanba, Yoshinori Iguchi, Takuya Saraya, Masaharu Kobayashi, Eiji Higurashi, Hiroshi Toshiyoshi, Toshiro Hiramoto

IEEE Transactions on Electron Devices   70 ( 9 )   4705 - 4711   2023

Mesoscopic-scale grain formation in HfO2-based ferroelectric thin films and its impact on electrical characteristics

Masaharu Kobayashi, Jixuan Wu, Yoshiki Sawabe, Saraya Takuya, Toshiro Hiramoto

Nano Convergence   9 ( 1 )   2022.11

On the thickness dependence of the polarization switching kinetics in HfO2-based ferroelectric

Yoshiki Sawabe, Takuya Saraya, Toshiro Hiramoto, Chun-Jung Su, Vita Pi-Ho Hu, Masaharu Kobayashi

Applied Physics Letters   2022.8

A 3D Vertical-Channel Ferroelectric/Anti-Ferroelectric FET With Indium Oxide

Zhuo Li, Jixuan Wu, Xiaoran Mei, Xingyu Huang, Takuya Saraya, Toshiro Hiramoto, Takanori Takahashi, Mutsunori Uenuma, Yukiharu Uraoka, Masaharu Kobayashi

IEEE Electron Device Letters   43 ( 8 )   1227 - 1230   2022.8

A Vertical Channel Ferroelectric/Anti-Ferroelectric FET with ALD InOx and Field-Induced Polar-Axis Alignment for 3D High-Density Memory

Zhuo Li, Jixuan Wu, Xiaoran Mei, Xingyu Huang, Takuya Saraya, Toshiro Hiramoto, Takanori Takahashi, Mutsunori Uenuma, Yukiharu Uraoka, Masaharu Kobayashi

2022 IEEE Silicon Nanoelectronics Workshop (SNW)   2022.6

Effect of percolation path on temperature dependence of threshold voltage variability in bulk MOSFETs

Tomoko Mizutani, Kiyoshi Takeuchi, Takuya Saraya, Hiroshi Oka, Takahiro Mori, Masaharu Kobayashi, Toshiro Hiramoto

Japanese Journal of Applied Physics   2022.5

Cause analysis of width-dependence of on-current variability in thin gate-all-around silicon nanowire MOSFET

Zihao Liu, Tomoko Mizutani, Takuya Saraya, Masaharu Kobayashi, Toshiro Hiramoto

Japanese Journal of Applied Physics   2022.5

A simulation study on memory characteristics of InGaZnO-channel ferroelectric FETs with 2D planar and 3D structures

Fei Mo, Xiaoran Mei, Takuya Saraya, Toshiro Hiramoto, Masaharu Kobayashi

Japanese Journal of Applied Physics   61 ( SC )   SC1013 - SC1013   2022.5

Estimation of minimum operating voltage in fully depleted SOI SRAM cells using gamma distribution

Hongkuan Yu, Tomoko Mizutani, Kiyoshi Takeuchi, Takuya Saraya, Masaharu Kobayashi, Toshiro Hiramoto

Japanese Journal of Applied Physics   2022.5

A robust single device MOSFET series resistance extraction method considering horizontal-field-dependent mobility

Kiyoshi Takeuchi, Tomoko Mizutani, Takuya Saraya, Masaharu Kobayashi, Toshiro Hiramoto

Japanese Journal of Applied Physics   2022.5

Corrigendum: “A robust single device MOSFET series resistance extraction method considering horizontal-field-dependent mobility” [Jpn. J. Appl. Phys. 61, SC1016 (2022)]

Kiyoshi Takeuchi, Tomoko Mizutani, Takuya Saraya, Masaharu Kobayashi, Toshiro Hiramoto

Japanese Journal of Applied Physics   61 ( 4 )   049301 - 049301   2022.4

A Threshold Voltage Definition Based on a Standardized Charge Versus Voltage Relationship

Kiyoshi Takeuchi, Masaharu Kobayashi, Toshiro Hiramoto

IEEE Transactions on Electron Devices   2022.3

Efficient Erase Operation by GIDL Current for 3D Structure FeFETs with Gate Stack Engineering and Compact Long-term Retention Model

Fei Mo, Jiawen Xiang, Xiaoran Mei, Yoshiki Sawabe, Takuya Saraya, Toshiro Hiramoto, Chun-Jung Su, Vita Pi-Ho Hu, Masaharu Kobayashi

IEEE Journal of the Electron Devices Society   1 - 1   2022

3-Layer Stacking Technology with Pixel-Wise Interconnections for Image Sensors Using Hybrid Bonding of Silicon-on-Insulator Wafers Mediated by Thin Si Layers

Masahide Goto, Yuki Honda, Masakazu Nanba, Yoshinori Iguchi, Eiji Higurashi, Takuya Saraya, Masaharu Kobayashi, Hiroshi Toshiyoshi, Toshiro Hiramoto

Proceedings - Electronic Components and Technology Conference   2022-May   122 - 125   2022

3-Layer Stacked Pixel-Parallel CMOS Image Sensors Using Hybrid Bonding of SOI Wafers

Masahide Goto, Yuki Honda, Masakazu Nanba, Yoshinori Iguchi, Takuya Saraya, Masaharu Kobayashi, Eiji Higurashi, Hiroshi Toshiyoshi, Toshiro Hiramoto

IS and T International Symposium on Electronic Imaging Science and Technology   34 ( 7 )   2022

Monolithic Integration of Oxide Semiconductor FET and Ferroelectric Capacitor Enabled by Sn-Doped InGaZnO for 3-D Embedded RAM Application

Jixuan Wu, Fei Mo, Takuya Saraya, Toshiro Hiramoto, Mototaka Ochi, Hiroshi Goto, Masaharu Kobayashi

IEEE Transactions on Electron Devices   68 ( 12 )   6617 - 6622   2021.12

Variability characteristics and corner effects of gate-all-around (GAA) p-type poly-Si junctionless nanowire/nanosheet transistors

Min-Ju Ahn, Takuya Saraya, Masaharu Kobayashi, Toshiro Hiramoto

Japanese Journal of Applied Physics   60   2021.5

TCAD validation of an intercept-at-zero-gate-length MOSFET series resistance extraction method

Kiyoshi Takeuchi, Tomoko Mizutani, Takuya Saraya, Masaharu Kobayashi, Toshiro Hiramoto

VLSI-TSA 2021 - 2021 International Symposium on VLSI Technology, Systems and Applications, Proceedings   2021.4

Subthreshold Swing in Silicon Gate-All-Around Nanowire MOSFET at Cryogenic Temperature

Shohei Sekiguchi, Min-Ju Ahn, Takuya Saraya, Masaharu Kobayashi, Toshiro Hiramoto

2021 5th IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2021   2021.4

Accurate TCAD simulation of trench-gate IGBTs and its application to prediction of carrier lifetime requirements for future scaled devices

M. Watanabe, N. Shigyo, T. Hoshii, K. Furukawa, K. Kakushima, K. Satoh, T. Matsudai, T. Saraya, T. Takakura, I. Muneta, H. Wakabayashi, A. Nakajima, S. Nishizawa, K. Tsutsui, T. Hiramoto, H. Ohashi, H. Iwai

2021 5th IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2021   2021.4

Design space exploration of hysteretic negative capacitance ferroelectric FETs based on static solutions of Landau-Khalatnikov model for nonvolatile memory applications

Kiyoshi Takeuchi, Masaharu Kobayashi, Toshiro Hiramoto

Japanese Journal of Applied Physics   60 ( 3 )   2021.3

Study on the Roles of Charge Trapping and Fixed Charge on Subthreshold Characteristics of FeFETs

C. Jin, C. J. Su, Y. J. Lee, P. J. Sung, T. Hiramoto, M. Kobayashi

IEEE Transactions on Electron Devices   68 ( 3 )   1304 - 1312   2021.3

Ultrathin MoS2-Channel FeFET Memory with Enhanced Ferroelectricity in HfZrO2 and Body-Potential Control

Jiawen Xiang, Wen Hsin Chang, Takuya Saraya, Toshiro Hiramoto, Toshifumi Irisawa, Masaharu Kobayashi

IEEE Journal of the Electron Devices Society   10   1 - 1   2021

Reconfigurable Multivalue Logic Functions of a Silicon Ellipsoidal Quantum-Dot Transistor Operating at Room Temperature

Youngmin Lee, Jin Woo Lee, Sejoon Lee, Toshiro Hiramoto, Kang L. Wang

ACS Nano   2021

A first-principles study on ferroelectric phase formation of Si-doped HfO2 through nucleation and phase transition in thermal process

Jixuan Wu, Fei Mo, Takuya Saraya, Toshiro Hiramoto, Masaharu Kobayashi

Applied Physics Letters   117 ( 25 )   252904 - 252904   2020.12

3.3 kV back-gate-controlled IGBT (BC-IGBT) using manufacturable double-side process technology

T. Saraya, K. Itou, T. Takakura, M. Fukui, S. Suzuki, K. Takeuchi, M. Tsukuda, K. Satoh, T. Matsudai, K. Kakushima, T. Hoshii, K. Tsutsui, H. Iwai, A. Ogura, W. Saito, S. Nishizawa, I. Omura, H. Ohashi, T. Hiramoto

Technical Digest - International Electron Devices Meeting, IEDM   2020-December   5.3.1 - 5.3.4   2020.12

A Monolithic 3-D Integration of RRAM Array and Oxide Semiconductor FET for In-Memory Computing in 3-D Neural Network

Jixuan Wu, Fei Mo, Takuya Saraya, Toshiro Hiramoto, Masaharu Kobayashi

IEEE Transactions on Electron Devices   67 ( 12 )   5322 - 5328   2020.12

Origin of carrier lifetime degradation in floating-zone silicon during a high-temperature process for insulated gate bipolar transistor

Ryo Yokogawa, Hiroto Kobayashi, Yohichiroh Numasawa, Atsushi Ogura, Shin-ichi Nishizawa, Takuya Saraya, Kazuo Ito, Toshihiko Takakura, Shinichi Suzuki, Munetoshi Fukui, Kiyoshi Takeuchi, Toshiro Hiramoto

Japanese Journal of Applied Physics   59 ( 11 )   115503 - 115503   2020.11

(Invited) 3D Neural Network: Monolithic Integration of Resistive-RAM Array with Oxide-Semiconductor FET

Masaharu Kobayashi, Jixuan Wu, Fei Mo, Takuya Saraya, Toshiro Hiramoto

ECS Transactions   98 ( 8 )   57 - 61   2020.9

Modeling and simulation of Si IGBTs

N. Shigyo, M. Watanabe, K. Kakushima, T. Hoshii, K. Furukawa, A. Nakajima, K. Satoh, T. Matsudai, T. Saraya, T. Takakura, K. Itou, M. Fukui, S. Suzuki, K. Takeuchi, I. Muneta, H. Wakabayashi, S. Nishizawa, K. Tsutsui, T. Hiramoto, H. Ohashi, H. Iwai

International Conference on Simulation of Semiconductor Processes and Devices, SISPAD   2020-September   129 - 132   2020.9

Superior subthreshold characteristics of gate-all-around p-type junctionless poly-Si nanowire transistor with ideal subthreshold slope

Min-Ju Ahn, Takuya Saraya, Masaharu Kobayashi, Naomi Sawamoto, Atsushi Ogura, Toshiro Hiramoto

Japanese Journal of Applied Physics   2020.7

Reliability characteristics of metal/ferroelectric-HfO2/IGZO/metal capacitor for non-volatile memory application Reviewed

Fei Mo, Takuya Saraya, Toshiro Hiramoto, Masaharu Kobayashi

Applied Physics Express   13 ( 7 )   074005 - 074005   2020.7

A Monolithic 3D Integration of RRAM Array with Oxide Semiconductor FET for In-memory Computing in Quantized Neural Network AI Applications

Jixuan Wu, Fei Mo, Takuya Saraya, Toshiro Hiramoto, Masaharu Kobayashi

Digest of Technical Papers - Symposium on VLSI Technology   2020-   2020.6

Integrated Circuits Composed of Nanowire and Single-Electron Transistors Operating at Room Temperature

Tomoko Mizutani, Kiyoshi Takeuchi, Takuya Saraya, Masaharu Kobayashi, Toshiro Hiramoto

2020 IEEE Silicon Nanoelectronics Workshop, SNW 2020   33 - 34   2020.6

Performance enhancement of BF2+implanted poly-Si junctionless transistors by boron segregation and fluorine effect

Min-Ju Ahn, Takuya Saraya, Masaharu Kobayashi, Toshiro Hiramoto

2020 IEEE Silicon Nanoelectronics Workshop, SNW 2020   51 - 52   2020.6

Superior subthreshold slope of gate-all-around (GAA) p-type poly-Si junctionless nanowire transistors with highly suppressed grain boundary defects

Min-Ju Ahn, Takuya Saraya, Masaharu Kobayashi, Toshiro Hiramoto

2020 IEEE Silicon Nanoelectronics Workshop, SNW 2020   55 - 56   2020.6

Bipolar Transistor Test Structures for Extracting Minority Carrier Lifetime in IGBTs Reviewed

Kiyoshi Takeuchi, Munetoshi Fukui, Takuya Saraya, Kazuo Itou, Toshihiko Takakura, Shinichi Suzuki, Yohichiroh Numasawa, Naoyuki Shigyo, Kuniyuki Kakushima, Takuya Hoshii, Kazuyoshi Furukawa, Masahiro Watanabe, Hitoshi Wakabayashi, Kazuo Tsutsui, Hiroshi Iwai, Atsushi Ogura, Wataru Saito, Shin-Ichi Nishizawa, Masanori Tsukuda, Ichiro Omura, Hiromichi Ohashi, Toshiro Hiramoto

IEEE Transactions on Semiconductor Manufacturing   33 ( 2 )   159 - 165   2020.5

A simulation study on low voltage operability of hafnium oxide based ferroelectric FET memories Reviewed

Kiyoshi Takeuchi, Masaharu Kobayashi, Toshiro Hiramoto

Japanese Journal of Applied Physics   59 ( {SG} )   GB11   2020.4

Statistical analysis of temperature dependence of worst case static random access memory data retention voltage using extreme value theory

Tomoko Mizutani, Kiyoshi Takeuchi, Takuya Saraya, Masaharu Kobayashi, Toshiro Hiramoto

Japanese Journal of Applied Physics   59   2020.4

Impact of structural parameter scaling on on-state voltage in 1200 V scaled IGBTs

Takuya Saraya, Kazuo Itou, Toshihiko Takakura, Munetoshi Fukui, Shinichi Suzuki, Kiyoshi Takeuchi, Kuniyuki Kakushima, Takuya Hoshii, Kazuo Tsutsui, Hiroshi Iwai, Shin-ichi Nishizawa, Ichiro Omura, Toshiro Hiramoto

JAPANESE JOURNAL OF APPLIED PHYSICS   59   2020.4

強誘電体トンネル接合メモリの大規模集積化に向けた設計に関する検討

吉村英将, 莫非, 平本俊郎, 小林正治

第67回応用物理学会春季学術講演会，上智大学（COVID-19のため開催中止），2020年3月14日   14p-A303-13   2020.3

Fabrication of Multi-stacked Integrated Circuit for High-Performance Image Sensors

Nakatani Naoki, Toshiyoshi Hiroshi, Hiramoto Toshiro, Honda Yuki, Goto Masahide, Watabe Toshihisa, Nanba Masakazu, Iguchi Yoshinori, Saraya Takuya, Kobayashi Masaharu, Higurashi Eiji

Transactions of The Japan Institute of Electronics Packaging   13   E20 - 004-1-E20-004-3   2020

Fabrication of 3-layer stacked pixel for pixel-parallel CMOS image sensors by Au/SiO<inf>2</inf> hybrid bonding of SOI wafers

Masahide Goto, Naoki Nakatani, Yuki Honda, Toshihisa Watabe, Masakazu Nanba, Yoshinori Iguchi, Takuya Saraya, Masaharu Kobayashi, Eiji Higurashi, Hiroshi Toshiyoshi, Toshiro Hiramoto

ECS Transactions   98 ( 4 )   167 - 171   2020

Low-Voltage Operating Ferroelectric FET with Ultrathin IGZO Channel for High-Density Memory Application Reviewed

Fei Mo, Yusaku Tagawa, Chengji Jin, MinJu Ahn, Takuya Saraya, Toshiro Hiramoto, Masaharu Kobayashi

IEEE Journal of the Electron Devices Society   8   717 - 723   2020

Width dependence of drain current and carrier mobility in gate-all-around multi-channel polycrystalline silicon nanowire transistors with 10 nm width scale Reviewed

Ki Hyun Jang, Takuya Saraya, Masaharu Kobayashi, Naomi Sawamoto, Atsushi Ogura, Toshiro Hiramoto

Japanese Journal of Applied Physics   59 ( 2 )   2020

Physical Mechanisms of Reverse DIBL and NDR in FeFETs with Steep Subthreshold Swing

Chengji Jin, Takuya Saraya, Toshiro Hiramoto, Masaharu Kobayashi

IEEE Journal of the Electron Devices Society   8   429 - 434   2020

An Architectural Study for Inference Coprocessor Core at the Edge in IoT Sensing. Reviewed

Daisuke Watanabe, Yuji Yano, Shintaro Izumi, Hiroshi Kawaguchi, Kiyoshi Takeuchi, Toshiro Hiramoto, Shoichi Iwai, Masami Murakata, Masahiko Yoshimoto

2nd IEEE International Conference on Artificial Intelligence Circuits and Systems(AICAS)   305 - 309   2020

強誘電体HfO2トンネル接合メモリのスケーラビリティに関する検討 Invited

小林正治, 莫非, 多川友作, 更屋拓哉, 平本俊郎

シリコン材料・デバイス研究会（SDM研究会），機械振興会館，2019年11月7日   5 - 8   2019.11

Triple-Stacked Silicon-on-Insulator Integrated Circuits Using Au/SiO<inf>2</inf>Hybrid Bonding

Yuki Honda, Masahide Goto, Toshihisa Watabe, Masakazu Nanba, Yoshinori Iguchi, Takuya Saraya, Masaharu Kobayashi, Eiji Higurashi, Hiroshi Toshiyoshi, Toshiro Hiramoto

2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2019   2019.10

Comprehensive understanding of negative capacitance fet from the perspective of transient ferroelectric model

Masaharu Kobayashi, Chengji Jin, Toshiro Hiramoto

Proceedings of International Conference on ASIC   2019.10

Switching of 3300v scaled igbt by 5v gate drive

T. Hiramoto, K. Satoh, T. Matsudai, W. Saito, K. Kakushima, T. Hoshii, K. Furukawa, M. Watanabe, N. Shigyo, H. Wakabayashi, K. Tsutsui, T. Sarava, H. Iwai, A. Ogura, S. Nishizawa, I. Omura, H. Ohash, K. Itou, T. Takakura, M. Fukui, S. Suzuki, K. Takeuchi, M. Tsukuda, Y. Numasawa

Proceedings of International Conference on ASIC   2019.10

Mechanisms of Reverse-DIBL and NDR Observed in Ferroelectric FETs

Chengji Jin, Takuya Saraya, Toshiro Hiramoto, Masaharu Kobayashi

第80回応用物理学会秋季学術講演会，北海道大学（北海道），18p-B11-1   2019.9

極薄IGZOチャネルを有する強誘電体トランジスタメモリの検討 Invited

小林正治, 莫非, 多川友作, 金成吉, 安珉柱, 更屋拓哉, 平本俊郎

シリコン材料・デバイス(SDM)研究会，北海道大学，2019年8月9日   59 - 62   2019.8

Experimental Demonstration of Ferroelectric HfO2 FET with Ultrathin-body IGZO for High-Density and Low-Power Memory Application Reviewed

Fei Mo, Yusaku Tagawa, Chengji Jin, MinJu Ahn, Takuya Saraya, Toshiro Hiramoto, Masaharu Kobayashi

VLSI technology symposium 2019, June 11th, 2019, Kyoto   42 - 43   2019.6

Transient Negative Capacitance as Cause of Reverse Drain-induced Barrier Lowering and Negative Differential Resistance in Ferroelectric FETs Reviewed

Chengji Jin, Takuya Saraya, Toshiro Hiramoto, Masaharu Kobayashi

VLSI technology symposium 2019, June 13th, 2019, Kyoto   220 - 221   2019.6

反強誘電体ZrO2を有するMIS構造のユニポーラスイッチング特性

2019.3

Vertical bipolar transistor test structure for measuring minority carrier lifetime in IGBTs Reviewed International journal

K. Takeuchi, M. Fukui, T. Saraya, K. Itou, T. Takakura, S. Suzuki, Y. Numasawa, K. Kakushima, T. Hoshii, K. Furukawa, M. Watanabe, N. Shigyo, H. Wakabayashi, M. Tsukuda, A. Ogura, K. Tsutsui, H. Iwai, Shinichi Nishizawa, I. Omura, H. Ohashi, T. Hiramoto

32nd IEEE International Conference on Microelectronic Test Structures, ICMTS 2019 2019 IEEE 32nd International Conference on Microelectronic Test Structures, ICMTS 2019   98 - 101   2019.3

Scalability Study on Ferroelectric-HfO2 Tunnel Junction Memory

莫 非, 多川 友作, 更屋 拓哉, 平本 俊郎, 小林 正治

第66回応用物理学会春季学術講演会、東京、10p-W934-5   2019.3

Polarization Switching as the Cause of Steep Subthreshold Slope in Ferroelectric FETs

Chengji Jin, Takuya Saraya, Toshiro Hiramoto, Masaharu Kobayashi

第66回応用物理学会春季学術講演会、東京、10p-W631-11   2019.3

A Feasibility Study on Ferroelectric Shadow SRAMs Using a New Variability Design Scheme Reviewed

Kiyoshi Takeuchi, Masaharu Kobayashi, Toshiro Hiramoto

3rd Electron Devices Technology and Manufacturing (EDTM) Conference 2019, Marina Bay Sands, Singapore, March 14, 2019.   109 - 111   2019.3

CMOS 互換プロセスによるスケーラブルな積層構造型シリコン量子ビットの提案

伊藤優希, 小林正治, 平本俊郎

第66回応用物理学会春季学術講演会，東京工業大学大岡山キャンパス，10a-S221-7，2019年3月10日．   2019.3

Steep Subthreshold Slope below 60mV/dec in Junctionless SOI Transistors at Low Drain Voltage of 50mV Reviewed

Min-Ju Ahn, Kiyoshi Takeuchi, Takuya Saraya, Masaharu Kobayashi, Toshiro Hiramoto

3rd Electron Devices Technology and Manufacturing (EDTM) Conference 2019, Marina Bay Sands, Singapore, March 14, 2019   2019.3

Scalability Study on Ferroelectric-HfO₂ Tunnel Junction Memory

MO FEI, yusaku Tagawa, Takuya Saraya, Toshiro Hiramoto, Masaharu Kobayashi

JSAP Annual Meetings Extended Abstracts   2019.1   2639 - 2639   2019.2

Demonstration of 1200V Scaled IGBTs Driven by 5V Gate Voltage with Superiorly Low Switching Loss

T. Saraya, K. Itou, T. Takakura, M. Fukui, S. Suzuki, K. Takeuchi, M. Tsukuda, Y. Numasawa, K. Satoh, T. Matsudai, W. Saito, K. Kakushima, T. Hoshii, K. Furukawa, M. Watanabe, N. Shigyo, K. Tsutsui, H. Iwai, A. Ogura, S. Nishizawa, I. Omura, H. Ohashi, T. Hiramoto

Technical Digest - International Electron Devices Meeting, IEDM   2018-December   2019.1

Experimental Study on the Role of Polarization Switching in Subthreshold Characteristics of HfO 2 -based Ferroelectric and Anti-ferroelectric FET

Chengji Jin, Kyungmin Jang, Takuya Saraya, Toshiro Hiramoto, Masaharu Kobayashi

Technical Digest - International Electron Devices Meeting, IEDM   2018-   31.5.1 - 31.5.4   2019.1

Self-Turn-on-Free 5V Gate Driving for 1200V Scaled IGBT

Masanori Tsukuda, Masaki Sudo, Kazunori Hasegawa, Seiya Abe, Takuya Saraya, Toshihiko Takakura, Munetoshi Fukui, Kazuo Itou, Shinichi Suzuki, Kiyoshi Takeuchi, Tamotsu Ninomiya, Toshiro Hiramoto, Ichiro Omura

2019 31ST INTERNATIONAL SYMPOSIUM ON POWER SEMICONDUCTOR DEVICES AND ICS (ISPSD)   339 - 342   2019

Triple-Layering Technology for Pixel-Parallel CMOS Image Sensors Developed by Hybrid Bonding of SOI Wafers. Reviewed

Masahide Goto, Joeri De Vos, Toshihisa Watabe, Kei Hagiwara, Masakazu Nanba, Yoshinori Iguchi, Eiji Higurashi, Yuki Honda, Takuya Saraya, Masaharu Kobayashi, Hiroshi Toshiyoshi, Toshiro Hiramoto

2019 International 3D Systems Integration Conference (3DIC)(3DIC)   1 - 4   2019

Quarter Video Graphics Array Image Sensor with Linear and Wide-Dynamic-Range Output Developed by Pixel-Wise 3D Integration

118 ( 337 )   43 - 48   2018.12

Proposal of scalable silicon qubits with vertically stacked structures fabricated by CMOS technology Reviewed

Yuki Ito, Masaharu Kobayashi, Toshiro Hiramoto

Silicon Quantum Electronics Workshop (SQEW), Doltone House, Sydney, Australia, Poster No. 23, November 13, 2018.   2018.11

多量子ビット化実現に向けたスケーラブルな積層構造型シリコン量子ビットの提案

伊藤優希, 小林正治, 平本俊郎

電子情報通信学会量子情報技術研究会，東京大学先端科学技術研究センター，2018年11月26日   2018.11

320×240 Pixel-Parallel 3D Integrated CMOS Image Sensors by Direct Bonding of SOI Layers Reviewed

35   4p   2018.10

New Methodology for Evaluating Minority Carrier Lifetime for Process Assessment

K. Kakushima, T. Hoshii, M. Watanabe, N. Shizyo, K. Furukawa, T. Saraya, T. Takakura, K. Itou, M. Fukui, S. Suzuki, K. Takeuchi, I. Muneta, H. Wakabayashi, Y. Numasawa, A. Ogura, S. Nishizawa, K. Tsutsui, T. Hiramoto, H. Ohashi, H. Iwai

IEEE Symposium on VLSI Circuits, Digest of Technical Papers   2018-June   105 - 106   2018.10

Pixel-Parallel Three-Dimensional Integrated CMOS Image Sensors by Using Direct Bonding of Silicon-on-Insulator Wafers for Next-Generation Television Systems Invited Reviewed

Masahide Goto, Yuki Honda, Toshihisa Watabe, Kei Hagiwara, Masakazu Nanba, Yoshinori Iguchi, Takuya Saraya, Masaharu Kobayashi, Eiji Higurashi, Hiroshi Toshiyoshi, Toshiro Hiramoto

The Forum on the Science and Technology of Silicon Materials 2018, Tsushima Campus, Okayama University, October 21, 2018   2018.10

Verification of the injection enhancement effect in IGBTs by measuring the electron and hole currents separately Reviewed

T. Hoshii, K. Furukawa, K. Kakushima, M. Watanabe, N. Shigvo, T. Saraya, T. Takakura, K. Ltou, M. Fukui, S. Suzuki, K. Takeuchi, I. Muneta, H. Wakabayashi, Shinichi Nishizawa, K. Tsutsui, T. Hiramoto, H. Ohashi, H. Lwai

48th European Solid-State Device Research Conference, ESSDERC 2018 2018 48th European Solid-State Device Research Conference, ESSDERC 2018   26 - 29   2018.10

Temperature Effect on DIBL Variability in Bulk and SOTB MOSFETs Reviewed

S. Gao, T. Mizutani, K. Takeuchi, M. Kobayashi, T. Hiramoto

International Conference on Solid State Devices and Materials (SSDM) 2018, Tokyo, Japan   167 - 168   2018.9

画素並列信号処理３層構造イメージセンサの設計 Reviewed

後藤正英, 本田悠葵, 渡部俊久, 萩原 啓, 難波正和, 井口義則, 更屋拓哉, 小林正治, 日暮栄治, 年吉 洋, 平本俊郎

第79回応用物理学会秋季学術講演会，名古屋国際会議場，19p-432-7，2018年9月19日．   79th   2018.9

Ferroelectric Neuron for Feedforward Neural Network Application Reviewed

Fei Mo, Tagawa Yusaku, Saraya Takuya, Hiramoto Toshiro, Kobayashi Masaharu

第79回応用物理学会秋季学術講演会、名古屋   20p-141-13   2018.9

高TER・多値メモリ性を有するHfO2強誘電トンネル接合メモリのためのデバイスおよびプロセス設計 Reviewed

多川 友作, 莫 非, 更屋 拓哉, 平本 俊郎, 小林 正治

第79回応用物理学会秋季学術講演会、名古屋   19p-233-11   2018.9

複数回ストレスを利用した特性ばらつき自己修復手法のBulk SRAMセルへの応用 Reviewed

水谷 朋子, 竹内 潔, 更屋 拓哉, 小林 正治, 平本 俊郎

20a-CE-4   2018.9

Reduced Drain-Induced-Barrier-Lowering (DIBL) Variability at High Temperature in Bulk and SOTB MOSFETs Reviewed

Shuang Gao, Tomoko Mizutani, Kiyoshi Takeuchi, Masaharu Kobayashi, Toshiro Hiramoto

第79回応用物理学会秋季学術講演会、名古屋   20a-CE-3   2018.9

On the Physical Origin of Steep Subthreshold Slope in Ferroelectric FET: Transient Negative Capacitance Effect Caused by Polarization Switching Delay Reviewed

C. Jin, T. Hiramoto, M. Kobayashi

International Conference on Solid State Devices and Materials (SSDM) 2018, Tokyo, Japan   199 - 200   2018.9

SRAMの安定性自己修復手法における複数回ストレス印加の効果

水谷朋子, 竹内 潔, 更屋拓哉, 小林正治, 平本俊郎

電子情報通信学会シリコン材料・デバイス研究会（SDM）および集積回路研究会(ICD)合同研究会，8/7-8/9，北海道   2018.8

Understanding Temperature Effect on Subthreshold Slope Variability in Bulk and SOTB MOSFETs Reviewed

Shuang Gao, Tomoko Mizutani, Kiyoshi Takeuchi, Masaharu Kobayashi, Toshiro Hiramoto

電子情報通信学会シリコン材料・デバイス研究会 (SDM)、北海道   2018.8

強誘電体HfO2 FTJの高TER化と多値化のためのデバイスおよびプロセス設計 Reviewed

小林正治, 多川友作, バク ヒ, 平本俊郎

電子情報通信学会シリコン材料・デバイス研究会（SDM）および集積回路研究会(ICD)合同研究会，8/7-8/9，北海道   2018.8

Scalability Study on Fcrroclcctric-HfO<inf>2</inf> Tunnel Junction Memory Based on Non-equilibrium Green Function Method with Self-consistent Potential

Fei Mo, Yusaku Tagawa, Takuya Saraya, Toshiro Hiramoto, Masaharu Kobayashi

Technical Digest - International Electron Devices Meeting, IEDM   2018-December   16.3.1 - 16.3.4   2018.7

Device and Process Design for HfO 2 -Based Ferroelectric Tunnel Junction - 3 - Memory with Large Tunneling Electroresistance Effect and Multi-level Cell Reviewed

M. Kobayashi, Y. Tagawa, M. Fei, T. Saraya, T. Hiramoto

2018 IEEE Silicon Nanoelectronics Workshop, Honolulu, HI, USA   29 - 30   2018.6

Improving Performance and Variability of Gate-All-Around Polycrystalline Silicon Nanowire Transistors by High Temperature Annealing with Passivation Oxide , Reviewed

K. –H. Jang, T. Saraya, M. Kobayashi, N. Sawamoto, A. Ogura, T. Hiramoto

2018 IEEE Silicon Nanoelectronics Workshop Hilton Hawaiian Village, Honolulu, HI USA   59 - 60   2018.6

Reduced Subthreshold Slope Variability at High Temperature in Bulk and SOTB MOSFETs Reviewed

S. Gao, T. Mizutani, K. Takeuchi, M. Kobayashi, T. Hiramoto

2018 IEEE Silicon Nanoelectronics Workshop June 17-18, 2018 Hilton Hawaiian Village, Honolulu, HI USA Satellite conference of 2018 IEEE Silicon Nanoelectronics Workshop Hilton Hawaiian Village, Honolulu, HI USA   9 - 10   2018.6

Drain-Induced Variability Due to Quantum Confinement Effect in Extremely Narrow Silicon Nanowire Transistors with Width down to 2nm Reviewed

Toshiro Hiramoto, Tomoko Mizutani, Kiyoshi Takeuchi, Takuya Saraya, Masaharu Kobayashi

International Conference on Nanoelectronics Strategy (INS), Qatar Science Hall, Tohoku University, May 14, 2018   2018.5

Statistics of Random Telegraph Noise Amplitude in Extremely Narrow Silicon Nanowire Transistors with Width down to 2nm Reviewed

Toshiro Hiramoto, Hao Qiu, Kiyoshi Takeuchi, Tomoko Mizutani, Takuya Saraya, Masaharu Kobayashi

International Conference on Nanoelectronics Strategy (INS), Qatar Science Hall, Tohoku University, May 14, 2018   2018.5

A Nonvolatile SRAM Based on Ferroelectric HfO2 capacitor for IoT Power Management Invited Reviewed

Masaharu Kobayashi, Nozomu Ueyama, Toshiro Hiramoto

ECS Transactions, Seattle, WA   85 ( 6 )   111 - 114   2018.5

Quarter Video Graphics Array Full-Digital Image Sensing with Wide Dynamic Range and Linear Output Using Pixel-Wise 3D Integration Reviewed

Masahide Goto, Yuki Honda, Toshihisa Watabe, Kei Hagiwara, Masakazu Nanba, Yoshinori Iguchi, Takuya Saraya, Masaharu Kobayashi, Eiji Higurashi, Hiroshi Toshiyoshi, Toshiro Hiramoto

Proceedings - IEEE International Symposium on Circuits and Systems   2018-May   2018.4

MOS-Gated Thyristorの電圧ベース等価回路モデルを用いた急峻スロープPN-Body Tied SOI FETのパラメータ依存性の検討 Reviewed

植田大貴, 竹内 潔, 小林正治, 平本俊郎

第65回応用物理学会春季学術講演会，早稲田大学西早稲田キャンパス（東京）   18a-G203-5   2018.3

複数回ストレスを利用した特性ばらつき自己修復手法によるSRAMデータ保持電圧の最小化 Reviewed

水谷朋子, 竹内 潔, 更屋拓哉, 小林正治, 平本俊郎

第65回応用物理学会春季学術講演会，早稲田大学西早稲田キャンパス（東京）   18p-G203-1   2018.3

Pixel-parallel 3-D integrated CMOS image sensors for next-generation video systems Reviewed

Masahide Goto, Yuki Honda, Toshihisa Watabe, Kei Hagiwara, Masakazu Nanba, Yoshinori Iguchi, Takuya Saraya, Masaharu Kobayashi, Eiji Higurashi, Hiroshi Toshiyoshi, Toshiro Hiramoto

ECS Transactions   85 ( 8 )   163 - 166   2018

３次元構造撮像デバイスの微細・高集積化に向けた直接接合による多層積層技術 Reviewed

本田悠葵, 後藤正英, 渡部俊久, 萩原 啓, 難波正和, 井口義則, 更屋拓哉, 小林正治, 日暮栄治, 年吉 洋, 平本俊郎

応用物理学会第9回集積化MEMSシンポジウム，広島   34th   2017.11

Fabrication of Three-Dimensional Integrated CMOS Image Sensors with Quarter VGA Resolution by Pixel-Wise Direct Bonding Technology Reviewed

Masahide Goto, Yuki Honda, Toshihisa Watabe, Kei Hagiwara, Masakazu Nanba, Yoshinori Iguchi, Takuya Saraya, Masaharu Kobayashi, Eiji Higurashi, Hiroshi Toshiyoshi, Toshiro Hiramoto

30th International Microprocesses and Nanotechnology Conference (MNC2017), Ramada Plaza JeJu Hotel, Jeju, Korea   2017.11

Parallel Programmable Nonvolatile Memory Using SRAM Cells Invited Reviewed

Toshiro Hiramoto, Tomoko Mizutani, Kiyoshi Takeuchi, Masaharu Kobayashi

12th International Conference on ASIC (ASICON 2017), Hotel Pullman Guiyang, Guiyang, China   434 - 437   2017.10

３次元構造撮像デバイスの画素内A/D変換回路に適用可能なイベントドリブン型雑音除去回路の開発 Reviewed

後藤正英, 本田悠葵, 渡部俊久, 萩原 啓, 難波正和, 井口義則, 更屋拓哉, 小林正治, 日暮栄治, 年吉 洋, 平本俊郎

応用物理学会第9回集積化MEMSシンポジウム，広島   34th   2017.10

Lowering Minimum Operation Voltage (Vmin) in SRAM Array by Post-Fabrication Self-Improvement of Cell Stability by Multiple Stress Application Reviewed

Tomoko Mizutani, Kiyoshi Takeuchi, Takuya Saraya, Masaharu Kobayashi, Toshiro Hiramoto

International Conference on Solid State Devices and Materials (SSDM), Sendai International Center, Miyagi   245 - 246   2017.9

Development of Event-Driven Correlated Double Sampling for A/D Converters in Pixel-Parallel 3-D Integrated CMOS Image Sensors Reviewed

後藤正英, 本田悠葵, 渡部俊久, 萩原 啓, 難波正和, 井口義則, 更屋拓哉, 小林正治, 日暮栄治, 年吉 洋, 平本俊郎

情報センシング研究会，械振興会館（東京）   41 ( 32 )   1 - 4   2017.9

急峻サブスレッショルドスロープPN-Body Tied SOI FETの最適化に向けたMOS-Gated Thyristorの電圧ベース等価回路モデル Reviewed

植田大貴, 竹内 潔, 小林正治, 平本俊郎

第78回応用物理学会秋季学術講演会，福岡国際会議場   8a-C18-6   2017.9

低消費電力応用に向けた強誘電体HfO2薄膜不揮発性SRAMの動作実証 Reviewed

小林正治, 上山 望, 平本 俊郎

第78回応用物理学会秋季学術講演会，福岡国際会議場   7p-A204-14   2017.9

強誘電性マルチドメイン相互作用モデルを用いた強誘電体HfO2の動特性に関する考察 Reviewed

Jang Kyungmin, 上山 望, 小林正治, 平本俊郎

第78回応用物理学会秋季学術講演会，福岡国際会議場   7p-A204-13   2017.9

ノーマリーオフ動作のための強誘電体HfO2を集積した不揮発性SRAM Invited Reviewed

小林正治, 上山 望, 平本俊郎

電子情報通信学会シリコン材料・デバイス研究会（SDM）および集積回路研究会(ICD)合同研究会，北海道大学情報教育館   SDM2017-37   2017.8

不揮発情報一括書き込み・読み出し可能な初期値確定SRAM Reviewed

水谷朋子, 竹内 潔, 更屋拓哉, 篠原尋史, 小林正治, 平本俊郎

電子情報通信学会シリコン材料・デバイス研究会（SDM）および集積回路研究会(ICD)合同研究会，北海道大学情報教育館   SDM2017-38   2017.8

Statistical analyses of random telegraph noise amplitude in ultra-narrow (deep sub-10nm) silicon nanowire transistors Reviewed

Hao Qiu, Kiyoshi Takeuchi, Tomoko Mizutani, Takuya Saraya, Jiezhi Chen, Masaharu Kobayashi, Toshiro Hiramoto

Digest of Technical Papers - Symposium on VLSI Technology   T50 - T51   2017.7

A nonvolatile SRAM integrated with ferroelectric HfO2 capacitor for normally-off and ultralow power IoT application Reviewed

Masaharu Kobayashi, Nozomu Ueyama, Toshiro Hiramoto

Digest of Technical Papers - Symposium on VLSI Technology   T156 - T157   2017.7

Event-Driven Correlated Double Sampling for Pulse-Frequency-Modulation A/D Converters Integrated in Pixel-Parallel Image Sensors Reviewed

Masahide Goto, Yuki Honda, Toshihisa Watabe, Kei Hagiwara, Masakazu Nanba, Yoshinori Iguchi, Takuya Saraya, Masaharu Kobayashi, Eiji Higurashi, Hiroshi Toshiyoshi, Toshiro Hiramoto

2017 International Image Sensor Workshop (IISW), Grand Prince Hotel Hiroshima, Hiroshima   2017.5

強誘電体HfO2を用いたGate-All-Aroundナノワイヤ負性容量FETにおけるIon/Ioff比の向上とそのスケーラビリティ Reviewed

Jang Kyungmin, 更屋拓哉, 小林正治, 平本俊郎

第64回応用物理学会春季学術講演会，パシフィコ横浜（神奈川）   17p-304-15   2017.3

強誘電体HfO2ダブルゲート負性容量FETの動特性に関する考察 Reviewed

Jang Kyungmin, 上山 望, 小林正治, 平本俊郎

第64回応用物理学会春季学術講演会，パシフィコ横浜（神奈川）   17p-304-14   2017.3

通常のSRAMセルを利用した一括書き込み可能な不揮発性メモリ Reviewed

水谷朋子, 竹内 潔, 更屋拓哉, 篠原尋史, 小林正治, 平本俊郎

第64回応用物理学会春季学術講演会，パシフィコ横浜（神奈川）   16a-412-5   2017.3

負性容量トランジスタに向けた強誘電性HfZrO2膜における負性容量の直接観測 Reviewed

上山 望, 小林正治, 平本俊郎

第64回応用物理学会春季学術講演会，パシフィコ横浜（神奈川）   17p-304-13   2017.3

SRAM の電源投入直後初期状態とトランジスタばらつきの関係 Reviewed

竹内 潔, 水谷朋子, 篠原尋史, 更屋拓哉, 小林正治, 平本俊郎

第64回応用物理学会春季学術講演会，パシフィコ横浜（神奈川）   16a-412-6   2017.3

Experimental study on polarization-limited operation speed of negative capacitance FET with ferroelectric HfO2 Reviewed

Masaharu Kobayashi, Nozomu Ueyama, Kyungmin Jang, Toshiro Hiramoto

Technical Digest - International Electron Devices Meeting, IEDM   12.3.1 - 12.3.4   2017.1

強誘電性HfO2を用いた負性容量トランジスタの動作速度に関する実験検討 Invited Reviewed

小林正治, 上山 望, 蒋 京珉, 平本俊郎

電子情報通信学会回路・デバイス・境界領域技術研究会，国民宿舎みやじま杜の宿（広島）   2017.1

Three-layered stacking process by Au/SiO<inf>2</inf> hybrid bonding for 3D structured image sensors Reviewed

Yuki Honda, Masahide Goto, Toshihisa Watabe, Kei Hagiwara, Masakazu Nanba, Yoshinori Iguchi, Takuya Saraya, Masaharu Kobayashi, Eiji Higurashi, Hiroshi Toshiyoshi, Toshiro Hiramoto

ECS Transactions   80 ( 4 )   227 - 231   2017

3D Scaling for Insulated Gate Bipolar Transistors (IGBTs) with Low V-ce(sat)

K. Tsutsui, K. Kakushima, T. Hoshii, A. Nakajima, S. Nishizawa, H. Wakabayashi, I. Muneta, K. Sato, T. Matsudai, W. Saito, T. Saraya, K. Itou, M. Fukui, S. Suzuki, M. Kobayashi, T. Takakura, T. Hiramoto, A. Ogura, Y. Numasawa, I. Omura, H. Ohashi, H. Iwai

2017 IEEE 12TH INTERNATIONAL CONFERENCE ON ASIC (ASICON)   1137 - 1140   2017

３次元構造撮像デバイスの微細・高集積化に向けた接合電極の微細・狭ピッチ化 Reviewed

本田悠葵, 萩原啓, 後藤正英, 渡部俊久, 難波正和, 井口義則, 更屋拓哉, 小林正治, 年吉洋, 日暮栄治, 平本俊郎

第8回集積化MEMSシンポジウム，平戸文化センター（長崎）   33rd   2016.10

A Study on the Correlation between SRAM Power-up State and Transistor Variation Reviewed

Kiyoshi Takeuchi, Tomoko Mizutani, Takuya Saraya, Hirofumi Shinohara, Masaharu Kobayashi, Toshiro Hiramoto

International Conference on Solid State Devices and Materials (SSDM), Tsukuba International Congress Center, Ibaraki   55 - 56   2016.9

線幅2nmの超微細シリコンナノワイヤトランジスタにおけるドレイン電圧に起因する特性ばらつき Reviewed

水谷朋子, 竹内 潔, 鈴木龍太, 更屋拓哉, 小林正治, 平本俊郎

第77回応用物理学会秋季学術講演会，朱鷺メッセ（新潟）   14a-B13-6   2016.9

SRAMセルアレーTEGを用いた電源投入直後データの測定 Reviewed

竹内 潔, 水谷朋子, 篠原尋史, 更屋拓哉, 小林正治, 平本俊郎

第77回応用物理学会秋季学術講演会，朱鷺メッセ（新潟）   14a-B13-7   2016.9

サブ0.2Vの高エネルギー効率動作に向けた強誘電体HfO2ダブルゲート負性容量FETにおけるゲートスタックのスケーラビリティ Reviewed

Jang Kyungmin, 更屋拓哉, 小林正治, 平本 俊郎

第77回応用物理学会秋季学術講演会，朱鷺メッセ（新潟）   13p-B13-5   2016.9

負性容量によるトンネルFETの性能向上負性容量によるトンネルFETの性能向上 Reviewed

小林正治, 蔣 京珉, 上山 望, 平本俊郎

第77回応用物理学会秋季学術講演会，朱鷺メッセ（新潟）   13p-B13-4   2016.9

Parallel Programmable Non-volatile Memory Using Normal SRAM Cells Reviewed

Tomoko Mizutani, Kiyoshi Takeuchi, Takuya Saraya, Hirofumi Shinohara, Masaharu Kobayashi, Toshiro Hiramoto

International Conference on Solid State Devices and Materials (SSDM), Tsukuba International Congress Center, Ibaraki   57 - 58   2016.9

線幅2nmの超微細シリコンナノワイヤトランジスタにおけるDIBLばらつきおよびデバイス内ばらつき Reviewed

水谷朋子, 竹内 潔, 鈴木龍太, 更屋拓哉, 小林正治, 平本俊郎

電子情報通信学会シリコン材料・デバイス研究会（SDM），中央電気倶楽部（大阪）   116 ( 172 )   123 - 126   2016.8

負性容量によるトンネルFETの性能向上に関する検討 Reviewed

小林正治, チャン キュンミン, 上山 望, 平本俊郎

電子情報通信学会シリコン材料・デバイス研究会（SDM），中央電気倶楽部（大阪）   40 ( 24 )   127 - 130   2016.8

128×96 Pixel-Parallel Three-Dimensional Integrated CMOS Image Sensors with 16-bit Output Reviewed

後藤正英, 萩原 啓, 本田悠葵, 渡部俊久, 難波正和, 井口義則, 更屋拓哉, 小林正治, 日暮栄治, 年吉 洋, 平本俊郎

電気学会E部門総合研究会，金沢市文化ホール（石川）   2016 ( 9 )   15 - 20   2016.6

A New Variability Origin in Extremely Narrow Silicon Nanowire MOSFETs with Nanowire Width down to 2nm Reviewed

T. Hiramoto, T. Mizutani, Y. Tanahashi, R. Suzuki, T. Saraya, M. Kobayashi

CMOS Emerging Technologies, Hotel Bonaventure Montreal, Montreal, Canada   2016.5

C-12-14 Pulse-Frequency-Modulation A/D Converters Suitable for CMOS Image Sensor Pixel Reviewed

Goto Masahide, Hagiwara Kei, Honda Yuki, Nanba Masakazu, Iguchi Yoshinori, Saraya Takuya, Kobayashi Masaharu, Higurashi Eiji, Toshiyoshi Hiroshi, Hiramoto Toshiro

Proceedings of the IEICE General Conference   2016 ( 2 )   87 - 87   2016.3

ランダムテレグラフノイズに起因するSRAM誤動作のトランジスタレベル解析 Reviewed

水谷朋子, 更屋拓哉, 竹内 潔, 小林 正治, 平本 俊郎

第63回応用物理学会春季学術講演会，東京工業大学大岡山キャンパス（東京）   20a-S422-3   2016.3

Ultra-Low Power and Ultra-Low Voltage Devices and Circuits for IoT Applications Invited Reviewed

T. Hiramoto, K. Takeuchi, T. Mizutani, A. Ueda, T. Saraya, M. Kobayashi, Y. Yamamoto, H. Makiyama, T. Yamashita, H. Oda, S. Kamohara, N. Sugii, Y. Yamaguchi

2016 IEEE SILICON NANOELECTRONICS WORKSHOP (SNW)   146 - 147   2016

画素並列信号処理を行うSOI積層型３次元構造撮像デバイスの試作と評価 Reviewed

後藤正英, 萩原 啓, 井口義則, 大竹 浩, 更屋拓哉, 小林正治, 日暮栄治, 年吉 洋, 平本俊郎

第7回集積化MEMSシンポジウム，朱鷺メッセ（新潟コンベンションセンター）   32nd   30pm1-D-5   2015.10

線幅2nmの超微細シリコンナノワイヤトランジスタにおける量子閉じ込め効果によるしきい値電圧および電流ばらつき Reviewed

水谷朋子, 棚橋裕麻, 鈴木龍太, 更屋拓哉, 小林正治, 平本俊郎

第76回応用物理学会秋季学術講演会，名古屋国際会議場（愛知）   15p-1C-7   2015.9

On the Device Design for Steep Slope Negative Capacitance FET (NCFET) Toward Sub-0.2V operation Reviewed

Masaharu Kobayashi, Toshiro Hiramoto

第76回応用物理学会秋季学術講演会，名古屋国際会議場（愛知）   16a-1C-7   2015.9

パルス周波数変調方式A/D変換回路の３次元集積化 Reviewed

後藤正英, 萩原 啓, 井口義則, 大竹 浩, 更屋拓哉, 小林正治, 日暮栄治, 年吉 洋, 平本俊郎

第76回応用物理学会秋季学術講演会，名古屋国際会議場（愛知）   76th   14a-1C-2   2015.9

FD-SOTB nMOSFETにおけるRTN振幅統計分布の基板バイアス依存性 Reviewed

Jang Kyungmin, 水谷朋子, 竹内潔, 更屋拓哉, 小林正治, 平本俊郎

第76回応用物理学会秋季学術講演会，名古屋国際会議場（愛知）   15p-1C-1   2015.9

負性容量による急峻スロープトランジスタ(NCFET)の設計指針 Reviewed

小林正治, 平本俊郎

電子情報通信学会 シリコン材料・デバイス研究会 集積回路研究会合同研究会，熊本市民会館崇城大学ホール   60   2015.8

high-k添加シングルp+Polyゲートを用いた超低リーク用途向け薄膜BOX-SOI CMOS Reviewed

山本芳樹, 槇山秀樹, 山下朋弘, 尾田秀一, 蒲原史朗, 山口泰男, 杉井信之, 水谷朋子, 小林正治, 平本俊郎

応用物理学会シリコンテクノロジー研究会 第184回研究集会「2015 VLSIシンポジウム」特集，甲南大学ネットワークキャンパス東京   67   2015.8

線幅2nmの超微細シリコンナノワイヤトランジスタにおけるしきい値電圧および電流ばらつき Reviewed

水谷朋子, 棚橋裕麻, 鈴木龍太, 更屋拓哉, 小林正治, 平本俊郎

電子情報通信学会 シリコン材料・デバイス研究会 集積回路研究会合同研究会，熊本市民会館崇城大学ホール   68   2015.8

Development of Three-Dimensional Integrated Circuits and Pixel-Parallel CMOS Image Sensors Using Direct Bonding of SOI Layers Reviewed

後藤正英, 萩原 啓, 井口義則, 大竹 浩, 更屋拓哉, 小林正治, 日暮栄治, 年吉 洋, 平本俊郎

第79回半導体集積回路シンポジウム, 早稲田大学西早稲田キャンパス   79   43 - 46   2015.7

画像並列信号処理を行う3次元構造撮像デバイスの試作 Reviewed

後藤正英, 萩原 啓, 井口義則, 大竹 浩, 更屋拓哉, 小林正治, 日暮栄治, 年吉 洋, 平本俊郎

応用物理学会第6回集積化MEMS技術研究ワークショップ，NHK放送技術研究所（東京）   2015.7

A Three-Dimensional Integration Technology with Embedded Au Electrodes for stacked CMOS Image Sensors Reviewed

Masahide Goto, Kei Hagiwara, Yoshinori Iguchi, Hiroshi Ohtake, Takuya Saraya, Masaharu Kobayashi, Eiji Higurashi, Hiroshi Toshiyoshi, Toshiro Hiramoto

2015 International Image Sensor Workshop (IISW), Vaals, The Netherlands   2015.6

Threshold Voltage Self-Adjusting MOSFETs and SRAM Cells Operating at 0.1V Reviewed

Toshiro Hiramoto, Akitsugu Ueda, Seung-Min Jung, Tomoko Mizutani, Takuya Saraya, Masaharu Kobayashi

11th International Nanotechnology Conference on Communication and Cooperation (INC11), Hilton Fukuoka Sea Hawk, Fukuoka   94   2015.5

Three-dimensional integrated CMOS image sensors with pixel-parallel A/D converters fabricated by direct bonding of SOI layers Reviewed

Masahide Goto, Kei Hagiwara, Yoshinori Iguchi, Hiroshi Ohtake, Takuya Saraya, Masaharu Kobayashi, Eiji Higurashi, Hiroshi Toshiyoshi, Toshiro Hiramoto

Technical Digest - International Electron Devices Meeting, IEDM   2015-February ( February )   4.2.1 - 4.2.4   2015.2

Re-Invention of FET Reviewed

Toshiro Hiramoto

Emerging Nanoelectronic Devices   277 - 297   2015.1

Threshold Voltage and Current Variability of Extremely Narrow Silicon Nanowire MOSFETs with Width down to 2nm Reviewed

T. Mizutani, Y. Tanahashi, R. Suzuki, T. Saraya, M. Kobayashi, T. Hiramoto

2015 SILICON NANOELECTRONICS WORKSHOP (SNW)   21 - 22   2015

Novel Single p plus Poly-Si/Hf/SiON Gate Stack Technology on Silicon-on-Thin-Buried-Oxide (SOTB) for Ultra-Low Leakage Applications Reviewed

Y. Yamamoto, H. Makiyama, T. Yamashita, H. Oda, S. Kamohara, N. Sugii, Y. Yamaguchi, T. Mizutani, M. Kobayashi, T. Hiramoto

2015 SYMPOSIUM ON VLSI TECHNOLOGY (VLSI TECHNOLOGY)   170 - 171   2015

Foreword Reviewed

Klaus Schruefer, Toshiro Hiramoto

Digest of Technical Papers - Symposium on VLSI Technology   2014.9

Three-dimensional integration of fully depleted silicon-on-insulator transistor substrates for CMOS image sensors using Au/SiO2 hybrid bonding and XeF2 etching Reviewed

Hagiwara, Kei, Goto, Masahide, Ohtake, Hiroshi, Iguchi, Yoshinori, Saraya, Takuya, Toshiyoshi, Hiroshi, Higurashi, Eiji, Hiramoto, Toshiro

ECS Transactions   64 ( 5 )   391 - 396   2014

Development of novel three-dimensional structuring of integrated circuits by using low temperature direct bonding for CMOS image sensors Reviewed

Masahide Goto, Kei Hagiwara, Yoshinori Iguchi, Hiroshi Ohtake, Takuya Saraya, Eiji Higurashi, Hiroshi Toshiyoshi, Toshiro Hiramoto

ECS Transactions   61 ( 6 )   87 - 90   2014

Three-Dimensional Integrated Circuits with NFET and PFET on Separate Layers Fabricated by Low Temperature Au/SiO2 Hybrid Bonding Reviewed

M. Goto, K. Hagiwara, Y. Iguchi, H. Ohtake, T. Saraya, E. Higurashi, H. Toshiyoshi, T. Hiramoto

2013 IEEE SOI-3D-SUBTHRESHOLD MICROELECTRONICS TECHNOLOGY UNIFIED CONFERENCE (S3S)   2013

Ultralow-voltage operation of Silicon-on-Thin-BOX (SOTB) 2Mbit SRAM down to 0.37 v utilizing adaptive back bias

Y. Yamamoto, H. Makiyama, H. Shinohara, T. Iwamatsu, H. Oda, S. Kamohara, N. Sugii, Y. Yamaguchi, T. Mizutani, T. Hiramoto

Digest of Technical Papers - Symposium on VLSI Technology   T212 - T213   2013

Vmin=0.4 v LSIs are the real with silicon-on-thin-buried-oxide (SOTB)-How is the application with 'Perpetuum-Mobile' micro-controller with SOTB? Reviewed

N. Sugii, T. Iwamatsu, Y. Yamamoto, H. Makiyama, H. Shinohara, H. Oda, S. Kamohara, Y. Yamaguchi, K. Ishibashi, T. Mizutani, T. Hiramoto

2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2013   2013

Suppression of die-to-die delay variability of silicon on thin buried oxide (SOTB) CMOS circuits by balanced P/N drivability control with back-bias for ultralow-voltage (0.4 V) operation Reviewed

H. Makiyama, Y. Yamamoto, H. Shinohara, T. Iwamatsu, H. Oda, N. Sugii, K. Ishibashi, T. Mizutani, T. Hiramoto, Y. Yamaguchi

Technical Digest - International Electron Devices Meeting, IEDM   33.2.4   2013

Silicon on Thin Buried Oxide (SOTB) Technology for Ultralow-Power Applications Reviewed

N. Sugii, T. Iwamatsu, Y. Yamamoto, H. Makiyama, H. Shinohara, H. Aono, H. Oda, S. Kamohara, Y. Yamaguchi, T. Mizutani, Toshiro Hiramoto

2013 INTERNATIONAL CONFERENCE ON SEMICONDUCTOR TECHNOLOGY FOR ULTRA LARGE SCALE INTEGRATED CIRCUITS AND THIN FILM TRANSISTORS (ULSIC VS. TFT 4)   54 ( 1 )   189 - 196   2013

Reduced drain current variability in fully depleted silicon-on-thin-BOX (SOTB) MOSFETs Reviewed

T. Mizutani, Y. Yamamoto, H. Makiyama, T. Tsunomura, T. Iwamatsu, H. Oda, N. Sugii, T. Hiramoto

2012 IEEE Silicon Nanoelectronics Workshop, SNW 2012   2012

Variability in Scaled MOSFETs: Measurements, Analysis, and Suppression Reviewed

Toshiro Hiramoto, Anil Kumar, Tomoko Mizutani, Takuya Saraya

2012 IEEE 11TH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT-2012)   654 - 657   2012

Development of Novel MOSFET with Front and Back Side Electrodes for 3D-Structured Image Sensors Reviewed

Masahide Goto, Kei Hagiwara, Yoshinori Iguchi, Hiroshi Ohtake, Takuya Saraya, Hiroshi Toshiyoshi, Toshiro Hiramoto

INTERNATIONAL SYMPOSIUM ON FUNCTIONAL DIVERSIFICATION OF SEMICONDUCTOR ELECTRONICS   50 ( 14 )   49 - 54   2012

Mechanisms of high hole mobility in (100) nanowire pMOSFETs with width of less than 10nm Reviewed

Hirotoshi Nomura, Ryota Suzuki, Tomohiro Kutsuki, Takuya Saraya, Toshiro Hiramoto

2012 13th International Conference on Ultimate Integration on Silicon, ULIS 2012   41 - 44   2012

Poly/high-k/SiON gate stack and novel profile engineering dedicated for ultralow-voltage silicon-on-thin-BOX (SOTB) CMOS operation Reviewed

Y. Yamamoto, H. Makiyama, T. Tsunomura, T. Iwamatsu, H. Oda, N. Sugii, Y. Yamaguchi, T. Mizutani, T. Hiramoto

Digest of Technical Papers - Symposium on VLSI Technology   109 - 110   2012

Characteristics control of single electron transistor with floating gate by charge pump circuit Reviewed

Motoki Nozue, Ryota Suzuki, Hirotoshi Nomura, Takuya Saraya, Toshiro Hiramoto

2012 13th International Conference on Ultimate Integration on Silicon, ULIS 2012   161 - 164   2012

Self-improvement of cell stability in SRAM by post fabrication technique Reviewed

Anil Kumar, Takuya Saraya, Shinji Miyano, Toshiro Hiramoto

2012 IEEE Silicon Nanoelectronics Workshop, SNW 2012   2012

Reinvestigation of dot formation mechanisms in silicon nanowire channel single-electron/hole transistors operating at room temperature Reviewed

Ryota Suzuki, Motoki Nozue, Takuya Saraya, Toshiro Hiramoto

2012 IEEE Silicon Nanoelectronics Workshop, SNW 2012   2012

Silicon Single Electron Transistors Operating at Room Temperature and Their Applications Reviewed

K. Miyaji, T. Hiramoto

Comprehensive Semiconductor Science and Technology   1-6   340 - 382   2011.1

Suppression of VT variability degradation induced by NBTI with RDF control

T. Tsunomura, J. Nishimura, A. Kumar, A. Nishida, S. Inaba, K. Takeuchi, T. Hiramoto, T. Mogami

Digest of Technical Papers - Symposium on VLSI Technology   150 - 151   2011

Statistical comparison of random telegraph noise (RTN) in bulk and fully depleted SOI MOSFETs Reviewed

Jun Nishimura, Takuya Saraya, Toshiro Hiramoto

2011 12th International Conference on Ultimate Integration on Silicon, ULIS 2011   191 - 194   2011

From bulk toward FDSOI and silicon nanowire transistors: Challenges and opportunities Reviewed

Toshiro Hiramoto

2011 12th International Conference on Ultimate Integration on Silicon, ULIS 2011   1 - 2   2011

Origin of "current-onset voltage" variability in scaled MOSFETs Reviewed

A. Kumar, T. Mizutani, K. Shimizu, T. Tsunomura, A. Nishida, K. Takeuchi, S. Inaba, S. Kamohara, K. Terada, T. Hiramoto

2010 Silicon Nanoelectronics Workshop, SNW 2010   2010

Suppression of DIBL and Current-Onset Voltage Variability in Intrinsic Channel Fully Depleted SOI MOSFETs Reviewed

T. Hiramoto, T. Mizutani, A. Kumar, A. Nishida, T. Tsunomura, S. Inaba, K. Takeuchi, S. Kamohara, T. Mogami

2010 IEEE INTERNATIONAL SOI CONFERENCE   2010

Analysis and Prospect of Local Variability of Drain Current in Scaled MOSFETs by a New Decomposition Method Reviewed

T. Tsunomura, A. Kumar, T. Mizutani, C. Lee, A. Nishida, K. Takeuchi, S. Inaba, S. Kamohara, K. Terada, T. Hiramoto, T. Mogami

2010 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS   97 - +   2010

Impact of DIBL Variability on SRAM Static Noise Margin Analyzed by DMA SRAM TEG Reviewed

X. Song, M. Suzuki, T. Saraya, A. Nishida, T. Tsunomura, S. Kamohara, K. Takeuchi, S. Inaba, T. Mogami, T. Hiramoto

2010 INTERNATIONAL ELECTRON DEVICES MEETING - TECHNICAL DIGEST   2010

Variation; key issue of the advanced CMOS &amp; LSI's Reviewed

Shiro Kamohara, Akio Nishida, Toshiro Hiramoto, Toru Mogami

Proceedings of 2010 International Symposium on VLSI Technology, System and Application, VLSI-TSA 2010   122 - 123   2010

Direct measurements, analysis, and post-fabrication improvement of noise margins in SRAM cells utilizing DMA SRAM TEG Reviewed

M. Suzuki, T. Saraya, K. Shimizu, A. Nishida, S. Kamohara, K. Takeuchi, S. Miyano, T. Sakurai, T. Hiramoto

Digest of Technical Papers - Symposium on VLSI Technology   191 - 192   2010

Statistic characteristics of "current-onset voltage" in scaled MOSFETs analyzed by 8k DMA TEG Reviewed

T. Mizutani, A. Kumar, T. Tsunomura, A. Nishida, K. Takeuchi, S. Inaba, S. Kamohara, K. Terada, T. Hiramoto

2010 Silicon Nanoelectronics Workshop, SNW 2010   2010

Mobility enhancement in silicon nanowire transistors Reviewed

Toshiro Hiramoto, Jiezhi Chen, Takuya Saraya

ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings   9 - 12   2010

Silicon on thin BOX (SOTB) CMOS for ultralow standby power with forward-biasing performance booster Reviewed

T. Ishigaki, R. Tsuchiya, Y. Morita, H. Yoshimoto, N. Sugii, T. Iwamatsu, H. Oda, Y. Inoue, T. Ohtou, T. Hiramoto, S. Kimura

SOLID-STATE ELECTRONICS   53 ( 7 )   717 - 722   2009.7

Transistor evolution for CMOS extension and future information processing technologies Reviewed

Toshiro Hiramoto

Extended Abstracts of the 9th International Workshop on Junction Technology, IWJT 2009   3 - 6   2009

Superior &lt; 110 &gt;-Directed Mobility to &lt; 100 &gt;-Directed Mobility in Ultrathin Body (110) nMOSFETs Reviewed

Ken Shimizu, Takuya Saraya, Toshiro Hiramoto

2009 IEEE INTERNATIONAL SOI CONFERENCE   143 - 144   2009

Analysis of Extra V-T Variability Sources in NMOS Using Takeuchi Plot Reviewed

T. Tsunomura, A. Nishida, F. Yano, A. T. Putra, K. Takeuchi, S. Inaba, S. Kamohara, K. Terada, T. Mama, T. Hiramoto, T. Mogami

2009 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS   110 - +   2009

Random Fluctuations in Scaled MOS Devices Reviewed

Kiyoshi Takeuchi, Akio Nishida, Toshiro Hiramoto

2009 INTERNATIONAL CONFERENCE ON SIMULATION OF SEMICONDUCTOR PROCESSES AND DEVICES   79 - +   2009

Anomalous back-bias dependence of threshold voltage variability in NMOSFETs due to high concentration regions near source and drain Reviewed

Ichiro Yamato, Tatsuya Mama, Takaaki Tsunomura, Akio Nishida, Toshiro Hiramoto

2009 International Semiconductor Device Research Symposium, ISDRS '09   2009

Improvement of static noise margin in SRAM by post-fabrication self-convergence technique Reviewed

Makoto Suzuki, Takuya Saraya, Ken Shimizu, Takayasu Sakurai, Toshiro Hiramoto

2009 International Semiconductor Device Research Symposium, ISDRS '09   2009

Experimental study on uniaxially stressed gate-all-around silicon nanowires nMOSFETs on (110) silicon-on-insulator Reviewed

Jiezhi Chen, Takuya Saraya, Toshiro Hiramoto

2009 International Semiconductor Device Research Symposium, ISDRS '09   2009

A new methodology for evaluating VT variability considering dopant depth profile

A. T. Putra, T. Tsunomura, A. Nishida, S. Kamohara, K. Takeuchi, S. Inaba, K. Terada, T. Hiramoto

Digest of Technical Papers - Symposium on VLSI Technology   116 - 117   2009

Transport in silicon nanowire transistors Reviewed

T. Hiramoto, J. Chen, Y. J. Jeong, T. Saraya

ECS Transactions   18 ( 1 )   55 - 60   2009

Analyses of random threshold voltage fluctuations in MOS devices Reviewed

K. Takeuchi, T. Tsunomura, A. T. Putra, T. Fukai, A. Nishida, S. Kamohara, T. Hiramoto

Extended Abstracts of the 9th International Workshop on Junction Technology, IWJT 2009   7 - 10   2009

Impact of fixed charge at MOSFETs' SiO2/Si interface on V th variation Reviewed

A. T. Putra, T. Tsunomura, A. Nishida, S. Kamohara, K. Takeuchi, T. Hiramoto

International Conference on Simulation of Semiconductor Processes and Devices, SISPAD   25 - 28   2008

Impact of Atomic Oxide Roughness and Local Gate Depletion on V-th Variation in MOSFETs Reviewed

Arifin Tamsir Putra, Takaaki Tsunomura, Akio Nishida, Shiro Kamohara, Kiyoshi Takeuchi, Toshiro Hiramoto

2008 IEEE SILICON NANOELECTRONICS WORKSHOP   21 - +   2008

Silicon on Thin BOX (SOTB) CMOS for Ultralow Standby Power with Forward-biasing Performance Booster Reviewed

T. Ishigaki, R. Tsuchiya, Y. Morita, H. Yoshimoto, N. Sugii, T. Iwamatsu, H. Oda, Y. Inoue, T. Ohtou, T. Hiramoto, S. Kimura

ESSDERC 2008: PROCEEDINGS OF THE 38TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE   198 - +   2008

Experimental Study on Silicon Nanowire nMOSFET and Single-Electron Transistor at Room Temperature under Uniaxial Tensile Strain Reviewed

YeonJoo Jeong, Kousuke Miyaji, Toshiro Hiramoto

2008 IEEE SILICON NANOELECTRONICS WORKSHOP   37 - 38   2008

Characteristic Modulation of Silicon MOSFETs and Single Electron Transistors with a Movable Gate Electrode Reviewed

J. S. Park, T. Saraya, K. Miyaji, K. Shimizu, A. Higo, K. Takahashi, Y. H. Yi, H. Toshiyoshi, T. Hiramoto

2008 IEEE SILICON NANOELECTRONICS WORKSHOP   9 - 10   2008

Experimental study of mobility in [110]- and [100]-directed multiple silicon nanowire GAA MOSFETs on (100) SOI Reviewed

Jiezhi Chen, Takuya Saraya, Kousuke Miyaji, Ken Shimizu, Toshiro Hiramoto

Digest of Technical Papers - Symposium on VLSI Technology   32 - 33   2008

Hole Mobility Enhancement by [110] Uniaxial Compressive Strain in (110) Oriented Ultra-Thin Body pFETs with SOI Thickness of Less Than 4 nm Reviewed

Ken Shimizu, Toshiro Hiramoto

2008 IEEE SILICON NANOELECTRONICS WORKSHOP   17 - +   2008

Analyses of 5 sigma V-th fluctuation in 65nm-MOSFETs using Takeuchi plot Reviewed

T. Tsunomura, A. Nishida, F. Yano, A. T. Putra, K. Takeuchi, S. Inaba, S. Kamohara, K. Terada, T. Hiramoto, T. Mogami

2008 SYMPOSIUM ON VLSI TECHNOLOGY   121 - +   2008

Novel Long-Range-Extension of Coulomb Blockade Region in Room-Temperature Operating Silicon Single-Hole Transistor Reviewed

S. Lee, K. Miyaji, M. Kobayashi, T. Hiramoto

Silicon Nanoelectronics Workshop, Kyoto   115 - 116   2007.6

2007 IEEE International SOI Conference Reviewed

Toshiro Hiramoto

Proceedings - IEEE International SOI Conference   2007

Understanding random threshold voltage fluctuation by comparing multiple fabs and technologies Reviewed

K. Takeuchi, T. Fukai, T. Tsunomura, A. T. Putra, A. Nishida, S. Kamohara, T. Hiramoto

Technical Digest - International Electron Devices Meeting, IEDM   467 - 470   2007

Transport in ultrathin SOI MOSFETs and silicon nanowire transistors Reviewed

T. Hiramoto

ECS Transactions   11 ( 6 )   403 - 411   2007

Impact of local poly-Si gate depletion on Vth variation in nanoscale MOSFETs investigated by 3D device simulation Reviewed

A. T. Putra, A. Nishida, S. Kamohara, T. Tsunomura, T. Hiramoto

2007 International Semiconductor Device Research Symposium, ISDRS   2007

Silicon VLSI device technology and nanoelectronics Reviewed

Toshiro Hiramoto

MICROPROCESSES AND NANOTECHNOLOGY 2007, DIGEST OF PAPERS   6 - 7   2007

Transport in silicon nanowire and single-electron transistors Invited Reviewed

Toshiro Hiramoto, Kousuke Miyaji, Masaharu Kobayashi

SISPAD 2007: SIMULATION OF SEMICONDUCTOR PROCESSES AND DEVICES 2007   209 - 215   2007

FinFETs with both large body factor and high drive-current Reviewed

Keisuke Takahashi, Arifin Tamsir Putra, Ken Shimizu, Toshiro Hiramoto

2007 INTERNATIONAL SEMICONDUCTOR DEVICE RESEARCH SYMPOSIUM, VOLS 1 AND 2   108 - 109   2007

Transport in ultra-thin-body SOI and silicon nanowire MOSFETs Reviewed

Toshiro Hiramoto, Gen Tsutsui, Ken Shimizu, Masaharu Kobayashi

2007 INTERNATIONAL SEMICONDUCTOR DEVICE RESEARCH SYMPOSIUM, VOLS 1 AND 2   417 - 418   2007

Suppression of Electron Mobility Degradation in (100)-Oriented Double-Gate Ultra-Thin Body nMOSFETs with SOI Thickness of Less Than 2 nm Reviewed

Ken Shimizu, Toshiro Hiramoto

2007 IEEE INTERNATIONAL SOI CONFERENCE PROCEEDINGS   125 - 126   2007

Integration of silicon single-electron transistors operating at room temperature Reviewed

Toshiro Hiramoto

Nanoscaled Semiconductor-on-Insulator Structures and Devices   97 - 112   2007

Integration of silicon single-electron transistors operating at room temperature Reviewed

Toshiro Hiramoto

NATO Security through Science Series C: Environmental Security   97 - 112   2007

Experimental study on mobility universality in (100) ultra thin body nMOSFET with SOI thickness of 5nm Reviewed

Ken Shimizu, Gen Tsutsui, Toshiro Hiramoto

Proceedings - IEEE International SOI Conference   159 - 160   2007

Charge Polarity Dependence of Negative Differential Conductance in Room-Temperature Operating Silicon Single-Charge Transistors Reviewed

Masaharu Kobayashi, Kousuke Miyaji, Toshiro Hiramoto

International Conference on Solid State Devices and Materials (SSDM), Yokohama   2006   806 - 807   2006.9

Emerging nanoscale silicon devices taking advantage of nanostructure physics Reviewed

T. Hiramoto, M. Saitoh, G. Tsutsui

IBM JOURNAL OF RESEARCH AND DEVELOPMENT   50 ( 4-5 )   411 - 418   2006.7

Compact analytical model for room-temperature-operating silicon single-electron transistors with discrete quantum energy levels Reviewed

K Miyaji, M Saitoh, T Hiramoto

IEEE TRANSACTIONS ON NANOTECHNOLOGY   5 ( 3 )   167 - 173   2006.5

Multi-gate MOSFETs with back-gate control Reviewed

Toshiro Hiramoto, Toshiharu Nagumo

2006 IEEE INTERNATIONAL CONFERENCE ON INTEGRATED CIRCUIT DESIGN AND TECHNOLOGY, PROCEEDINGS   80 - +   2006

Mobility enhancement in (110)-oriented ultra-thin-body single-gate and double-gate SOI MOSFETs Reviewed

Toshiro Hiramoto, Gen Tsutsui, Masurni Saitoh, Toshiharu Nagumo, Takuya Saraya

2006 INTERNATIONAL WORKSHOP ON NANO CMOS, PROCEEDINGS   44 - 55   2006

Large Temperature Dependence of Negative Differential Conductance in Room-Temperature Operating Silicon Single-Electron/Single-Hole Transistor Reviewed

Masaharu Kobayashi, Kousuke Miyaji, Masumi Saitoh, Toshiro Hiramoto

International Semiconductor Device Research Symposium 2005, Bethesda, MD, USA   TP3-03   2005.12

Large Temperature Dependence of Coulomb Blockade Oscillations in Room-Temperature Operating Silicon Single-Hole Transistor Reviewed

Masaharu Kobayashi, Masumi Saitoh, Toshiro Hiramoto

International Conference on Solid State Devices and Materials (SSDM) 2005, Kobe, Hyogo   2005   164 - 165   2005.9

Reverse short-channel effect of body factor in low-fin field-effect transistors induced by corner effect Reviewed

T Nagumo, T Hiramoto

JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS   44 ( 1A )   50 - 54   2005.1

Mobility enhancement due to volume inversion in (110)-oriented ultra-thin body double-gate nMOSFETs with body thickness less than 5 nm Reviewed

G Tsutsui, M Saitoh, T Saraya, T Nagumo, T Hiramoto

IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2005, TECHNICAL DIGEST   747 - 750   2005

Emerging devices for post-classical CMOS - From memory, logic to architectures Reviewed

Toshiro Hiramoto

2005 IEEE VLSI-TSA - International Symposium on VLSI Technology - VLSI-TSA-TECH, Proceedings of Technical Papers   1 - 4   2005

Integration and performance improvements of silicon nanocrystal memories Reviewed

T Hiramoto, Kim, I, M Saitoh, K Yanagidaira

Materials and Processes for Nonvolatile Memories   830   37 - 44   2005

V-th control of t(pd)-degradation-free FD SOT MOSFET with extremely thin BOX using variable body-factor scheme Reviewed

T Ohtou, K Yokoyama, T Nagumo, T Hiramoto

2005 IEEE International SOI Conference, Proceedings   101 - 103   2005

Design guideline of multi-gate MOSFETs considering body effect

Toshiharu Nagumo, Toshiro Hiramoto

2005 International Semiconductor Device Research Symposium   2005   205 - 206   2005

On the accuracy of analytical model for room-temperature operating silicon single-electron transistors with discrete quantum energy levels

Kousuke Miyaji, Masaharu Kobayashi, Tetsu Ohtou, Masumi Saitoh, Toshiro Hiramoto

2005 International Semiconductor Device Research Symposium   2005   348 - 349   2005

Superior mobility characteristics in (110)-oriented ultra thin body pMOSFETs with SOI thikness less than 6 nm Reviewed

G Tsutsui, M Saitoh, T Hiramoto

2005 Symposium on VLSI Technology, Digest of Technical Papers   76 - 77   2005

Room-temperature demonstration of low-voltage and tunable static memory based on negative differential conductance in silicon single-electron transistors Reviewed

M Saitoh, H Harata, T Hiramoto

APPLIED PHYSICS LETTERS   85 ( 25 )   6233 - 6235   2004.12

Analytical model of body factor in short channel bulk MOSFETs for low voltage applications Reviewed

A Kumar, T Nagumo, G Tsutsui, T Hiramoto

SOLID-STATE ELECTRONICS   48 ( 10-11 )   1763 - 1766   2004.10

Variable body effect factor fully depleted silicon-on-insulator metal oxide semiconductor field effect transistor for ultra low-power variable-threshold-voltage complementary metal oxide semiconductor applications Reviewed

T Ohtou, T Nagumo, T Hiramoto

JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS   43 ( 6A )   3311 - 3314   2004.6

Room-temperature demonstration of highly-functional single-hole transistor logic based on quantum mechanical effect Reviewed

M Saitoh, T Hiramoto

ELECTRONICS LETTERS   40 ( 13 )   836 - 837   2004.6

Scaling of nanocrystal memory cell by direct tungsten bitline on self-aligned landing plug polysilicon contact Reviewed

GI Kim, K Yanagidaira, T Hiramoto

IEEE ELECTRON DEVICE LETTERS   25 ( 5 )   265 - 267   2004.5

Extension of Coulomb blockade region by quantum confinement in the ultrasmall silicon dot in a single-hole transistor at room temperature Reviewed

M Saitoh, T Hiramoto

APPLIED PHYSICS LETTERS   84 ( 16 )   3172 - 3174   2004.4

Room-temperature observation of negative differential conductance due to large quantum level spacing in silicon single-electron transistor Reviewed

M Saitoh, T Hiramoto

JAPANESE JOURNAL OF APPLIED PHYSICS PART 2-LETTERS   43 ( 2A )   L210 - L213   2004.2

Degradation of body factor (gamma) of single gate fully depleted SOI MOSFETs due to short channel effects Reviewed

A Kumar, T Nagumo, G Tsutsui, T Hiramoto

2004 IEEE INTERNATIONAL SOI CONFERENCE, PROCEEDINGS   58 - 59   2004

Room-temperature demonstration of integrated silicon single-electron transistor circuits for current switching and analog pattern matching Reviewed

M Saitoh, H Harata, T Hiramoto

IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2004, TECHNICAL DIGEST   187 - 190   2004

Enhancement of adjustable threshold voltage range by substrate bias due to quantum confinement in ultrathin body SOI pMOSFETs Reviewed

G Tsutsui, T Nagumo, T Hiramoto

IEEE TRANSACTIONS ON NANOTECHNOLOGY   2 ( 4 )   314 - 318   2003.12

IEEE Transactions on Nanotechnology: Foreword Reviewed

Toshiro Hiramoto, Michiharu Tabe

IEEE Transactions on Nanotechnology   2 ( 4 )   191 - 192   2003.12

Large Coulomb blockade oscillations at room temperature in ultranarrow wire channel MOSFETs formed by slight oxidation process Reviewed

M Saitoh, T Murakami, T Hiramoto

IEEE TRANSACTIONS ON NANOTECHNOLOGY   2 ( 4 )   241 - 245   2003.12

VTCMOS Characteristics and Its Optimum Conditions Predicted by a Compact Analytical Model Reviewed

Hyunsik Im, Takashi Inukai, Hiroyuki Gomyo, Toshiro Hiramoto, Takayasu Sakurai

IEEE Transactions on Very Large Scale Integration (VLSI) Systems   11 ( 5 )   755 - 761   2003.10

Quantum effects and single-electron charging effects in nano-scale silicon MOSFETs at room temperature Reviewed

T Hiramoto, H Majima, M Saitoh

MATERIALS SCIENCE AND ENGINEERING B-SOLID STATE MATERIALS FOR ADVANCED TECHNOLOGY   101 ( 1-3 )   24 - 27   2003.8

Tunneling barrier structures in room-temperature operating silicon single-electron and single-hole transistors Reviewed

M Saitoh, H Majima, T Hiramoto

JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS   42 ( 4B )   2426 - 2428   2003.4

Future electron devices and SOI technology - Semi-planar SOI MOSFETs with sufficient body effect Reviewed

T Hiramoto, T Saito, T Nagumo

JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS   42 ( 4B )   1975 - 1978   2003.4

Current drive improvement using enhanced body effect factor due to finite inversion layer thickness in variable-threshold-voltage complementary MOS (VTCMOS) Reviewed

T Nagumo, T Hiramoto

JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS   42 ( 4B )   1988 - 1992   2003.4

Optimum device consideration for standby power reduction scheme using drain-induced barrier lowering Reviewed

QY Liu, T Sakurai, T Hiramoto

JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS   42 ( 4B )   2171 - 2175   2003.4

Large memory window and long charge-retention time in ultranarrow-channel silicon floating-dot memory Reviewed

M Saitoh, E Nagata, T Hiramoto

APPLIED PHYSICS LETTERS   82 ( 11 )   1787 - 1789   2003.3

Low-Power device design of fully-depleted SOI MOSFETs Reviewed

Toshiro Hiramoto, Toshiaki Nagumo, Tetsu Ohtou

2003 International Semiconductor Device Research Symposium, ISDRS 2003 - Proceedings   388 - 389   2003

Scanning probe nanolithography using self-assembled monolayer for fabrication of single electron transistors Reviewed

Y. Isono, K. Shimamoto, G. Hashiguchi, Y. Mihara, H. Mimura, T. Hiramoto, H. Fujita

TRANSDUCERS 2003 - 12th International Conference on Solid-State Sensors, Actuators and Microsystems, Digest of Technical Papers   1   242 - 245   2003

Integration of fluorinated nano-crystal memory cells with 4.6F(2) size by landing plug polysilicon contact and direct-tungsten bitline Reviewed

IG Kim, K Yanagidaira, T Hiramoto

2003 IEEE INTERNATIONAL ELECTRON DEVICES MEETING, TECHNICAL DIGEST   605 - 608   2003

Room-temperature operation of highly functional single-electron transistor logic based on quantum mechanical effect in ultra-small silicon dot Reviewed

M Saitoh, T Hiramoto

2003 IEEE INTERNATIONAL ELECTRON DEVICES MEETING, TECHNICAL DIGEST   753 - 756   2003

0.5V, 400MHz, VDD-hopping processor with zero VTH FD-SOI technology

Hiroshi Kawaguchi, Kouichi Kanda, Koichi Nose, Sadaaki Hattori, Danardono Dwi Antono, Daisuke Yamada, Takayuki Miyazaki, Kenichi Inagaki, Toshiro Hiramoto, Takayasu Sakurai

Digest of Technical Papers - IEEE International Solid-State Circuits Conference   101 - 481   2003

Experimental study on the mobility universality in ultra thin body SOI pMOSFETs Reviewed

G. Tsutsui, M. Saitoh, T. Nagumo, T. Hiramoto

2003 International Semiconductor Device Research Symposium, ISDRS 2003 - Proceedings   361 - 362   2003

Analytical expression of body factor in short channel bulk MOSFETs Reviewed

Anil Kumar, Toshiharu Nagumo, Gen Tsutsui, Toshiro Hiramoto

2003 International Semiconductor Device Research Symposium, ISDRS 2003 - Proceedings   476 - 477   2003

Effects of oxidation process on the tunneling barrier structures in room-temperature operating silicon single-electron transistors Reviewed

M Saitoh, T Murakami, T Hiramoto

IEEE TRANSACTIONS ON NANOTECHNOLOGY   1 ( 4 )   214 - 218   2002.12

Suppression of short channel effect in triangular parallel wire channel MOSFETs Reviewed

T Saito, T Saraya, T Inukai, H Majima, T Nagumo, T Hiramoto

IEICE TRANSACTIONS ON ELECTRONICS   E85C ( 5 )   1073 - 1078   2002.5

Observation of current staircase due to large quantum level spacing in a silicon single-electron transistor with low parasitic series resistance Reviewed

M Saitoh, T Hiramoto

JOURNAL OF APPLIED PHYSICS   91 ( 10 )   6725 - 6728   2002.5

Origin of critical substrate bias in variable threshold voltage complementary MOS (VTCMOS) Reviewed

T Inukai, H Im, T Hiramoto

JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS   41 ( 4B )   2312 - 2315   2002.4

Physical insight into fractional power dependence of saturation current on gate voltage in advanced short channel MOSFETS (Alpha-Power law model) Reviewed

H Im, M Song, T Hiramoto, T Sakurai

ISLPED'02: PROCEEDINGS OF THE 2002 INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN   13 - 18   2002

Optimum design of device/circuit cooperative schemes for ultra-low power applications Reviewed

T. Hiramoto

ICCDCS 2002 - 4th IEEE International Caracas Conference on Devices, Circuits and Systems   2002

Effects of ultra-narrow channel on characteristics of MOSFET memory with silicon nanocrystal floating gates Reviewed

M Saitoh, E Nagata, T Hiramoto

INTERNATIONAL ELECTRON DEVICES 2002 MEETING, TECHNICAL DIGEST   181 - 184   2002

Transport spectroscopy of the ultrasmall silicon quantum dot in a single-electron transistor Reviewed

M Saitoh, T Saito, T Inukai, T Hiramoto

APPLIED PHYSICS LETTERS   79 ( 13 )   2025 - 2027   2001.9

Effects of discrete quantum levels on electron transport in silicon single-electron transistors with an ultra-small quantum dot Reviewed

M Saitoh, T Hiramoto

IEICE TRANSACTIONS ON ELECTRONICS   E84C ( 8 )   1071 - 1076   2001.8

High drive-current electrically induced body dynamic threshold SOI MOSFET (EIB-DTMOS) with large body effect and low threshold voltage Reviewed

M Takamiya, T Hiramoto

IEEE TRANSACTIONS ON ELECTRON DEVICES   48 ( 8 )   1633 - 1640   2001.8

Optimum device parameters and scalability of variable threshold voltage complementary MOS (VTCMOS) Reviewed

T Hiramoto, M Takamiya, H Koura, T Inukai, H Gomyo, H Kawaguchi, T Sakurai

JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS   40 ( 4B )   2854 - 2858   2001.4

Effects of dot size and its distribution on electron number control in metal-oxide-semiconductor-field-effect-transistor memories based on silicon nanocrystal floating dots Reviewed

HN Wang, N Takahashi, H Majima, T Inukai, M Saitoh, T Hiramoto

JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS   40 ( 3B )   2038 - 2040   2001.3

Large electron addition energy above 250 meV in a silicon quantum dot in a single-electron transistor Reviewed

M Saitoh, N Takahashi, H Ishikuro, T Hiramoto

JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS   40 ( 3B )   2010 - 2012   2001.3

Room Temperature Operation of SiliconSingle Electron Transsistors Fabricated by Anisotropic Etching Technique

Hiramoto Toshiro, Takahashi Nobuyoshi, Ishikuro Hiroki, Saitoh Masumi

Monthly journal of the Institute of Industrial Science, University of Tokyo   53 ( 2 )   116 - 118   2001.2

Suppression of series parasitic resistance and observation of quantum effects in a silicon single-electron transistor Reviewed

M Saitoh, T Hiramoto

PROCEEDINGS OF THE 2001 1ST IEEE CONFERENCE ON NANOTECHNOLOGY   243 - 247   2001

Dynamics of tunneling into charge-tunable Si quantum dots Reviewed

Y Shi, XL Yuan, J Wu, HM Bu, HG Yang, P Han, YD Zheng, T Hiramoto

SUPERLATTICES AND MICROSTRUCTURES   28 ( 5-6 )   387 - 392   2000.11

Separation of effects of statistical impurity number fluctuations and position distribution on Vth fluctuations in scaled MOSFETs Reviewed

Y Yasuda, M Takamiya, T Hiramoto

IEEE TRANSACTIONS ON ELECTRON DEVICES   47 ( 10 )   1838 - 1842   2000.10

Magnetic actuation of bending and torsional vibrations for 2D optical-scanner application Reviewed

A. Garnier, T. Bourouina, H. Fujita, T. Hiramoto, E. Orsier, J. C. Peuzin

Sensors and Actuators, A: Physical   84 ( 1 )   156 - 160   2000.8

A Device Operating by Single Electron

HIRAMOTO Toshiro

IEEJ Transactions on Sensors and Micromachines   120 ( 8 )   518 - 521   2000.8

Experimental evidence for quantum mechanical narrow channel effect in ultra-narrow MOSFET's Reviewed

H Majima, H Ishikuro, T Hiramoto

IEEE ELECTRON DEVICE LETTERS   21 ( 8 )   396 - 398   2000.8

Random telegraph signals and low-frequency noise in n-metal-oxide-semiconductor field-effect transistors with ultranarrow channels Reviewed

HM Bu, Y Shi, XL Yuan, J Wu, SL Gu, YD Zheng, H Majima, H Ishikuro, T Hiramoto

APPLIED PHYSICS LETTERS   76 ( 22 )   3259 - 3261   2000.5

Optimum conditions of body effect factor and substrate bias in variable threshold voltage MOSFETs Reviewed

H Koura, M Takamiya, T Hiramoto

JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS   39 ( 4B )   2312 - 2317   2000.4

Suppression of stand-by tunnel current in ultra-thin gate oxide MOSFETs by dual oxide thickness-multiple threshold voltage CMOS (DOT-MTCMOS) Reviewed

T Inukai, T Hiramoto

JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS   39 ( 4B )   2287 - 2290   2000.4

Low power and low voltage MOSFETs with variable threshold voltage controlled by back-bias Reviewed

T Hiramoto, M Takamiya

IEICE TRANSACTIONS ON ELECTRONICS   E83C ( 2 )   161 - 169   2000.2

Control of Coulomb blockade oscillations in silicon single electron transistors using silicon nanocrystal floating gates Reviewed

N Takahashi, H Ishikuro, T Hiramoto

APPLIED PHYSICS LETTERS   76 ( 2 )   209 - 211   2000.1

Effects of interface traps in silicon-quantum-dots-based memory structures Reviewed

Yuan Xiaoli, Shi Yi, Gu Shulin, Zhu Jianmin, Zheng Youdou, Saito Kenichi, Ishikuro Hiroki, Hiramoto Toshiro

Physica E: Low-Dimensional Systems and Nanostructures   8 ( 2 )   189 - 193   2000

Characteristics of silicon nano-scale devices Reviewed

T Hiramoto, H Majima

2000 INTERNATIONAL CONFERENCE ON SIMULATION OF SEMICONDUCTOR PROCESSES AND DEVICES   179 - 183   2000

Boosted gate MOS (BGMOS): Device/circuit cooperation scheme to achieve leakage-free giga-scale integration Reviewed

T Inukai, M Takamiya, K Nose, H Kawaguchi, T Hiramoto, T Sakurai

PROCEEDINGS OF THE IEEE 2000 CUSTOM INTEGRATED CIRCUITS CONFERENCE   409 - 412   2000

Threshold voltage fluctuations induced by statistical 'position' and 'number' impurity fluctuations in bulk MOSFETs Reviewed

Yuri Yasuda, Makoto Takamiya, Toshiro Hiramoto

Superlattices and Microstructures   28 ( 5-6 )   357 - 361   2000

Characteristic distributions of narrow channel metal-oxide-semiconductor field-effect transistor memories with silicon nanocrystal floating gates Reviewed

E Nagata, N Takahashi, Y Yasuda, T Inukai, H Ishikuro, T Hiramoto

JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS   38 ( 12B )   7230 - 7232   1999.12

Characteristics of narrow channel MOSFET memory based on silicon nanocrystals Reviewed

Y Shi, K Saito, H Ishikuro, T Hiramoto

JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS   38 ( 4B )   2453 - 2456   1999.4

High-performance accumulated back-interface dynamic threshold SOI MOSFET (AB-DTMOS) with large body effect at low supply voltage Reviewed

M Takamiya, T Saraya, TN Duyet, Y Yasuda, T Hiramoto

JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS   38 ( 4B )   2483 - 2486   1999.4

Measurement of energetic and lateral distribution of interface state density in fully-depleted silicon on insulator metal-oxide-semiconductor field-effect transistors Reviewed

TN Duyet, H Ishikuro, Y Shi, M Takamiya, T Saraya, T Hiramoto

JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS   38 ( 4B )   2496 - 2500   1999.4

On the origin of tunneling barriers in silicon single electron and single hole transistors Reviewed

H Ishikuro, T Hiramoto

APPLIED PHYSICS LETTERS   74 ( 8 )   1126 - 1128   1999.2

Fabrication of nano-scale point contact metal-oxide-semiconductor field-effect-transistors using micrometer-scale design rule Reviewed

H Ishikuro, T Hiramoto

JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS   38 ( 1B )   396 - 398   1999.1

Effects of interface traps on charge retention characteristics in silicon-quantum-dot-based metal-oxide-semiconductor diodes Reviewed

Y Shi, K Saito, H Ishikuro, T Hiramoto

JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS   38 ( 1B )   425 - 428   1999.1

Characteristics distribution of narrow channel MOSFET memories with silicon nano-crystal floating gates Reviewed

E. Nagata, N. Takahashi, H. Ishikuro, T. Hiramoto

1999 International Microprocesses and Nanotechnology Conference   86 - 87   1999

Highly integrated single electron devices and giga-bit lithography Reviewed

T. Hiramoto, H. Ishikuro, H. Majima

Journal of Photopolymer Science and Technology   12 ( 3 )   417 - 422   1999

Coulomb blockade in VLSI-compatible multiple-dot and single-dot MOSFETs Reviewed

Toshiro Hiramoto, Hiroki Ishikuro

International Journal of Electronics   86 ( 5 )   591 - 603   1999

Directional current switch using silicon single electron transistors controlled by charge injection into silicon nano-crystal floating dots

Nobuyoshi Takahashi, Hiroki Ishikuro, Toshiro Hiramoto

Technical Digest - International Electron Devices Meeting   371 - 374   1999

Quantum energy and charging energy in point contact MOSFETs acting as single electron transistors

Toshiro Hiramoto, Hiroki Ishikuro

Superlattices and Microstructures   25 ( 1-2 )   263 - 267   1999

Deep sub-0.1-mu m MOSFETs with very thin SOI layer for ultralow-power applications Reviewed

M Takamiya, Y Yasuda, T Hiramoto

ELECTRONICS AND COMMUNICATIONS IN JAPAN PART II-ELECTRONICS   81 ( 11 )   18 - 25   1998.11

Effects of traps on charge storage characteristics in metal-oxide-semiconductor memory structures based on silicon nanocrystals Reviewed

Y Shi, K Saito, H Ishikuro, T Hiramoto

JOURNAL OF APPLIED PHYSICS   84 ( 4 )   2358 - 2360   1998.8