Rigorous electromagnetic simulator for extreme ultraviolet lithography and convolutional neural network reproducing electromagnetic simulations 査読

Hiroyoshi Tanabe, Masayuki Shimoda, Atsushi Takahashi

Journal of Micro/Nanopatterning, Materials, and Metrology   24 ( 02 )   2025年5月

A Novel Data Representation Towards Efficient FPGA-based Quantum Computer Simulation. 査読

Haruhiko Hasegawa, Masayuki Shimoda, Hiroki Nakahara, Takefumi Miyoshi

ISMVL   117 - 122   2025年

Gap Channel Routing with Fixed Wires. 査読

Masayuki Shimoda, Atsushi Takahashi 0001, Kosuke Yanagidaira, Mikiko Hirai, Toshikazu Watanabe, Toshimitsu Iwasawa, Chikaaki Kodama

ISCAS   1 - 5   2025年

UEO Channel Routing Algorithm to Alleviate Local Congestion for Generalized Channels 査読

Zezhong WANG, Hiroto NAKAYAMA, Masayuki SHIMODA, Atsushi TAKAHASHI, Kosuke YANAGIDAIRA, Chikaaki KODAMA

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   2025年

SDG Channel Routing to Minimize Wirelength for Generalized Channel. 査読

Zezhong Wang, Masayuki Shimoda, Atsushi Takahashi 0001

IEICE Trans. Fundam. Electron. Commun. Comput. Sci.   108 ( 3 )   500 - 508   2025年

Gridless Gap Channel Routing with Variable-Width Wires. 査読

Masayuki Shimoda, Atsushi Takahashi 0001

IEICE Trans. Fundam. Electron. Commun. Comput. Sci.   108 ( 3 )   517 - 524   2025年

Gridless Gap Channel Routing to Minimize Wirelength 査読

Masayuki Shimoda, Atsushi Takahashi

IPSJ Transactions on System and LSI Design Methodology   2025年

A Table Look-Up Based Quantum Simulation Accelerator on an FPGA 査読

Haruhiko Hasegawa, Masayuki Shimoda, Hiroki Nakahara, Takefumi Miyoshi

2024 International Conference on Field Programmable Technology (ICFPT)   1 - 2   2024年12月

BCA Channel Routing to Minimize Wirelength for Generalized Channel Problem. 査読

Zezhong Wang, Masayuki Shimoda, Atsushi Takahashi 0001

IEEE International Symposium on Circuits and Systems(ISCAS)   1 - 5   2024年

Wirelength Minimization by Gap Swap-Flip in Gridless Gap Channel Routing. 査読

Masayuki Shimoda, Atsushi Takahashi 0001

ISOCC   213 - 214   2024年

Pre- and post-processing techniques for reinforcement-learning-based routing and spectrum assignment in elastic optical networks. 査読

Takafumi Tanaka, Masayuki Shimoda

Journal of Optical Communications and Networking   15 ( 12 )   1019 - 1019   2023年12月

FPGA-Based Inter-layer Pipelined Accelerators for Filter-Wise Weight-Balanced Sparse Fully Convolutional Networks with Overlapped Tiling. 招待 査読

Masayuki Shimoda, Youki Sada, Hiroki Nakahara

Journal of Signal Processing Systems   93 ( 5 )   499 - 512   2021年

Mask RSA: End-To-End Reinforcement Learning-based Routing and Spectrum Assignment in Elastic Optical Networks. 査読

Masayuki Shimoda, Takafumi Tanaka

European Conference on Optical Communication(ECOC)   1 - 4   2021年

Impact of Operational Mode Selection and Grooming Policies on Auxiliary Graph-Based Multi-layer Network Planning. 査読

Takafumi Tanaka, Masayuki Shimoda

European Conference on Optical Communication(ECOC)   1 - 4   2021年

Deep Reinforcement Learning-based Spectrum Assignment with Multi-metric Reward Function and Assignable Boundary Slot Mask 査読

Masayuki Shimoda, Takafumi Tanaka

26th Optoelectronics and Communications Conference   M4B.3 - M4B.3   2021年

Fast Monocular Depth Estimation on an FPGA. 査読

Youki Sada, Naoto Soga, Masayuki Shimoda, Akira Jinguji, Shimpei Sato, Hiroki Nakahara

2020 IEEE International Parallel and Distributed Processing Symposium Workshops   143 - 146   2020年

SENTEI: Filter-Wise Pruning with Distillation towards Efficient Sparse Convolutional Neural Network Accelerators. 査読

Masayuki Shimoda, Youki Sada, Ryosuke Kuramochi, Shimpei Sato, Hiroki Nakahara

IEICE Transactions on Information & Systems   103-D ( 12 )   2463 - 2470   2020年

An FPGA-based Fine Tuning Accelerator for a Sparse CNN. 査読

Hiroki Nakahara, Akira Jinguji, Masayuki Shimoda, Shimpei Sato

Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays(FPGA)   186 - 186   2019年

An FPGA Implementation of Real-Time Object Detection with a Thermal Camera. 査読

Masayuki Shimoda, Youki Sada, Ryosuke Kuramochi, Hiroki Nakahara

29th International Conference on Field Programmable Logic and Applications(FPL)   413 - 414   2019年

A Dataflow Pipelining Architecture for Tile Segmentation with a Sparse MobileNet on an FPGA. 査読

Youki Sada, Masayuki Shimoda, Akira Jinguji, Hiroki Nakahara

International Conference on Field-Programmable Technology(FPT)   267 - 270   2019年

Filter-Wise Pruning Approach to FPGA Implementation of Fully Convolutional Network for Semantic Segmentation. 査読

Masayuki Shimoda, Youki Sada, Hiroki Nakahara

Applied Reconfigurable Computing - 15th International Symposium(ARC)   371 - 386   2019年

Power Efficient Object Detector with an Event-Driven Camera for Moving Object Surveillance on an FPGA. 査読

Masayuki Shimoda, Shimpei Sato, Hiroki Nakahara

IEICE Transactions on Information & Systems   102-D ( 5 )   1020 - 1028   2019年

Many Universal Convolution Cores for Ensemble Sparse Convolutional Neural Networks. 査読

Ryosuke Kuramochi, Youki Sada, Masayuki Shimoda, Shimpei Sato, Hiroki Nakahara

13th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip(MCSoC)   93 - 100   2019年

GUINNESS: A GUI Based Binarized Deep Neural Network Framework for Software Programmers. 査読

Hiroki Nakahara, Haruyoshi Yonekawa, Tomoya Fujii, Masayuki Shimoda, Shimpei Sato

IEICE Transactions on Information & Systems   102-D ( 5 )   1003 - 1011   2019年

FPGA-Based Training Accelerator Utilizing Sparseness of Convolutional Neural Network. 査読

Hiroki Nakahara, Youki Sada, Masayuki Shimoda, Kouki Sayama, Akira Jinguji, Shimpei Sato

29th International Conference on Field Programmable Logic and Applications(FPL)   180 - 186   2019年

A Tri-State Weight Convolutional Neural Network for an FPGA: Applied to YOLOv2 Object Detector 査読

Hiroki Nakahara, Masayuki Shimoda, Shimpei Sato

2018 International Conference on Field-Programmable Technology (FPT)   298 - 301   2018年12月

A Demonstration of FPGA-Based You Only Look Once Version2 (YOLOv2) 査読

Hiroki Nakahara, Masayuki Shimoda, Shimpei Sato

2018 28th International Conference on Field Programmable Logic and Applications (FPL)   457 - 4571   2018年8月

Demonstration of Object Detection for Event-Driven Cameras on FPGAs and GPUs 査読

Masayuki Shimoda, Shimpei Sato, Hiroki Nakahara

2018 28th International Conference on Field Programmable Logic and Applications (FPL)   461 - 4611   2018年8月

Power Efficient Object Detector with an Event-Driven Camera on an FPGA 査読

Masayuki Shimoda, Shimpei Sato, Hiroki Nakahara

Proceedings of the 9th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies   1 - 6   2018年6月

All binarized convolutional neural network and its implementation on an FPGA 査読

Masayuki Shimoda, Shimpei Sato, Hiroki Nakahara

2017 International Conference on Field Programmable Technology (ICFPT)   291 - 294   2017年12月

A demonstration of the GUINNESS: A GUI based neural NEtwork SyntheSizer for an FPGA 査読

H. Nakahara, H. Yonekawa, T. Fujii, M. Shimoda, S. Sato

2017 27th International Conference on Field Programmable Logic and Applications (FPL)   1 - 1   2017年9月

Development of a Consensus Building System to Support Community Planning that Centers on Information Sharing Using the Map 査読

Koji OBOKATA, Genki ONIYANAGI, Kenta SATO, Masayuki SHIMODA, Hiroki CHIBA

Theory and Applications of GIS   24 ( 2 )   115 - 124   2016年12月

畳み込みニューラルネットワークを用いた単眼深度推定のFPGA実装について—An FPGA Implementation of Monocular Depth Estimation—VLSI設計技術

佐田 悠生, 下田 将之, 佐藤 真平, 中原 啓貴

電子情報通信学会技術研究報告 = IEICE technical report : 信学技報   119 ( 371 )   73 - 78   2020年1月

意味的領域分割のための組み込みシステム向け疎な全畳み込みニューラルネットワークのFPGA実装の検討—Filter-wise Pruning Approach to FPGA Implementation of Fully Convolutional Network for Semantic Segmentation—VLSI設計技術

下田 将之, 佐田 悠生, 中原 啓貴

電子情報通信学会技術研究報告 = IEICE technical report : 信学技報   118 ( 430 )   25 - 30   2019年1月

特徴マップを空間分割したCNNのFPGAにおける小メモリ実装—Spatial-Separable Convolution : Low memory CNN for FPGA—VLSI設計技術

神宮司 明良, 下田 将之, 中原 啓貴

電子情報通信学会技術研究報告 = IEICE technical report : 信学技報   118 ( 457 )   7 - 12   2019年

全2値化畳み込みニューラルネットワークとそのFPGA実装について : FPT2017デザインコンテスト参加報告—All Binarized Convolutional Neural Network and Its implementation on an FPGA : FPT2017 Design Competition Report

下田 将之, 佐藤 真平, 中原 啓貴

電子情報通信学会技術研究報告 = IEICE technical report : 信学技報   117 ( 378 )   7 - 11   2018年1月

FPGA向けディープラーニング開発環境GUINNESSについて—GUINNESS : A GUI based Binarized Deep Neural Network Framework for an FPGA

中原 啓貴, 米川 晴義, 藤井 智也, 下田 将之, 佐藤 真平

電子情報通信学会技術研究報告 = IEICE technical report : 信学技報   117 ( 221 )   51 - 56   2017年9月

畳み込みニューラルネットワークの全2値化に関する一検討—Consideration of All Binarized Convolutional Neural Network

下田 将之, 藤井 智也, 米川 晴義, 佐藤 真平, 中原 啓貴

電子情報通信学会技術研究報告 = IEICE technical report : 信学技報   117 ( 153 )   131 - 136   2017年7月

情報処理システムおよび情報処理方法

大原 拓也, 小田 拓哉, 犬塚 史一, 田中 貴章, 下田 将之

通信システム、振分装置、データ振分方法及びプログラム

小田 拓哉, 大原 拓也, 犬塚 史一, 田中 貴章, 下田 将之

情報処理システム、情報処理方法およびプログラム

大原 拓也, 小田 拓哉, 犬塚 史一, 田中 貴章, 下田 将之

情報処理システム、接続制御方法およびプログラム

大原 拓也, 小田 拓哉, 犬塚 史一, 田中 貴章, 下田 将之

Best Paper Runner-up Award

2019年10月   IEEE International Symposium on Embedded Multicore Socs (MCSoC)  

Iron Award

2019年10月   InnovateFPGA Global Design Contest (APJ Regional Competition)  

若手講演賞

2019年1月   リコンフィギャラブルシステム研究会   意味的領域分割のための組み込みシステム向け疎な全畳み込みニューラルネットワークのFPGA実装の検討

若手奨励賞

2018年1月   システム・アーキテクチャ研究会   全2値化畳み込みニューラルネットワークとその FPGA 実装について FPT2017 デザインコンテスト参加報告