2026/01/23 更新

写真a

イッシキ ツヨシ
一色 剛
ISSHIKI TSUYOSHI
所属
工学院 教授
職名
教授
外部リンク

学位

  • PhD (Computer Engineering) ( University of California, Santa Cruz )

研究分野

  • ものづくり技術(機械・電気電子・化学工学) / 通信工学

学歴

  • カリフォルニア大学サンタクルーズ校大学院   コンピューター工学

    - 1996年

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    国名: アメリカ合衆国

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  • 東京工業大学   工学部   電気電子工学科

    - 1990年

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    国名: 日本国

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経歴

  • 東京工業大学

    2003年

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  • 東京大学   大規模集積システム設計教育研究センター

    2001年 - 2003年

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  • 東京工業大学

    2000年 - 2001年

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  • 東京工業大学

    1996年

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所属学協会

委員歴

  • 電子情報通信学会   VLSI設計技術研究専門委員会委員  

    2006年   

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    団体区分:学協会

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  • 電子情報通信学会   VLSI Design and CAD Algorithms 小特集編集委員  

    2005年   

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    団体区分:学協会

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  • 情報処理学会   システムLSI設計技術研究運営委員会委員  

    2005年   

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    団体区分:学協会

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  • 電子情報通信学会   和文論文誌A編集委員  

    2004年   

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    団体区分:学協会

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  • 電気学会   電子回路技術研究会リコンフィギャラブルLSIとその機能調査専門委員会幹事  

    2002年 - 2004年   

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    団体区分:学協会

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論文

  • Speaker Recognition using fusion of features with Feedforward Artificial Neural Network and Support Vector Machine

    Neha Chauhan, Tsuyoshi Isshiki, Dongju Li

    Proceedings of International Conference on Intelligent Engineering and Management, ICIEM 2020   170 - 176   2020年6月

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    記述言語:英語   掲載種別:研究論文(国際会議プロシーディングス)   出版者・発行元:Institute of Electrical and Electronics Engineers Inc.  

    DOI: 10.1109/ICIEM48762.2020.9160269

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  • Small Area Fingerprint Verification using Deep Convolutional Neural Network

    Nabilah Shabrina, Dongju Li, Tsuyoshi Isshiki

    Proceedings of International Conference on Intelligent Engineering and Management, ICIEM 2020   1 - 6   2020年6月

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    記述言語:英語   掲載種別:研究論文(国際会議プロシーディングス)   出版者・発行元:Institute of Electrical and Electronics Engineers Inc.  

    DOI: 10.1109/ICIEM48762.2020.9160286

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  • Speaker recognition using LPC, MFCC, ZCR features with ANN and SVM classifier for large input database

    Neha Chauhan, Tsuyoshi Isshiki, Dongju Li

    2019 IEEE 4th International Conference on Computer and Communication Systems, ICCCS 2019   130 - 133   2019年2月

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    記述言語:英語   掲載種別:研究論文(国際会議プロシーディングス)   出版者・発行元:Institute of Electrical and Electronics Engineers Inc.  

    DOI: 10.1109/CCOMS.2019.8821751

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  • HOG-based object detection processor design using ASIP methodology 査読

    Shanlin Xiao, Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda

    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E100A ( 12 )   2972 - 2984   2017年12月

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    記述言語:英語   掲載種別:研究論文(国際会議プロシーディングス)   出版者・発行元:Institute of Electronics, Information and Communication, Engineers, IEICE  

    DOI: 10.1587/transfun.E100.A.2972

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  • Design of an Application Specific Instruction Set Processor for Real-Time Object Detection Using AdaBoost Algorithm 査読

    Shanlin Xiao, Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E100A ( 7 )   1384 - 1395   2017年7月

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    記述言語:英語   掲載種別:研究論文(学術雑誌)  

    DOI: 10.1587/transfun.E100.A.1384

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  • Narrow Fingerprint Template Synthesis by Clustering Minutiae Descriptors 査読

    Zhiqiang Hu, Dongju Li, Tsuyoshi Isshiki, Hiroaki Kunieda

    IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS   E100D ( 6 )   1290 - 1302   2017年6月

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    記述言語:英語   掲載種別:研究論文(学術雑誌)  

    DOI: 10.1587/transinf.2016EDP7401

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  • Hybrid Minutiae Descriptor for Narrow Fingerprint Verification 査読

    Zhiqiang Hu, Dongju Li, Tsuyoshi Isshiki, Hiroaki Kunieda

    IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS   E100D ( 3 )   546 - 555   2017年3月

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    記述言語:英語   掲載種別:研究論文(学術雑誌)  

    DOI: 10.1587/transinf.2016EDP7256

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  • An accurate and fast trace-aware performance estimation model for prioritized MPSoC bus with multiple interfering bus-masters 査読

    Farhan Shafiq, Tsuyoshi Isshiki, Dongju Li

    IPSJ Transactions on System LSI Design Methodology   10   13 - 27   2017年2月

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    記述言語:英語   掲載種別:研究論文(学術雑誌)   出版者・発行元:Information Processing Society of Japan  

    DOI: 10.2197/ipsjtsldm.10.13

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  • Hybrid shared-memory and message-passing multiprocessor system-on-chip for UWB MAC layer 査読

    Hao Xiao, Busheng Zheng, Tsuyoshi Isshiki, Hiroaki Kunieda

    IET COMPUTERS AND DIGITAL TECHNIQUES   11 ( 1 )   8 - 15   2017年1月

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    記述言語:英語   掲載種別:研究論文(学術雑誌)  

    DOI: 10.1049/iet-cdt.2015.0217

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  • Fingerprint Spoof Detection using Wavelet based Local Binary Pattern 査読

    Supawan Kumpituck, Dongju Li, Hiroaki Kunieda, Tsuyoshi Isshiki

    EIGHTH INTERNATIONAL CONFERENCE ON GRAPHIC AND IMAGE PROCESSING (ICGIP 2016)   10225   2017年

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    記述言語:英語   掲載種別:研究論文(国際会議プロシーディングス)  

    DOI: 10.1117/12.2266852

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  • Efficient Synchronization for Distributed Embedded Multiprocessors 査読

    Hao Xiao, Ning Wu, Fen Ge, Tsuyoshi Isshiki, Hiroaki Kunieda, Jun Xu, Yuangang Wang

    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS   24 ( 2 )   779 - 783   2016年2月

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    記述言語:英語   掲載種別:研究論文(学術雑誌)  

    DOI: 10.1109/TVLSI.2015.2408345

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  • A fast trace aware statistical based prediction model with burst traffic modeling for contention stall in a priority based MPSoC bus 査読

    Farhan Shafiq, Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda

    IPSJ Transactions on System LSI Design Methodology   9   37 - 48   2016年

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    記述言語:英語   掲載種別:研究論文(学術雑誌)   出版者・発行元:Information Processing Society of Japan  

    DOI: 10.2197/ipsjtsldm.9.37

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  • Fingerprint Authentication on Touch Sensor using Phase-Only Correlation Method 査読

    Nabilah Shabrina, Tsuyoshi Isshiki, Hiroaki Kunieda

    7TH INTERNATIONAL CONFERENCE ON INFORMATION COMMUNICATION TECHNOLOGY FOR EMBEDDED SYSTEMS 2016 (IC-ICTES 2016)   85 - 89   2016年

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    記述言語:英語   掲載種別:研究論文(国際会議プロシーディングス)  

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  • A Design Method for Real-Time Image Denoising Circuit using High-Level Synthesis 査読

    Ikumi Endo, Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda

    7TH INTERNATIONAL CONFERENCE ON INFORMATION COMMUNICATION TECHNOLOGY FOR EMBEDDED SYSTEMS 2016 (IC-ICTES 2016)   30 - 35   2016年

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    記述言語:英語   掲載種別:研究論文(国際会議プロシーディングス)  

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  • An Efficient Embedded Processor for Object Detection Using ASIP Methodology 査読

    Shanlin Xiao, Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda

    2016 IEEE 27TH INTERNATIONAL CONFERENCE ON APPLICATION-SPECIFIC SYSTEMS, ARCHITECTURES AND PROCESSORS (ASAP)   225 - 226   2016年

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    記述言語:英語   掲載種別:研究論文(国際会議プロシーディングス)  

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  • Design of an Efficient ASIP-Based Processor for Object Detection Using AdaBoost Algorithm 査読

    Shanlin Xiao, Dongju Li, Hiroaki Kunieda, Tsuyoshi Isshiki

    7TH INTERNATIONAL CONFERENCE ON INFORMATION COMMUNICATION TECHNOLOGY FOR EMBEDDED SYSTEMS 2016 (IC-ICTES 2016)   96 - 99   2016年

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    記述言語:英語   掲載種別:研究論文(国際会議プロシーディングス)  

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  • Register-Based Process Virtual Machine Acceleration Using Hardware Extension with Hybrid Execution 査読

    Surachai Thongkaew, Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E98A ( 12 )   2505 - 2518   2015年12月

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    記述言語:英語   掲載種別:研究論文(学術雑誌)  

    DOI: 10.1587/transfun.E98.A.2505

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  • Efficient design exploration framework of SW/HW systems based on tightly-coupled thread model 査読

    Arif Ullah Khan, Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda

    IPSJ Transactions on System LSI Design Methodology   8   38 - 50   2015年2月

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    記述言語:英語   掲載種別:研究論文(学術雑誌)   出版者・発行元:Information Processing Society of Japan  

    DOI: 10.2197/ipsjtsldm.8.38

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  • Online Detection of Spoof Fingers for Smartphone-based Applications 査読

    Dongju Li, Hiroaki Kunieda, Supawan Kumpituck, Tsuyoshi Isshiki

    2015 IEEE 17TH INTERNATIONAL CONFERENCE ON HIGH PERFORMANCE COMPUTING AND COMMUNICATIONS, 2015 IEEE 7TH INTERNATIONAL SYMPOSIUM ON CYBERSPACE SAFETY AND SECURITY, AND 2015 IEEE 12TH INTERNATIONAL CONFERENCE ON EMBEDDED SOFTWARE AND SYSTEMS (ICESS)   1292 - 1297   2015年

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    記述言語:英語   掲載種別:研究論文(国際会議プロシーディングス)  

    DOI: 10.1109/HPCC-CSS-ICESS.2015.322

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  • Branch Bitstream Machine Instruction-level System Tracing 査読

    Pipat Methavanitpong, Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda

    2015 6TH INTERNATIONAL CONFERENCE OF INFORMATION AND COMMUNICATION TECHNOLOGY FOR EMBEDDED SYSTEMS (IC-ICTES)   2015年

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    記述言語:英語   掲載種別:研究論文(国際会議プロシーディングス)  

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  • SIFT-based Algorithm for Fingerprint authentication on smartphone 査読

    Masao Yamazaki, Dongju Li, Tsuyoshi Isshiki, Hiroaki Kunieda

    2015 6TH INTERNATIONAL CONFERENCE OF INFORMATION AND COMMUNICATION TECHNOLOGY FOR EMBEDDED SYSTEMS (IC-ICTES)   2015年

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    記述言語:英語   掲載種別:研究論文(国際会議プロシーディングス)  

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  • C-Based RTL Design Method for Circuit Switched Network on Chips 査読

    Kensuke Fujiya, Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda

    2015 6TH INTERNATIONAL CONFERENCE OF INFORMATION AND COMMUNICATION TECHNOLOGY FOR EMBEDDED SYSTEMS (IC-ICTES)   2015年

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    記述言語:英語   掲載種別:研究論文(国際会議プロシーディングス)  

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  • Dalvik bytecode acceleration using fetch/decode hardware extension 査読

    Surachai Thongkaew, Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda

    Journal of Information Processing   23 ( 2 )   118 - 130   2015年

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    記述言語:英語   掲載種別:研究論文(学術雑誌)   出版者・発行元:Information Processing Society of Japan  

    DOI: 10.2197/ipsjjip.23.118

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  • Retargeting Derivative-ASIP with Assembly Converter Tool 査読

    Agus Bejo, Dongju Li, Tsuyoshi Isshiki, Hiroaki Kunieda

    IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS   E97D ( 5 )   1188 - 1195   2014年5月

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    記述言語:英語   掲載種別:研究論文(学術雑誌)  

    DOI: 10.1587/transinf.E97.D.1188

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  • Distributed synchronization for message-passing based embedded multiprocessors 査読

    Hao Xiao, Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda, Guanyu Zhu

    Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors   82 - 83   2014年

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    記述言語:英語   掲載種別:研究論文(国際会議プロシーディングス)   出版者・発行元:Institute of Electrical and Electronics Engineers Inc.  

    DOI: 10.1109/ASAP.2014.6868640

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  • Dalvik Bytecode Acceleration Using Fetch/Decode Hardware Extension With Hybrid Execution 査読

    Surachai Thongkaew, Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda

    2014 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS)   375 - 378   2014年

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    記述言語:英語   掲載種別:研究論文(国際会議プロシーディングス)  

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  • Distributed Synchronization for Message-passing based Embedded Multiprocessors 査読

    Hao Xiao, Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda, Guanyu Zhu

    PROCEEDINGS OF THE 2014 IEEE 25TH INTERNATIONAL CONFERENCE ON APPLICATION-SPECIFIC SYSTEMS, ARCHITECTURES AND PROCESSORS (ASAP 2014)   82 - +   2014年

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    記述言語:英語   掲載種別:研究論文(国際会議プロシーディングス)  

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  • Custom Instruction Search for Application Specific Instruction-Set Processor using Guided Simulated Annealing 査読

    Amr Fathy, Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda

    2014 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS)   367 - 370   2014年

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    記述言語:英語   掲載種別:研究論文(国際会議プロシーディングス)  

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  • A method of software development tool and hardware generation for ASIP with a co-processor based on the derivative ASIP approach 査読

    Agus Bejo, Dongju Li, Tsuyoshi Isshiki, Hiroaki Kunieda

    Journal of Information Processing   22 ( 2 )   131 - 141   2014年

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    記述言語:英語   掲載種別:研究論文(学術雑誌)   出版者・発行元:Information Processing Society of Japan  

    DOI: 10.2197/ipsjjip.22.131

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  • A Design of High Performance Parallel Architecture and Communication for Multi-ASIP Based Image Processing Engine 査読

    Hsuan-Chun Liao, Mochamad Asri, Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E96A ( 6 )   1222 - 1235   2013年6月

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    記述言語:英語   掲載種別:研究論文(学術雑誌)  

    DOI: 10.1587/transfun.E96.A.1222

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  • Flexible and high performance ASIPs for pixel level image processing and two dimensional image processing 査読

    Hsuan-Chun Liao, Mochamad Asri, Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda

    Journal of Information Processing   21 ( 3 )   552 - 562   2013年

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    記述言語:英語   掲載種別:研究論文(学術雑誌)  

    DOI: 10.2197/ipsjjip.21.552

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  • A High Level Design of Reconfigurable and High-Performance ASIP Engine for Image Signal Processing 査読

    Hsuan-Chun Liao, Mochamad Asri, Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E95A ( 12 )   2373 - 2383   2012年12月

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    記述言語:英語   掲載種別:研究論文(学術雑誌)  

    DOI: 10.1587/transfun.E95.A.2373

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  • A Low-Cost and Energy-Efficient Multiprocessor System-on-Chip for UWB MAC Layer 査読

    Hao Xiao, Tsuyoshi Isshiki, Arif Ullah Khan, Dongju Li, Hiroaki Kunieda, Yuko Nakase, Sadahiro Kimura

    IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS   E95D ( 8 )   2027 - 2038   2012年8月

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    記述言語:英語   掲載種別:研究論文(学術雑誌)  

    DOI: 10.1587/transinf.E95.D.2027

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  • Narrow Fingerprint Sensor Verification with Template Updating Technique 査読

    SangWoo Sin, Ru Zhou, Dongju Li, Tsuyoshi Isshiki, Hiroaki Kunieda

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E95A ( 1 )   346 - 353   2012年1月

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    記述言語:英語   掲載種別:研究論文(学術雑誌)  

    DOI: 10.1587/transfun.E95.A.346

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  • Optimized communication and synchronization for embedded multiprocessors using ASIP methodology 査読

    Hao Xiao, Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda, Yuko Nakase, Sadahiro Kimura

    IPSJ Transactions on System LSI Design Methodology   5   118 - 132   2012年

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    記述言語:英語   掲載種別:研究論文(学術雑誌)  

    DOI: 10.2197/ipsjtsldm.5.118

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  • Hybrid Shared-memory and Message-passing Multiprocessor System-on-Chip for UWB MAC 査読

    Hao Xiao, Tsuyoshi Isshiki, Hiroaki Kunieda, Yuko Nakase, Sadahiro Kimura

    2012 IEEE INTERNATIONAL CONFERENCE ON CONSUMER ELECTRONICS (ICCE)   658 - +   2012年

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    記述言語:英語   掲載種別:研究論文(国際会議プロシーディングス)  

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  • A Reconfigurable High Performance ASIP Engine for Image Signal Processing 査読

    Hsuanchun Liao, Mochamad Asri, Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda

    2012 IEEE 26TH INTERNATIONAL PARALLEL AND DISTRIBUTED PROCESSING SYMPOSIUM WORKSHOPS & PHD FORUM (IPDPSW)   368 - 375   2012年

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    記述言語:英語   掲載種別:研究論文(国際会議プロシーディングス)  

    DOI: 10.1109/IPDPSW.2012.45

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  • A Reconfigurable ASIP-based Approach for High Performance Image Signal Processing 査読

    Mochamad Asri, Hsuan-Chun Liao, Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda

    2012 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS)   611 - 614   2012年

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    記述言語:英語   掲載種別:研究論文(国際会議プロシーディングス)  

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  • Application-Specific Instruction-Set Processor Design Methodology for Wireless Image Transmission Systems 査読

    Tsuyoshi Isshiki, Hao Xiao, Hsuan-Chun Liao, Dongju Li, Hiroaki Kunieda

    2012 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC)   293 - 296   2012年

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    記述言語:英語   掲載種別:研究論文(国際会議プロシーディングス)  

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  • Robust multiple minutiae partitions for fingerprint authentication 査読

    Hao Ni, Dongju Li, Tsuyoshi Isshiki, Hiroaki Kunieda

    Proceedings - 2012 International Symposium on Biometrics and Security Technologies, ISBAST 2012   35 - 44   2012年

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    記述言語:英語   掲載種別:研究論文(国際会議プロシーディングス)  

    DOI: 10.1109/ISBAST.2012.19

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  • Ultrafast fingerprint indexing for embedded systems 査読

    Ru Zhou, Sang Woo Sin, Dongju Li, Tsuyoshi Isshiki, Hiroaki Kunieda

    OPTICAL ENGINEERING   50 ( 10 )   2011年10月

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    記述言語:英語   掲載種別:研究論文(学術雑誌)  

    DOI: 10.1117/1.3633336

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  • Practical Orientation Field Estimation for Embedded Fingerprint Recognition Systems 査読

    Yukun Liu, Dongju Li, Tsuyoshi Isshiki, Hiroaki Kunieda

    IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS   E94D ( 9 )   1792 - 1799   2011年9月

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    記述言語:英語   掲載種別:研究論文(学術雑誌)  

    DOI: 10.1587/transinf.E94.D.1792

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  • Unique Fingerprint-Image-Generation Algorithm for Line Sensors 査読

    Hao Ni, Dongju Li, Tsuyoshi Isshiki, Hiroaki Kunieda

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E94A ( 2 )   781 - 788   2011年2月

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    記述言語:英語   掲載種別:研究論文(学術雑誌)  

    DOI: 10.1587/transfun.E94.A.781

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  • Adaptive SIFT-based algorithm for specific fingerprint verification 査読

    Ru Zhou, Sang Woo Sin, Dongju Li, Tsuyoshi Isshiki, Hiroaki Kunieda

    2011 International Conference on Hand-Based Biometrics, ICHB 2011 - Proceedings   41 - 46   2011年

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    記述言語:英語   掲載種別:研究論文(国際会議プロシーディングス)  

    DOI: 10.1109/ICHB.2011.6094354

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  • A novel similarity measurement for minutiae-based fingerprint verification 査読

    Yukun Liu, Dongju Li, Tsuyoshi Isshiki, Hiroaki Kunieda

    IEEE 4th International Conference on Biometrics: Theory, Applications and Systems, BTAS 2010   2010年

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    記述言語:英語   掲載種別:研究論文(国際会議プロシーディングス)  

    DOI: 10.1109/BTAS.2010.5634521

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  • Entropy Decoding Processor for Modern Multimedia Applications 査読

    Sumek Wisayataksin, Dongju Li, Tsuyoshi Isshiki, Hiroaki Kunieda

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E92A ( 12 )   3248 - 3257   2009年12月

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    記述言語:英語   掲載種別:研究論文(学術雑誌)  

    DOI: 10.1587/transfun.E92.A.3248

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  • Trace-Driven Workload Simulation Method for Multiprocessor System-On-Chips 査読

    Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda, Toshio Isomura, Kazuo Satou

    DAC: 2009 46TH ACM/IEEE DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2   232 - +   2009年

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    記述言語:英語   掲載種別:研究論文(国際会議プロシーディングス)  

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  • Multiprocessor SoC Design Framework on Tightly-Coupled Thread Model 査読

    Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda

    ISOCC: 2008 INTERNATIONAL SOC DESIGN CONFERENCE, VOLS 1-3   56 - 61   2008年

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    記述言語:英語   掲載種別:研究論文(国際会議プロシーディングス)  

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  • H.264/AVC decoder SoC towards the low cost mobile video player 査読

    Sumek Wisayataksin, Dongju Li, Tsuyoshi Isshiki, Hiroaki Kunieda

    20TH ANNIVERSARY IEEE INTERNATIONAL SOC CONFERENCE, PROCEEDINGS   151 - 154   2007年

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    記述言語:英語   掲載種別:研究論文(国際会議プロシーディングス)  

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  • Novel SoC architecture embedded bit serial FPGA 査読

    YW Wang, DJ Li, T Isshiki, H Kunieda

    PROCEEDINGS OF THE 2004 IEEE ASIA-PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS, VOL 1 AND 2   133 - 136   2004年

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    記述言語:英語   掲載種別:研究論文(国際会議プロシーディングス)  

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  • High density bit-serial FPGA with LUT embedding shift register function. 査読

    T Isshiki, A Ohta, T Watanabe, T Nakada, K Akahane, Sisla, I, D Li, H Kunieda

    APCCAS 2002: ASIA-PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS, VOL 1, PROCEEDINGS   475 - 480   2002年

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    記述言語:英語   掲載種別:研究論文(国際会議プロシーディングス)  

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  • Efficient method for face region quality enhancement in low bit rate video coding 査読

    R Adiono, T Isshiki, D Li, H Kunieda

    APCCAS 2002: ASIA-PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS, VOL 1, PROCEEDINGS   549 - 553   2002年

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    記述言語:英語   掲載種別:研究論文(国際会議プロシーディングス)  

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  • Cost-effective shadowing method using the ED-buffer on an adaptive light cube 査読

    T Isshiki, M Ishikawa, H Kunieda

    VISUAL COMPUTER   16 ( 8 )   453 - 468   2000年

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    記述言語:英語   掲載種別:研究論文(学術雑誌)  

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  • Efficient anti-aliasing algorithm for computer generated images 査読

    T Isshiki, H Kunieda

    ISCAS '99: PROCEEDINGS OF THE 1999 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 4   532 - 535   1999年

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    記述言語:英語   掲載種別:研究論文(国際会議プロシーディングス)  

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  • Array architecture and design for image window operation processing ASICs

    Dongju Li, Li Jiang, Tsuyoshi Isshiki, Hiroaki Kunieda

    Proceedings - IEEE International Symposium on Circuits and Systems   2   474 - 477   1998年

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    記述言語:英語   掲載種別:研究論文(国際会議プロシーディングス)   出版者・発行元:IEEE  

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  • Bit-serial pipeline synthesis and layout for large-scale configurable systems 査読

    T Isshiki, WWM Dai, H Kunieda

    PROCEEDINGS OF THE ASP-DAC '97 - ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE 1997   441 - 446   1996年

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    記述言語:英語   掲載種別:研究論文(国際会議プロシーディングス)  

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  • PARALLEL PROCESSING ARCHITECTURE DESIGN FOR 2-DIMENSIONAL IMAGE-PROCESSING USING SPATIAL EXPANSION OF THE SIGNAL FLOW GRAPH 査読

    T ISSHIKI, Y TAKEUCHI, H KUNIEDA

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E76A ( 3 )   337 - 348   1993年3月

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    記述言語:英語   掲載種別:研究論文(学術雑誌)  

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  • SYSTEMATIC ARCHITECTURE DESIGN FOR HIGHLY PARALLEL IMAGE-PROCESSING ARRAY 査読

    T ISSHIKI, Y TAKEUCHI, H KUNIEDA

    PROCEEDINGS OF THE 35TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1 AND 2   299 - 302   1992年

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    記述言語:英語   掲載種別:研究論文(国際会議プロシーディングス)  

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▼全件表示

MISC

  • Dalvik Bytecode Acceleration Using Fetch/Decode Hardware Extension (Preprint)

    Surachai Thongkaew, Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda

    情報処理学会論文誌   56 ( 2 )   2015年2月

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    記述言語:英語   出版者・発行元:一般社団法人情報処理学会  

    The Dalvik virtual machine (Dalvik VM) is an essential piece of software that runs applications on the Android operating system. Android application programs are commonly written in the Java language and compiled to Java bytecode. The Java bytecode is converted to Dalvik bytecode (Dalvik Executable file) which is interpreted by the Dalvik VM on typical Android devices. The significant disadvantage of interpretation is a much slower speed of program execution compared to direct machine code execution on the host CPU. However, there are many techniques to improve the performance of Dalvik VM. A typical methodology is just-in-time compilation which converts frequently executed sequences of interpreted instruction to host machine code. Other methodologies include dedicated bytecode processors and architectural extension on existing processors. In this paper, we propose an alternative methodology, "Fetch & Decode Hardware Extension," to improve the performance of Dalvik VM. The Fetch & Decode Hardware Extension is a specially designed hardware component to fetch and decode Dalvik bytecode directly, while the core computations within the virtual registers are done by the optimized Dalvik bytecode software handler. The experimental results show the speed improvements on Arithmetic instructions, loop & conditional instructions and method invocation & return instructions, can be achieved up to 2.4x, 2.7x and 1.8x, respectively. The approximate size of the proposed hardware extension is 0.03mm2 (equivalent to 10.56 Kgate) and consumes additional power of only 0.23mW. The stated results are obtained from logic synthesis using the TSMC 90nm technology @ 200MHz clock frequency.------------------------------This is a preprint of an article intended for publication Journal ofInformation Processing(JIP). This preprint should not be cited. Thisarticle should be cited as: Journal of Information Processing Vol.23(2015) No.2 (online)------------------------------

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  • A Method of Software Development Tool and Hardware Generation for ASIP with a Co-processor based on the Derivative ASIP Approach

    Agus Bejo, Dongju Li, Tsuyoshi Isshiki, Hiroaki Kunieda

    情報処理学会論文誌   55 ( 2 )   2014年2月

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    記述言語:英語  

    In this paper, a processor design method using the Derivative ASIP approach is introduced. The concept of Derivative ASIP is basically to develop an ASIP architecture based on existing GPP processor architecture in order to diminish the design effort and shorten the design time. In this approach, the base processor architecture can be enhanced with more co-processor/instruction extensions quickly since all the required development tools have been available for the base processor. In order to support the Derivative ASIP approach, a new tool called the Co-processor/Instruction Extension Generator Tool is developed. This tool generates complementary files suitable for updating the base processor architecture with co-processor/instruction extensions. A complete set of software development tools consisting of a compiler, assembler, disassembler, linker, debugger, simulator and also hardware implementation for the modified ASIP architecture can be generated automatically by using these complementary files. With our proposed tool, a new co-processor/instruction extension can be designed and added to the base architecture more easily. It contributes to the reduction of the architecture exploration time in the design stage. Derivative ARM ASIP architecture enhanced with instruction extensions for the AES algorithm and a co-processor for the fingerprint navigation algorithm is given to demonstrate the effectiveness of our approach.------------------------------This is a preprint of an article intended for publication Journal ofInformation Processing(JIP). This preprint should not be cited. Thisarticle should be cited as: Journal of Information Processing Vol.22(2014) No.2 (online)DOI http://dx.doi.org/10.2197/ipsjjip.22.131------------------------------In this paper, a processor design method using the Derivative ASIP approach is introduced. The concept of Derivative ASIP is basically to develop an ASIP architecture based on existing GPP processor architecture in order to diminish the design effort and shorten the design time. In this approach, the base processor architecture can be enhanced with more co-processor/instruction extensions quickly since all the required development tools have been available for the base processor. In order to support the Derivative ASIP approach, a new tool called the Co-processor/Instruction Extension Generator Tool is developed. This tool generates complementary files suitable for updating the base processor architecture with co-processor/instruction extensions. A complete set of software development tools consisting of a compiler, assembler, disassembler, linker, debugger, simulator and also hardware implementation for the modified ASIP architecture can be generated automatically by using these complementary files. With our proposed tool, a new co-processor/instruction extension can be designed and added to the base architecture more easily. It contributes to the reduction of the architecture exploration time in the design stage. Derivative ARM ASIP architecture enhanced with instruction extensions for the AES algorithm and a co-processor for the fingerprint navigation algorithm is given to demonstrate the effectiveness of our approach.------------------------------This is a preprint of an article intended for publication Journal ofInformation Processing(JIP). This preprint should not be cited. Thisarticle should be cited as: Journal of Information Processing Vol.22(2014) No.2 (online)DOI http://dx.doi.org/10.2197/ipsjjip.22.131------------------------------

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  • Flexible and High Performance ASIPs for Pixel Level Image Processing and Two Dimensional Image Processing

    Hsuan-ChunLiao, Mochamad Asri, Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda

    情報処理学会論文誌   54 ( 7 )   2013年7月

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    記述言語:英語  

    An image processing engine is an important component in generating high quality images in video systems. Processing during capture and display are non-standard and vary from case by case, hence, the flexibility of image processing engines has turned out to be an important issue. The conventional hardware type of image processing engine such as an Application Specific Integrated Circuit (ASIC) is not applicable for this case. In order to increase design reusability and ease time-to-market pressures, Application Specific Instruction-set Processors (ASIP) which provide high flexibility and high computational efficiency have emerged as a promising solution. In this paper, we present two ASIPs. PXL ASIP, which has a reconfigurable multi bank memory module and an SIMD type computation pipeline, is designed for pixel level image processing, while 2D ASIP, which has slide register module and reconfigurable ALU modules, is designed for 2D image processing. PXL ASIP can perform 4 to 10 times faster compared to its base processor, and 2D ASIP can perform 5 to 43 times faster compared to its base processor.------------------------------This is a preprint of an article intended for publication Journal ofInformation Processing(JIP). This preprint should not be cited. Thisarticle should be cited as: Journal of Information Processing Vol.21(2013) No.3 (online)DOI http://dx.doi.org/10.2197/ipsjjip.21.552------------------------------An image processing engine is an important component in generating high quality images in video systems. Processing during capture and display are non-standard and vary from case by case, hence, the flexibility of image processing engines has turned out to be an important issue. The conventional hardware type of image processing engine such as an Application Specific Integrated Circuit (ASIC) is not applicable for this case. In order to increase design reusability and ease time-to-market pressures, Application Specific Instruction-set Processors (ASIP) which provide high flexibility and high computational efficiency have emerged as a promising solution. In this paper, we present two ASIPs. PXL ASIP, which has a reconfigurable multi bank memory module and an SIMD type computation pipeline, is designed for pixel level image processing, while 2D ASIP, which has slide register module and reconfigurable ALU modules, is designed for 2D image processing. PXL ASIP can perform 4 to 10 times faster compared to its base processor, and 2D ASIP can perform 5 to 43 times faster compared to its base processor.------------------------------This is a preprint of an article intended for publication Journal ofInformation Processing(JIP). This preprint should not be cited. Thisarticle should be cited as: Journal of Information Processing Vol.21(2013) No.3 (online)DOI http://dx.doi.org/10.2197/ipsjjip.21.552------------------------------

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  • Optimized Communication and Synchronization for Embedded Multiprocessors Using ASIP Methodology (IPSJ Transactions on System LSI Design Methodology Vol.5)

    XIAO HAO, ISSHIKI TSUYOSHI, LI DONGJU

    情報処理学会論文誌 論文誌トランザクション   2012 ( 1 )   118 - 132   2012年10月

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    記述言語:英語   出版者・発行元:情報処理学会  

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  • Orientation Field Estimation for Embedded Fingerprint Authentication System

    Wei Tang, Dongju Li, Tsuyoshi Isshiki, Hiroaki Kunieda

    IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS   E93D ( 7 )   1918 - 1926   2010年7月

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  • A unified performance estimation method for hardware and software components in multiprocessor system-on-chips

    Arif Ullah Khan, Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda

    IPSJ Transactions on System LSI Design Methodology   3   194 - 206   2010年

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  • Weed Detection over Between-Row of Sugarcane Fields Using Machine Vision with Shadow Robustness Technique for Variable Rate Herbicide Applicator

    Apimuk Muangkasem, Somying Thainimit, Rachaporn Keinprasit, TSUYOSHI ISSHIKI, Rattana Tangwongkit

    Energy Research Journal   1 ( 2 )   141 - 145   2010年

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  • A Unified Performance Estimation Method for Hardware and Software Components in Multiprocessor System-On-Chips

    ARIF ULLAH KHAN, TSUYOSHI ISSHIKI, DONGJU LI, hiroaki kunieda

    IPSJ Transactions on System LSI Design Methodology   3   194 - 206   2010年

  • Weed Detection over Between-Row of Sugarcane Fields Using Machine Vision with Shadow Robustness Technique for Variable Rate Herbicide Applicator

    Apimuk Muangkasem, Somying Thainimit, Rachaporn Keinprasit, TSUYOSHI ISSHIKI, Rattana Tangwongkit

    Energy Research Journal   1 ( 2 )   141 - 145   2010年

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  • バンコクだより 東工大から世界へ ~タイ国との連携大学院TAIST-Tokyo Techの取り組み~

    杉野暢彦, 一色 剛, 西原明法, 國枝博昭

    電子情報通信学会 基礎・境界ソサイエティ Fundamentals Review   12 ( 4 )   102 - 105   2009年

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    出版者・発行元:The Institute of Electronics, Information and Communication Engineers  

    DOI: 10.1587/essfr.2.4_102

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  • Decomposition of task-level concurrency on C programs applied to the design of multiprocessor SoC

    Mohammad Zalfany Urfianto, Tsuyoshi Isshiki, Arif Ullah Khan, Dongju Li, Hiroaki Kunieda

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E91A ( 7 )   1748 - 1756   2008年7月

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  • A Multiprocessor SoC architecture with efficient communication infrastructure and advanced compiler support for easy application development

    Mohammad Zalfany Urfianto, Tsuyoshi Isshiki, Arif Ullah Khan, Dongju Li, Hiroaki Kunieda

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E91A ( 4 )   1185 - 1196   2008年4月

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  • Low cost SoC design of H.264/AVC decoder for handheld video player

    Sumek Wisayataksin, Dongju Li, Tsuyoshi Isshiki, Hiroaki Kunieda

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E91A ( 4 )   1197 - 1205   2008年4月

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  • Fast and Accurate Singular Point Detection and Classfication on Quantized Orientation Field of Fingerprints

    Wei Tang, Dongju Li, Tsuyoshi Isshiki, Hiroaki Kunieda

    IEICE transaction on Information and System   accepted   2008年

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  • Minutia Shape Indexing for Embedded Fingerprint Identification

    Wei Tang, Dongju Li, Tsuyoshi Isshiki, Hiroaki Kunieda

    IEICE transaction on Information and System   submitted   2008年

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  • Fast and Accurate Singular Point Detection and Classfication on Quantized Orientation Field of Fingerprints

    Wei Tang, Dongju Li, Tsuyoshi Isshiki, Hiroaki Kunieda

    IEICE transaction on Information and System   accepted   2008年

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  • Minutia Shape Indexing for Embedded Fingerprint Identification

    Wei Tang, Dongju Li, Tsuyoshi Isshiki, Hiroaki Kunieda

    IEICE transaction on Information and System   submitted   2008年

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  • 組込みシステム実現技術

    一色剛

    映像情報メディア学会誌   61 ( 7 )   901 - 904   2007年9月

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    記述言語:英語  

    DOI: 10.3169/itej.61.901

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  • A fingerprint matching using minutia ridge shape for low cost match-on-card systems

    AS Rikin, DJ Li, T Isshiki, H Kunieda

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E88A ( 5 )   1305 - 1312   2005年5月

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  • A Novel Fingerprint SoC with Bit Serial FPGA Engine

    Y. Wang, D. Li, T, Isshiki H. Kunieda

    IPSJ Digital Courier   Vol.46   1366 - 1373   2005年

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    記述言語:英語   出版者・発行元:Information Processing Society of Japan  

    The paper presents firstly a novel system-on-chip (SoC) architecure consisting of a 32-bit RISC processor, on-chip memory, state-of-the art IPs and embedded full-custom bit serial FPGA(BSFPGA) I/O interface. The system inherits the compatibility of AMBA architecture, the flexibility of BSFPGA, so that it can be used for various types of applications without any additional I/O pins. Example application is to realize fingerprint authentication system in a chip. The paper presents secondly design flow for SoC, including a full-custom block. With RTL model for BSFPGA, it enables a timing simulation of the total system in RTL level and a timing verification in transistor level.

    DOI: 10.2197/ipsjdc.1.226

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  • A Novel Fingerprint SoC with Bit Serial FPGA Engine

    Y. Wang, D. Li, T, Isshiki H. Kunieda

    Vol.46   1366 - 1373   2005年

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  • A fingerprint matching using minutia ridge shape for low cost Match-on-Card systems

    Andy Surya Rikin, Dongju Li, Tsuyoshi Isshiki, Hiroaki Kunieda

    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E88-A ( 5 )   1305 - 1312   2005年

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    記述言語:英語   出版者・発行元:Institute of Electronics, Information and Communication, Engineers, IEICE  

    DOI: 10.1093/ietfec/e88-a.5.1305

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  • Fast fingerprint classification based on direction pattern

    JQ Qi, DJ Li, T Isshiki, H Kunieda

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E87A ( 8 )   1887 - 1892   2004年8月

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    記述言語:英語  

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  • Binary line-pattern algorithm for embedded fingerprint authentication system

    JQ Qi, DJ Li, T Isshiki, H Kunieda

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E87A ( 8 )   1879 - 1886   2004年8月

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    記述言語:英語  

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  • Binary Line-Pattern Algorithm for Embedded Fingerprint Authentication System

    J. Qi, D. Li, T, Isshiki H. Kunieda

    IEICE Trans. Fundamentals   vol.E87-A   1879 - 1886   2004年

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  • Fast Fingerprint Classification based on Direction Pattern

    J. Qi, D. Li, T, Isshiki H. Kunieda

    IEICE Trans. Fundamentals   vol.E87-A   1887 - 1892   2004年

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  • New rate control method with minimum skipped frames for very low delay in H.263+codec

    T Adiono, T Isshiki, C Honsawek, K Ito, DJ Li, H Kunieda

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E85A ( 6 )   1396 - 1407   2002年6月

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    記述言語:英語  

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  • System-MSPA design of H.263+video encoder/decoder LSI for videotelephony applications

    C Honsawek, K Ito, T Ohtsuka, T Adiono, DJ Li, T Isshiki, H Kunieda

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E84A ( 11 )   2614 - 2622   2001年11月

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    記述言語:英語  

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  • Cost-effective shadowing method using the ED-buffer on an adaptive light cube

    Tsuyoshi Isshiki, Makoto Ishikawa, Hiroaki Kunieda

    Visual Computer   16 ( 8 )   453 - 468   2000年11月

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    記述言語:英語   出版者・発行元:Springer-Verlag GmbH & Company KG  

    DOI: 10.1007/s003710000081

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  • Cost-effective shadowing method using the ED-buffer on an adaptive light cube

    Tsuyoshi Isshiki, Makoto Ishikawa, Hiroaki Kunieda

    Visual Computer   16 ( 8 )   453 - 468   2000年11月

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    記述言語:英語   出版者・発行元:Springer-Verlag GmbH & Company KG  

    DOI: 10.1007/s003710000081

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  • A new FPGA architecture for high performance bit-serial pipeline datapath

    A Ohta, T Isshiki, H Kunieda

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E83A ( 8 )   1663 - 1672   2000年8月

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    記述言語:英語  

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  • A new FPGA architecture for high performance bit-serial pipeline datapath

    A Ohta, T Isshiki, H Kunieda

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E83A ( 8 )   1663 - 1672   2000年8月

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    記述言語:英語  

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  • New VLSI array processor design for image window operations

    DJ Li, L Jiang, T Isshiki, H Kunieda

    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING   46 ( 5 )   635 - 640   1999年5月

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  • New VLSI array processor design for image window operations

    DJ Li, L Jiang, T Isshiki, H Kunieda

    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING   46 ( 5 )   635 - 640   1999年5月

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  • Scalable VLSI architectures for lattice structure-based discrete wavelet transform

    JT Kim, YH Lee, T Isshiki, H Kunieda

    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING   45 ( 8 )   1031 - 1043   1998年8月

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  • Scalable VLSI architectures for lattice structure-based discrete wavelet transform

    JT Kim, YH Lee, T Isshiki, H Kunieda

    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING   45 ( 8 )   1031 - 1043   1998年8月

     詳細を見る

  • Routability analysis of bit-serial pipeline datapaths

    T Isshiki, WWM Dai, H Kunieda

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E80A ( 10 )   1861 - 1870   1997年10月

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    記述言語:英語  

    Web of Science

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  • Instruction sequence based synthesis for application specific micro-architecture

    KS Jang, T Isshiki, H Kunieda

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E80A ( 6 )   1021 - 1032   1997年6月

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    記述言語:英語  

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  • Routability Analysis of Bit-Serial Pipe Line Datapaths

    T. Isshiki W, W.-M, Dai, H. Kunieda

    IEICE Trans.   E80-A   1861 - 1870   1997年

     詳細を見る

  • A SILICON-ON-SILICON FIELD-PROGRAMMABLE MULTICHIP-MODULE (FPMCM) - INTEGRATING FPGA AND MCM TECHNOLOGIES

    J DARNAUER, T ISSHIKI, P GARAY, J RAMIREZ, MAHESHWARI, V, WWM DAI

    IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY PART B-ADVANCED PACKAGING   18 ( 4 )   601 - 608   1995年11月

     詳細を見る

  • A SILICON-ON-SILICON FIELD-PROGRAMMABLE MULTICHIP-MODULE (FPMCM) - INTEGRATING FPGA AND MCM TECHNOLOGIES

    J DARNAUER, T ISSHIKI, P GARAY, J RAMIREZ, MAHESHWARI, V, WWM DAI

    IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY PART B-ADVANCED PACKAGING   18 ( 4 )   601 - 608   1995年11月

     詳細を見る

  • Parallel Processing Architecture Design for Two-Dimensional Image Processing Using Spatial Expansion of the Signal Flow Description

    T. Isshiki, Y. Takeuchi, H. Kunieda

    IEICE Trans. Fundamentals   E76-A   337 - 348   1993年

     詳細を見る

  • Parallel Processing Architecture Design for Two-Dimensional Image Processing Using Spatial Expansion of the Signal Flow Description

    T. Isshiki, Y. Takeuchi, H. Kunieda

    IEICE Trans. Fundamentals   E76-A   337 - 348   1993年

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  • 2-DIMENSIONAL QUADRILATERAL RECURSIVE DIGITAL-FILTERS WITH PARALLEL STRUCTURE - SYNTHESIS AND PARALLEL PROCESSING

    T ISSHIKI, H KUNIEDA, M KANEKO

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E75A ( 3 )   352 - 361   1992年3月

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    記述言語:英語  

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  • 2-DIMENSIONAL QUADRILATERAL RECURSIVE DIGITAL-FILTERS WITH PARALLEL STRUCTURE - SYNTHESIS AND PARALLEL PROCESSING

    T ISSHIKI, H KUNIEDA, M KANEKO

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E75A ( 3 )   352 - 361   1992年3月

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    記述言語:英語  

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▼全件表示

講演・口頭発表等

  • Embedded Software Development Flow and Verification for a Heterogeneous MPSoC Based on Tightly Coupled Thread Model

    Embedded Systems Symposium 2007  2007年 

     詳細を見る

  • H.264/AVC Decoder SoC Towards the Low Cost Mobile Video Player

    IEEE SOC Conference  2007年 

     詳細を見る

  • H.264/AVC Decoder SoC Towards the Low Cost Mobile Video Player

    IEEE SOC Conference  2007年 

     詳細を見る

  • Tightly-Coupled Threadモデルに基づくマルチプロセッサSoCアーキテクチャ

    情報通信学会北陸支部講演会  2007年 

     詳細を見る

  • MAPS-TCT: MPSoC Application Parallelization and Architecture Exploration Framework

    2008年 

     詳細を見る

  • MAPS-TCT: MPSoC Application Parallelization and Architecture Exploration Framework

    2008年 

     詳細を見る

  • MAPS: An Integrated Framework for MPSoC Application Parallelization

    Proceedings of 45th Design Automation Conference (2008)  2008年 

     詳細を見る

  • Tightly-Coupled-Thread Model: A New Design Framework for Multiprocessor System-on-Chips

    DAシンポジウム  2006年 

     詳細を見る

  • Embedded Software Development Flow and Verification for a Heterogeneous MPSoC Based on Tightly Coupled Thread Model

    Embedded Systems Symposium 2007  2007年 

     詳細を見る

  • Data-driven Multiprocessor SoC Architecture Design Based on Tightly-Coupled-Thread Model

    DAシンポジウム  2006年 

     詳細を見る

  • Fast Search for Fingerprint Matching in Embedded System

    International Conference on Information and Communication Technology for Embedded Systems  2010年 

     詳細を見る

  • Implementation of Low Cost Data Logger Using Flash Disk with File Allocation Table

    International Conference on Information and Communication Technology for Embedded Systems  2010年 

     詳細を見る

  • Fingerprint Reference Point Extraction in Small Size Sensor Images

    International Conference on Information and Communication Technology for Embedded Systems  2010年 

     詳細を見る

  • A Novel Fingerprint Orientation Field Estimation Method

    International Conference on Information and Communication Technology for Embedded Systems  2010年 

     詳細を見る

  • “Prototype of a Real-Time Precision Herbicide Applicator over between-row of Sugarcane Field

    International Conference on Information and Communication Technology for Embedded Systems  2010年 

     詳細を見る

  • High-Speed Video Processing System-On-Chip Architecture Exploration

    International Conference on Information and Communication Technology for Embedded Systems  2010年 

     詳細を見る

  • Cool MPSoC Programming

    Design, Automation & Test in Europe  2010年 

     詳細を見る

  • Architecture of Dynamic Reconfigurable Neural Networks Based ib Network-on-Chip

    International Conference on Information and Communication Technology for Embedded Systems  2010年 

     詳細を見る

  • MAPS: An Integrated Framework for MPSoC Application Parallelization

    Proceedings of 45th Design Automation Conference (2008)  2008年 

     詳細を見る

  • MPSoC Platform for Super Hi-vision Video Processing System

    2010年 

     詳細を見る

  • Efficient Method for FaceRegion Quality Enhancement in Low Bit Rate Video Coding

    IEEE Asia Pasific Conference on Circuit and System  2002年 

     詳細を見る

  • Realization of Fingerprint Identification Module on DSP Board

    IEEE Asia Pasific Conference on Circuit and System  2002年 

     詳細を見る

  • High Density Bit-Serial FPGA with LUT Embedding Shift Register Function

    IEEE Asia Pasific Conference on Circuit and System  2002年 

     詳細を見る

  • A New Methodology for Low Delay Real-time Videophone Software Architecture Design

    IEEE Asia Pasific Conference on Circuit and System  2002年 

     詳細を見る

  • A Novel Fingerprint Orientation Field Estimation Method

    International Conference on Information and Communication Technology for Embedded Systems  2010年 

     詳細を見る

  • Fast Search for Fingerprint Matching in Embedded System

    International Conference on Information and Communication Technology for Embedded Systems  2010年 

     詳細を見る

  • Architecture of Dynamic Reconfigurable Neural Networks Based ib Network-on-Chip

    International Conference on Information and Communication Technology for Embedded Systems  2010年 

     詳細を見る

  • Fingerprint Reference Point Extraction in Small Size Sensor Images

    International Conference on Information and Communication Technology for Embedded Systems  2010年 

     詳細を見る

  • Implementation of Low Cost Data Logger Using Flash Disk with File Allocation Table

    International Conference on Information and Communication Technology for Embedded Systems  2010年 

     詳細を見る

  • Efficient Method for FaceRegion Quality Enhancement in Low Bit Rate Video Coding

    IEEE Asia Pasific Conference on Circuit and System  2002年 

     詳細を見る

  • Multiprocessor System-On-Chip Design Methodology Using Model-Based Tightly-Compled Thread Model

    International Conference on Information and Communication Technology for Embedded Systems  2010年 

     詳細を見る

  • Realization of Fingerprint Identification Module on DSP Board

    IEEE Asia Pasific Conference on Circuit and System  2002年 

     詳細を見る

  • High Density Bit-Serial FPGA with LUT Embedding Shift Register Function

    IEEE Asia Pasific Conference on Circuit and System  2002年 

     詳細を見る

  • A New Methodology for Low Delay Real-time Videophone Software Architecture Design

    IEEE Asia Pasific Conference on Circuit and System  2002年 

     詳細を見る

  • MPSoC Platform for Super Hi-vision Video Processing System

    2010年 

     詳細を見る

  • Cool MPSoC Programming

    Design, Automation & Test in Europe  2010年 

     詳細を見る

  • Performance Improvement of Eddy-current Dynamometers with FEL Controller

    International Conference on Information and Communication Technology for Embedded Systems  2010年 

     詳細を見る

  • Template-Statistical based Fingerprint Classification

    International Symposium on Intelligent Signal Processing and Communication Systems ISPACS  2003年 

     詳細を見る

  • Unique Fingerprint Image Generation Algorithm for One Line Swipe Sensors

    International Conference on Information and Communication Technology for Embedded Systems  2010年 

     詳細を見る

  • Small Memory Minutia Matching Method

    International Symposium on Intelligent Signal Processing and Communication Systems ISPACS  2003年 

     詳細を見る

  • Fingerprint Authentication Programmable SoC Featuring Run-time Reconfigurable Interfaces

    International Symposium on Intelligent Signal Processing and Communication Systems ISPACS  2003年 

     詳細を見る

  • Fingerprint Authentication Programmable SoC Featuring Run-time Reconfigurable Interfaces

    International Symposium on Intelligent Signal Processing and Communication Systems ISPACS  2003年 

     詳細を見る

  • A novel SOC architecture embedded bit serial FPGA

    IEEE Asia-Pacific Conference on Circuits and Systems  2004年 

     詳細を見る

  • Template-Statistical based Fingerprint Classification

    International Symposium on Intelligent Signal Processing and Communication Systems ISPACS  2003年 

     詳細を見る

  • Small Memory Minutia Matching Method

    International Symposium on Intelligent Signal Processing and Communication Systems ISPACS  2003年 

     詳細を見る

  • “Prototype of a Real-Time Precision Herbicide Applicator over between-row of Sugarcane Field

    International Conference on Information and Communication Technology for Embedded Systems  2010年 

     詳細を見る

  • Data-driven Multiprocessor SoC Architecture Design Based on Tightly-Coupled-Thread Model

    DAシンポジウム  2006年 

     詳細を見る

  • High-Speed Video Processing System-On-Chip Architecture Exploration

    International Conference on Information and Communication Technology for Embedded Systems  2010年 

     詳細を見る

  • Tightly-Coupled-Thread Model: A New Design Framework for Multiprocessor System-on-Chips

    DAシンポジウム  2006年 

     詳細を見る

  • A novel SOC architecture embedded bit serial FPGA

    IEEE Asia-Pacific Conference on Circuits and Systems  2004年 

     詳細を見る

  • A Multiprocessor System-on-chip Architecture with Enhanced Compiler Support and Efficient Interconnect

    IP-SOC 2006  2006年 

     詳細を見る

  • Unique Fingerprint Image Generation Algorithm for One Line Swipe Sensors

    International Conference on Information and Communication Technology for Embedded Systems  2010年 

     詳細を見る

  • Multiprocessor System-On-Chip Design Methodology Using Model-Based Tightly-Compled Thread Model

    International Conference on Information and Communication Technology for Embedded Systems  2010年 

     詳細を見る

  • A Multiprocessor System-on-chip Architecture with Enhanced Compiler Support and Efficient Interconnect

    IP-SOC 2006  2006年 

     詳細を見る

  • Performance Improvement of Eddy-current Dynamometers with FEL Controller

    International Conference on Information and Communication Technology for Embedded Systems  2010年 

     詳細を見る

▼全件表示

受賞

  • 第2回 IP LSIデザインアワード開発奨励賞

    2000年   LSI IPデザイン・アワード運営委員会  

     詳細を見る

    受賞国:日本国

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  • 第4回 回路とシステム(軽井沢)ワークショップ 奨励賞

    1991年   電子情報通信学会 回路とシステム研究専門委員会  

     詳細を見る

    受賞区分:国内学会・会議・シンポジウム等の賞  受賞国:日本国

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