ACM

RVCar: An FPGA-Based Simple and Open-Source Mini Motor Car System with a RISC-V Soft Processor.

Takuto Kanamori, Takashi Odan, Kazuki Hirohata, Kenji Kise

IEICE Transactions on Information & Systems   105-D ( 12 )   1999 - 2007   2022.12

An Efficient Resource Shared RISC-V Multicore Architecture.

Md. Ashraful Islam, Kenji Kise

IEICE Transactions on Information & Systems   105-D ( 9 )   1506 - 1515   2022.9

A Low Cost and Portable Mini Motor Car System with a BNN Accelerator on FPGA.

Fumio Hamanaka, Takuto Kanamori, Kenji Kise

14th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip(MCSoC)   84 - 91   2021

RVCoreP-32IC: An optimized RISC- V soft processor supporting the compressed instructions.

Takuto Kanamori, Kenji Kise

14th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip(MCSoC)   38 - 45   2021

A function-rich FPGA system of camera image processing for video meeting.

Takashi Odan, Takuto Kanamori, Kenji Kise

14th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip(MCSoC)   31 - 37   2021

Efficient Resource Shared RISC-V Multicore Processor.

Md. Ashraful Islam, Kenji Kise

14th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip(MCSoC)   366 - 372   2021

RVCoreP: An Optimized RISC-V Soft Processor of Five-Stage Pipelining.

Hiromu Miyazaki, Takuto Kanamori, Md. Ashraful Islam, Kenji Kise

IEICE Transactions on Information & Systems   103-D ( 12 )   2494 - 2503   2020

High-Performance and Hardware-Efficient Odd-Even Based Merge Sorter.

Elsayed A. Elsayed, Kenji Kise

IEICE Transactions on Information & Systems   103-D ( 12 )   2504 - 2517   2020

Dependency-Driven Trace-Based Network-on-Chip Emulation on FPGAs.

Thiem Van Chu, Kenji Kise, Kiyofumi Tanaka

FPGA '20: The 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays(FPGA)   211 - 221   2020

RVCoreP : An optimized RISC-V soft processor of five-stage pipelining.

Hiromu Miyazaki, Takuto Kanamori, Md. Ashraful Islam, Kenji Kise

CoRR   abs/2002.03568   2020

A portable and Linux capable RISC-V computer system in Verilog HDL.

Junya Miura, Hiromu Miyazaki, Kenji Kise

CoRR   abs/2002.03576   2020

RVCoreP-32IM: An effective architecture to implement mul/div instructions for five stage RISC-V soft processors.

Md. Ashraful Islam, Hiromu Miyazaki, Kenji Kise

CoRR   abs/2010.16171   2020

RVCoreP-32IC: A high-performance RISC-V soft processor with an efficient fetch unit supporting the compressed instructions.

Takuto Kanamori, Hiromu Miyazaki, Kenji Kise

CoRR   abs/2011.11246   2020

LEF: An Effective Routing Algorithm for Two-Dimensional Meshes.

Thiem Van Chu, Kenji Kise

IEICE Transactions on Information & Systems   102-D ( 10 )   1925 - 1941   2019

Towards an Efficient Hardware Architecture for Odd-Even Based Merge Sorter.

Elsayed A. Elsayed, Kenji Kise

13th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip(MCSoC)   249 - 256   2019

An Efficient Implementation of a TAGE Branch Predictor for Soft Processors on FPGA.

Katsunoshin Matsui, Md. Ashraful Islam, Kenji Kise

13th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip(MCSoC)   108 - 115   2019

An Efficient Instruction Fetch Architecture for a RISC-V Soft Processor on an FPGA.

Hiromu Miyazaki, Junya Miura, Kenji Kise

Proceedings of the 10th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies(HEART)   14 - 4   2019

ArchHDL: A Novel Hardware RTL Modeling and High-Speed Simulation Environment.

Shimpei Sato, Ryohei Kobayashi 0001, Kenji Kise

IEICE Transactions on Information & Systems   101-D ( 2 )   344 - 353   2018

An Efficient Parallel Hardware Scheme for Solving the N-Queens Problem.

Yuuma Azuma, Hayato Sakagami, Kenji Kise

12th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip(MCSoC)   16 - 22   2018

Swap Based Merge Network for High Performance Sorting Accelerators.

Kenji Kise

Proceedings of the 9th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies(HEART)   8 - 7   2018

Very Massive Hardware Merge Sorter.

Makoto Saitoh, Kenji Kise

International Conference on Field-Programmable Technology(FPT)   86 - 93   2018

An Effective Architecture for Trace-Driven Emulation of Networks-on-Chip on FPGAs.

Thiem Van Chu, Kenji Kise

28th International Conference on Field Programmable Logic and Applications(FPL)   419 - 426   2018

Design and Evaluation of a Configurable Hardware Merge Sorter for Various Output Records.

Elsayed A. Elsayed, Kenji Kise

12th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip(MCSoC)   201 - 208   2018

A High-Performance and Cost-Effective Hardware Merge Sorter without Feedback Datapath.

Makoto Saitoh, Elsayed A. Elsayed, Thiem Van Chu, Susumu Mashimo, Kenji Kise

26th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines(FCCM)   197 - 204   2018

A High Performance FPGA-Based Sorting Accelerator with a Data Compression Mechanism.

Ryohei Kobayashi 0001, Kenji Kise

IEICE Transactions on Information & Systems   100-D ( 5 )   1003 - 1015   2017

High-Performance Hardware Merge Sorter.

Susumu Mashimo, Thiem Van Chu, Kenji Kise

25th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines(FCCM)   1 - 8   2017

Enhanced Long Edge First Routing Algorithm and Evaluation in Large-Scale Networks-on-Chip.

Thiem Van Chu, Myeonggu Kang, Shi Fa, Kenji Kise

11th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip(MCSoC)   83 - 90   2017

Fast and Cycle-Accurate Emulation of Large-Scale Networks-on-Chip Using a Single FPGA.

Thiem Van Chu, Shimpei Sato, Kenji Kise

ACM Transactions on Reconfigurable Technology and Systems   10 ( 4 )   27 - 27   2017

A Cost-Effective and Scalable Merge Sorter Tree on FPGAs Reviewed

Takuma Usui, Thiem Van Chu, Kenji Kise

2016 FOURTH INTERNATIONAL SYMPOSIUM ON COMPUTING AND NETWORKING (CANDAR)   47 - 56   2016

The synchronous vs. asynchronous NoC routers: an apple-to-apple comparison between synchronous and transition signaling asynchronous designs.

Masashi Imai, Thiem Van Chu, Kenji Kise, Tomohiro Yoneda

Tenth IEEE/ACM International Symposium on Networks-on-Chip(NOCS)   1 - 8   2016

An Effective Page Padding Method for RAM Buffer Algorithms to Enhance the SSD Endurance.

Eri Ogawa, Kenji Kise

Fourth International Symposium on Computing and Networking(CANDAR)   133 - 139   2016

A High-speed Verilog HDL Simulation Method using a Lightweight Translator.

Ryohei Kobayashi 0001, Tomohiro Misono, Kenji Kise

SIGARCH Computer Architecture News   44 ( 4 )   26 - 31   2016

Cost-Effective and High-Throughput Merge Network: Architecture for the Fastest FPGA Sorting Accelerator.

Susumu Mashimo, Thiem Van Chu, Kenji Kise

SIGARCH Computer Architecture News   44 ( 4 )   8 - 13   2016

Enabling Fast and Accurate Emulation of Large-scale Network on Chip Architectures on a Single FPGA Reviewed

Thiem Van Chu, Shimpei Sato, Kenji Kise

2015 IEEE 23rd Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)   60 - 63   2015

ArchHDL: A Novel Hardware RTL Design Environment in C++.

Shimpei Sato, Kenji Kise

Applied Reconfigurable Computing - 11th International Symposium(ARC)   53 - 64   2015

Ultrasmall: A Tiny Soft Processor Architecture with Multi-Bit Serial Datapaths for FPGAs.

Shinya Takamaeda-Yamazaki, Hiroshi Nakatsuka, Yuichiro Tanaka, Kenji Kise

IEICE Transactions on Information & Systems   98-D ( 12 )   2150 - 2158   2015

Design and Performance Evaluation of a Manycore Processor for Large FPGA Reviewed

Haruka Mori, Kenji Kise

2014 IEEE 8TH INTERNATIONAL SYMPOSIUM ON EMBEDDED MULTICORE/MANYCORE SOCS (MCSOC)   207 - 214   2014

KNoCEmu: High Speed FPGA Emulator for Kilo-Node Scale NoCs Reviewed

Thiem Van Chu, Shimpei Sato, Kenji Kise

2014 IEEE 8TH INTERNATIONAL SYMPOSIUM ON EMBEDDED MULTICORE/MANYCORE SOCS (MCSOC)   215 - 222   2014

A Framework for Efficient Rapid Prototyping by Virtually Enlarging FPGA Resources Reviewed

Shinya Takamaeda-Yamazaki, Kenji Kise

2014 INTERNATIONAL CONFERENCE ON RECONFIGURABLE COMPUTING AND FPGAS (RECONFIG)   2014

Parallel processing of matrix multiplication in a CPU and GPU heterogeneous environment Reviewed

Satoshi Ohshima, Kenji Kise, Takahiro Katagiri, Toshitsugu Yuba

HIGH PERFORMANCE COMPUTING FOR COMPUTATIONAL SCIENCE - VECPAR 2006   4395   305 - +   2007

Evaluation of the acknowledgment reduction in a software-DSM system Reviewed

Kenji Kise, Takahiro Katagiri, Hiroki Honda, Toshitsugu Yuba

PARALLEL PROCESSING AND APPLIED MATHEMATICS   3911   17 - 25   2006

Effect of auto-tuning with user's knowledge for numerical software

Takahiro Katagiri, Kenji Kise, Hiroki Honda, Toshitsugu Yuba

2004 Computing Frontiers Conference   12 - 25   2004

An efficient algorithm for the euclidean distance transformation Reviewed

Toshihiro Kato, Tomio Hirata, Toyofumi Saito, Kenji Kise

Systems and Computers in Japan   27 ( 7 )   18 - 24   1996.1

The COINS TMD Implementation for the Alpha Architecture and Its Performance Comparison with GCC

TSUKAMOTO Tomohiro, KISE Kenji, KATAGIRI Takahiro, YUBA Toshitsugu, Tomohiro Tsukamoto, Kenji Kise, Takahiro Katagiri, Toshitsugu Yuba, Graduate School of Information Systems The University of Electro-Communications, Graduate School of Information Science and Engineering Tokyo Institute of Technology, Graduate School of Information Systems The University of Electro-Communications, Graduate School of Information Systems The University of Electro-Communications

24 ( 3 )   4 - 14   2007

Cell Speed Challenge 2007 Contest Report : Did you Enjoy the Cell Speed Challenge 2007?

Kenji Kise

Journal of Information Processing Society of Japan   48 ( 11 )   1251 - 1253   2007

The COINS TMD Implementation for the Alpha Architecture and Its Performance Comparison with GCC

Tomohiro Tsukamoto, Kenji Kise, Takahiro Katagiri, Toshitsugu Yuba

24 ( 3 )   4 - 14   2007

Cell プロセッサの分岐ペナルティを軽減するソフトウェア分岐予測の可能性検討 (プロセッサ アーキテクチャ (2),「ハイパフォーマンスコンピューティングとアーキテクチャの評価」に関する北海道ワークショップ (HOKKE-2007))

吉瀬謙二

情報処理学会研究報告. [ハイパラォーマンスコンピューティング]   2007 ( 17 )   245 - 250   2007

ABCLib_DRSSED: A parallel eigensolver with an auto-tuning facility

T Katagiri, K Kise, H Honda, T Yuba

PARALLEL COMPUTING   32 ( 3 )   231 - 250   2006.3

ABCLibScript: a directive to support specification of an auto-tuning facility for numerical software

T Katagiri, K Kise, H Honda, T Yuba

PARALLEL COMPUTING   32 ( 1 )   92 - 112   2006.1

CPUとGPUを用いた並列GEMM演算の提案と実装

大島聡史, 吉瀬謙二, 片桐孝洋, 弓場敏嗣

情報処理学会論文誌コンピューティングシステム   47 ( SIG 12(ACS 15) )   317 - 328   2006

Proposal and Implementation of Parallel GEMM Routine Using CPU and CPU

Satoshi Ohshima, Kenji Kise, Takahiro Katagiri, Toshitsugu Yuba

47 ( SIG 12(ACS 15) )   317 - 328   2006

A time-to-live based reservation algorithm on fully decentralized resource discovery in Grid computing

S Tangpongprasit, T Katagiri, K Kise, H Honda, T Yuba

PARALLEL COMPUTING   31 ( 6 )   529 - 543   2005.6

SimCore/Alpha Functional Simulatorの設計と実装

吉瀬謙二, 片桐孝洋, 本多弘樹, 弓場敏嗣

電子情報通信学会論文誌   J88-D-I ( 2 )   143 - 154   2005

特集 新世代マイクロプロセッサアーキテクチャ タイルプロセッサ

吉瀬謙二

情報処理学会会誌 情報処理   46 ( 10 )   1131 - 1137   2005

S-DSMシステムにおけるページ要求時の受信通知を削減する方式

吉瀬謙二, 田邊浩志, 多忠行, 片桐孝洋, 本多弘樹, 弓場敏嗣

情報処理学会論文誌コンピューティングシステム   46 ( SIG 12 )   170 - 180   2005

Bimode-Plus分岐予測器の提案

吉瀬謙二, 片桐孝洋, 本多弘樹, 弓場敏嗣

情報処理学会論文誌コンピューティングシステム   46 ( SIG 7 )   85 - 102   2005

Special Features New Generation Microprocessor Architecture (1) Tile Processor

Kenji Kise

Journal of Information Processing Society of Japan   46 ( 10 )   1131 - 1137   2005

A Method to Reduce the Acknowledgement Message for a Page Request of S-DSM Systems

Kenji Kise, Hiroshi Tanabe, Tadayuki Ohno, Takahiro Katagiri, Hiroki Honda, Toshitsugu Yuba

46 ( SIG 12 )   170 - 180   2005

The bimode plus plus branch predictor

K Kise, T Katagiri, H Honda, T Yuba

INNOVATIVE ARCHITECTURE FOR FUTURE GENERATION HIGH-PERFORMANCE PROCESSORS AND SYSTEMS   46 ( SIG 7 )   19 - 26   2005

Design and Implementation of the SimCore/Alpha Functional Simulator

Kenji Kise, Takahiro Katagiri, Hiroki Honda, Toshitsugu Yuba

J88-D-I ( 2 )   143 - 154   2005

PCクラスタを用いたN-queens問題の求解

吉瀬謙二, 片桐孝洋, 本多弘樹, 弓場敏嗣

電子情報通信学会論文誌レター   J87-D-I ( 12 )   1145 - 1148   2004

データ再分散を行う並列Gram-Schmidt再直行化

片桐孝洋, 吉瀬謙二, 本多弘樹, 弓場敏嗣

情報処理学会論文誌コンピューティングシステム   45 ( SIG 6(ACS 6) )   75 - 85   2004

Solving the N-queens Problem with a PC Cluster

Kenji Kise, Takahiro Katagiri, Hiroki Honda, Toshitsugu Yuba

J87-D-I ( 12 )   1145 - 1148   2004

A Parallel Gram-Schmidt Re-orthogonalization Method Using Data Re-distribution

Takahiro Katagiri, Kenji Kise, Hiroki Honda, Toshitsugu Yuba

45 ( SIG 6(ACS 6) )   75 - 85   2004

ホームベースソフトウェア分散共有メモリ上でMigratory Accessを効率良く処理する権限委譲プロトコル

城田祐介, 吉瀬謙二, 本多弘樹, 弓場敏嗣

情報処理学会論文誌   44 ( SIG 1(HPC 6) )   103 - 113   2003

Design and Preliminary Implementation of a Particle Simulation Machine for Efficient Short-range Interaction Computations

Ryo Takata, Kenji Kise, Hiroki Honda, Toshitsugu Yuba

IPSJ Transactions on Advanced Computing System   44 ( SIG 6(ACS 1) )   96 - 112   2003

The Ownership Delegation Protocol for Migratory Access in Home-based Software Distributed Shared Memory

Yusuke Shirota, Kenji Kise, Hiroki Honda, Toshitsugu Yuba

44 ( SIG 1(HPC 6) )   103 - 113   2003

Design and Preliminary Implementation of a Particle Simulation Machine for Efficient Short-range Interaction Computations

Ryo Takata, Kenji Kise, Hiroki Honda, Toshitsugu Yuba

IPSJ Transactions on Advanced Computing System   44 ( SIG 6(ACS 1) )   96 - 112   2003

2レベル・ストライド値予測機構の可能性検討

吉瀬謙二, 坂井修一, 田中英彦

情報処理学会論文誌   41 ( 5 )   1340 - 1350   2000

Performance Potential of Two-level Stride Value Predictor

Kenji Kise, Shuichi Sakai, Hidehiko Tanaka

41 ( 5 )   1340 - 1350   2000

An Efficient Algorithm for the Euclidean Distance Transformation

Toshihiro Kato, Tomio Hirata, Toyofumi Saito, Kenji Kise

J78-D-2 ( 12 )   1750 - 1757   1995

ユークリッド距離変換アルゴリズムの効率化

加藤敏洋, 平田富夫, 斉藤豊文, 吉瀬謙二

電子情報通信学会論文誌   J78-D-2 ( 12 )   1750 - 1757   1995

DEM-1: A Particle Simulation Machine for Efficient Short-Range Interaction Computations

International Parallel and Distributed Processing Symposium (IPDPS-2002)  2002 

Processor Architecture to Enhance the Control Flow Code Execution

2002 

FIBER:A Generalized Framework for Auto-tuning Software

Lecture Note in Computer Science (LNCS)  2003 

SimAlpha Version 1.0: Simple and Readable Alpha Processor Simulator

Lecture Note in Computer Science (LNCS)  2003 

Bimode-Plus分岐予測器の提案

電子情報通信学会技術研究報告CPSY2003-10  2003 

FIBER:A Generalized Framework for Auto-tuning Software

Lecture Note in Computer Science (LNCS)  2003 

SimAlpha Version 1.0: Simple and Readable Alpha Processor Simulator

Lecture Note in Computer Science (LNCS)  2003 

Bimode-Plus Branch Predictor

2003 

S-DSMシステムの受信通知オーバヘッドを削減する方式

電子情報通信学会技術研究報告CPSY2004-44  2004 

The SimCore/Alpha Functional Simulator

Workshop on Computer Architecture Education (WCAE-2004)  2004 

DEM-1: A Particle Simulation Machine for Efficient Short-Range Interaction Computations

International Parallel and Distributed Processing Symposium (IPDPS-2002)  2002 

Effect of Auto-tuning with User's Knowledge for Numerical Software

Proceedings of ACM Computing Frontiers 04  2004 

A Super Instruction-Flow Architecture for High Performance and Low Power Processors

Proceedings of the Innovative Architecture on Future Generation High-Performance Processors and Systems(IWIA-2004)  2004 

The SimCore/Alpha Functional Simulator

Workshop on Computer Architecture Education (WCAE-2004)  2004 

Effect of Auto-tuning with User's Knowledge for Numerical Software

Proceedings of ACM Computing Frontiers 04  2004 

A Super Instruction-Flow Architecture

International Symposium on Low-Power and High-Speed Chips (COOL Chips VII)  2004 

A Super Instruction-Flow Architecture for High Performance and Low Power Processors

Proceedings of the Innovative Architecture on Future Generation High-Performance Processors and Systems(IWIA-2004)  2004 

Evaluation of the Acknowledgment Reduction in a Software-DSM System

Lecture Note in Computer Science (LNCS)  2005 

S-DSMシステムにおけるページ要求時の受信通知を削減する方式

先進的計算基盤システムシンポジウムSACSIS2005論文集  2005 

極端な偏りを利用するBimode++分岐予測器の提案

情報処理学会研究報告2005-ARC-161  2005 

A Super Instruction-Flow Architecture

International Symposium on Low-Power and High-Speed Chips (COOL Chips VII)  2004 

SimCore/Alpha Functional Simulatorの設計と評価

情報処理学会研究報告2004-ARC-156  2004 

The Bimode++ Branch Predictor Using the Feature of Extremely Biased Branches

2005 

The Bimode++ Branch Predictor

Proceedings of the Innovative Architecture on Future Generation High-Performance Processors and Systems(IWIA-2005)  2005 

現実的な構成を保ちながら大幅な予測ミスの削減を図るgshare+分岐予測

情報処理学会研究報告2006-EMB-2  2006 

相乗り通信を利用したソフトウェアDSMの通信回数削減手法

情報処理学会研究報告2007-ARC-169  2006 

MPIとの比較によるソフトウェアDSMの性能評価

情報処理学会研究報告2007-ARC-169  2006 

Parallel Processing of Matrix Multiplication in a CPU and GPU Heterogeneous Environment

Lecture Note in Computer Science (LNCS)  2006 

Ainori Communication : A Method to Reduce the Page Transfer of S-DSM Systems

2006 

The Bimode++ Branch Predictor

Proceedings of the Innovative Architecture on Future Generation High-Performance Processors and Systems(IWIA-2005)  2005 

Evaluation of the Acknowledgment Reduction in a Software-DSM System

Lecture Note in Computer Science (LNCS)  2005 

A Method to Reduce the Acknowledgement Message for a Page Request of S-DSM Systems

2005 

多機能メニーコアを実現するアーキテクチャ技術Feature-Packingの構想

情報処理学会研究報告2007-ARC-175  2007 

実用的かつコードのシンプルさを追求したCell BEの機能レベルシミュレータSimCellの設計と実装

コンピュータシステム・シンポジウム(ComSys2007)論文集  2007 

Cell BE機能レベルシミュレータの設計と実装

情報処理学会研究報告2007-ARC-174  2007 

マルチコアプログラミングコンテスト「Cellスピードチャレンジ2007」実施報告

情報処理学会研究報告2007-ARC-174  2007 

分岐履歴のパターンマッチングと命令アドレスを用いた分岐予測精度の検討

情報処理学会第69回全国大会  2007 

ハードウェア分岐予測機構を持たないプロセッサにおけるソフトウェア分岐予測の可能性

情報処理学会第69回全国大会  2007 

A Performance Comparison of Parallel Applications between Software-DSM and MPI

2006 

Parallel Processing of Matrix Multiplication in a CPU and GPU Heterogeneous Environment

Lecture Note in Computer Science (LNCS)  2006 

マルチコア・プロセッサにおけるSimCellを用いたキャッシュコアの可能性の検討

2007 

予測精度の限界を目指すパターンマッチングを用いた分岐予測手法の検討と評価

情報処理学会研究報告2007-ARC-175  2007 

Examination and estimation of the branch predictors using pattern matching pursing excellent prediction accuracy

2007 

Feature-Packing: Architectural-level Techniques for Multifunction Many-core

2007 

The Cell BE Functional Simulator SimCell that is Designed and Implemented Pursuing Practical and Simply Coded Simulator

2007 

Design and Implementation of Cell BE Functional Simulator

2007 

The Report on Multicore Programming Contest Cell Speed Challenge 2007

2007 

多数コアを集積するCMPにおける階層型ネットワークの検討

情報処理学会第69回全国大会  2007 

ソフトウェアDSM MochaとMPIの並列ベンチマークを用いた性能評価

情報処理学会研究報告2007-ARC-172  2007 

通信量の密度に着目したS-DSM開発支援ツールS-CATの機能拡張

情報処理学会研究報告2007-DSM-44  2007 

電力的制約を考慮した低消費電力指向最適化コンパイラ

情報処理学会研究報告2007-ARC-172  2007 

Cellプロセッサの分岐ペナルティを軽減するソフトウェア分岐予測の可能性検討

情報処理学会研究報告2007-ARC-172  2007 

A Performance Comparison of Software-DSM Mocha and MPI Using Parallel Benchmarks

2007 

Extension of S-DSM Development Assistance Tool S-CAT Focusing on Density of Communication Volume

2007 

An Optimization Compiler Considering Energy Limitation for CPU Energy Reduction

2007 

多機能メニーコアにおけるデータ供給を支援するキャッシュコアの提案

情報処理学会研究報告2007-ARC-176  2008 

The proposal of Cache Core which supports data supply on multifunctional many-core processors

2008