Updated on 2026/03/05

写真a

 
NAKAHARA HIROKI
 
Organization
School of Engineering Visiting Professor
Title
Visiting Professor
External link

Research Interests

  • Reconfigurable System

  • FPGA

  • Machine Learning

  • Computer System

  • Embedded System

  • Multiple Valued Logic

  • Deep Learning

Research Areas

  • Informatics / Software

  • Manufacturing Technology (Mechanical Engineering, Electrical and Electronic Engineering, Chemical Engineering) / Communication and network engineering

  • Informatics / Information network

  • Informatics / Theory of informatics

Research History

  • Tohoku University   Unprecedented-scale Data Analytics Center   Professor

    2023.10

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    Country：Japan

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  • Tokyo Institute of Technology   Associate Professor

    2016.4 - 2023.9

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  • Ehime University   Senior Assistant Professor

    2014.10 - 2016.3

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  • Kagoshima University   Assistant Professor

    2012.10 - 2014.9

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  • Kyushu Institute of Technology Faculty of Computer Science and Systems Engineering, Department of Computer Science and Electronics

    2007.9 - 2012.9

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Professional Memberships

Papers

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MISC

  • アンサンブル学習を用いたスパースCNNのFPGA実装に関して—Many Universal Convolution Cores for Ensemble Sparse Convolutional Neural Networks—VLSI設計技術

    倉持 亮佑, 佐田 悠生, 下田 将之, 佐藤 真平, 中原 啓貴

    電子情報通信学会技術研究報告 = IEICE technical report : 信学技報   119 ( 371 )   67 - 72   2020.1

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    Language：Japanese   Publisher：東京 : 電子情報通信学会  

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    Other Link： https://ndlsearch.ndl.go.jp/books/R000000004-I030250032

  • 畳み込みニューラルネットワークを用いた単眼深度推定のFPGA実装について—An FPGA Implementation of Monocular Depth Estimation—VLSI設計技術

    佐田 悠生, 下田 将之, 佐藤 真平, 中原 啓貴

    電子情報通信学会技術研究報告 = IEICE technical report : 信学技報   119 ( 371 )   73 - 78   2020.1

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    Language：Japanese   Publisher：東京 : 電子情報通信学会  

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    Other Link： https://ndlsearch.ndl.go.jp/books/R000000004-I030250044

  • 意味的領域分割のための組み込みシステム向け疎な全畳み込みニューラルネットワークのFPGA実装の検討—Filter-wise Pruning Approach to FPGA Implementation of Fully Convolutional Network for Semantic Segmentation—VLSI設計技術

    下田 将之, 佐田 悠生, 中原 啓貴

    電子情報通信学会技術研究報告 = IEICE technical report : 信学技報   118 ( 430 )   25 - 30   2019.1

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    Language：Japanese   Publisher：東京 : 電子情報通信学会  

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    Other Link： https://ndlsearch.ndl.go.jp/books/R000000004-I029501244

  • 特徴マップを空間分割したCNNのFPGAにおける小メモリ実装—Spatial-Separable Convolution : Low memory CNN for FPGA—VLSI設計技術

    神宮司 明良, 下田 将之, 中原 啓貴

    電子情報通信学会技術研究報告 = IEICE technical report : 信学技報   118 ( 457 )   7 - 12   2019

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    Language：Japanese   Publisher：東京 : 電子情報通信学会  

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    Other Link： https://ndlsearch.ndl.go.jp/books/R000000004-I029575870

  • 全2値化畳み込みニューラルネットワークとそのFPGA実装について : FPT2017デザインコンテスト参加報告—All Binarized Convolutional Neural Network and Its implementation on an FPGA : FPT2017 Design Competition Report

    下田 将之, 佐藤 真平, 中原 啓貴

    電子情報通信学会技術研究報告 = IEICE technical report : 信学技報   117 ( 378 )   7 - 11   2018.1

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    Language：Japanese   Publisher：東京 : 電子情報通信学会  

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    Other Link： https://ndlsearch.ndl.go.jp/books/R000000004-I028823442

  • FPGA向けディープラーニング開発環境GUINNESSについて—GUINNESS : A GUI based Binarized Deep Neural Network Framework for an FPGA

    中原 啓貴, 米川 晴義, 藤井 智也, 下田 将之, 佐藤 真平

    電子情報通信学会技術研究報告 = IEICE technical report : 信学技報   117 ( 221 )   51 - 56   2017.9

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    Language：Japanese   Publisher：東京 : 電子情報通信学会  

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    Other Link： https://ndlsearch.ndl.go.jp/books/R000000004-I028572859

  • 依頼講演 BRein Memory : バイナリ・インメモリ再構成型深層ニューラルネットワークアクセラレータ (集積回路)

    安藤 洸太, 植吉 晃大, 折茂 健太郎, 米川 晴義, 佐藤 真平, 中原 啓貴, 池辺 将之, 浅井 哲也, 高前田 伸也, 黒田 忠広, 本村 真人

    電子情報通信学会技術研究報告 = IEICE technical report : 信学技報   117 ( 167 )   101 - 106   2017.7

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    Language：Japanese   Publisher：電子情報通信学会  

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  • 依頼講演 BRein Memory : バイナリ・インメモリ再構成型深層ニューラルネットワークアクセラレータ (情報センシング)

    安藤 洸太, 植吉 晃大, 折茂 健太郎, 米川 晴義, 佐藤 真平, 中原 啓貴, 池辺 将之, 浅井 哲也, 高前田 伸也, 黒田 忠広, 本村 真人

    映像情報メディア学会技術報告 = ITE technical report   41 ( 25 )   101 - 106   2017.7

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    Language：Japanese   Publisher：映像情報メディア学会  

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  • 畳み込みニューラルネットワークの全2値化に関する一検討—Consideration of All Binarized Convolutional Neural Network

    下田 将之, 藤井 智也, 米川 晴義, 佐藤 真平, 中原 啓貴

    電子情報通信学会技術研究報告 = IEICE technical report : 信学技報   117 ( 153 )   131 - 136   2017.7

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    Language：Japanese   Publisher：東京 : 電子情報通信学会  

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    Other Link： https://ndlsearch.ndl.go.jp/books/R000000004-I028441350

  • A Binarized Deep Neural Network for an Embedded System

    61   8p   2017.5

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  • Accelerated Ternarized Deep Neural Network by sparse matrix calculation

    117 ( 46 )   7 - 11   2017.5

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  • A Memory Reduction with Neuron Pruning for a Convolutional Neural Network : Its FPGA Realization

    116 ( 417 )   55 - 60   2017.1

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  • Implementation of Binarized Deep Neural Network for FPGA Considering Power Performance Enhancement

    116 ( 417 )   127 - 132   2017.1

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  • A Memory Based Realization of the Binarized Deep Convolutional Neural Network

    116 ( 210 )   63 - 68   2016.9

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  • A Realization of Deep Convolutional Neural Network using the Nested RNS on an FPGA including the Constant Division

    115 ( 400 )   227 - 232   2016.1

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  • A Realization of Deep Convolutional Neural Network using the Nested RNS on an FPGA including the Constant Division

    115 ( 398 )   227 - 232   2016.1

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  • An FFT Circuit Using Nested RNS in a Digital Spectrometer for a Radio Telescope

    115 ( 343 )   39 - 44   2015.12

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  • A Design Method Using Discrete Particle Swarm Optimization for a Deep Neural Network Based on Nested RNS

    115 ( 228 )   63 - 68   2015.9

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  • A Deep Convolutional Neural Network Based on Nested Residue Number System

    115 ( 109 )   91 - 96   2015.6

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  • An AWF Digital Spectrometer for a Radio Telescope

    NAKAHARA Hiroki, NAKANISHI Hiroyuki, IWAI Kazumasa

    Technical report of IEICE. VLD   114 ( 426 )   67 - 72   2015.1

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    Language：Japanese   Publisher：The Institute of Electronics, Information and Communication Engineers  

    A radio telescope analyzes radio frequency (RF) received from celestial objects. It consists of an antenna, a receiver, and a spectrometer. The spectrometer converts the time domain into the frequency domain by a FFT operation. In the spectrometer, first, it multiples the window coefficient to the received signal. Second, it applies the FFT operation. Third, it converts to the absolute of a complex number. Finally, to reduce the noise, it accumulates obtained power spectrum. We call this a WFA spectrometer. Since an AD converter is faster than the FPGA, a parallel FFT computation is desired. However, since the amount of hardware for the FFT becomes bottleneck, the conventional WFA does not realized the high-performance analysis. This paper proposes an AWF spectrometer which replaces the order of operations. Since the AWF spectrometer reduces the parallelism of the FFT, it is smaller than the conventional WFA spectrometer. Also, the paper proposes a off-chip memory realization which is highly efficient use of the FPGA. Experimental results show that the proposed AWF spectrometer outperforms conventional spectrometers.

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  • An Update Method for a CAM Emulator using a LUT Cascade Based on an EVBDD

    KUSHIYAMA Kensuke, NAKAHARA Hiroki, SASAO Tsutomu, MATSUURA Munehiro

    IEICE technical report   113 ( 325 )   7 - 12   2013.11

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    Language：Japanese   Publisher：The Institute of Electronics, Information and Communication Engineers  

    The core routers forward packets by IP-lookup using longest prefix matching (LPM). With the rapid growth of the Internet, LPM has become the bottleneck in network traffic management. We have proposed an area-efficiency and high-performance LPM architecture using a LUT cascade based on an edge-valued binary decision diagram (EVBDD). As for the internet, the registered vector is frequency updated. This paper proposes an algorithm for the update of the LUT cascade. Its update time is O(n), where n is the length of the registered vector. We implemented the proposed algorithm on the ARM processor of the Zynq-FPGA. Experimental shows that, as for the normalized area and lookup speed, our architecture outperforms existing FPGA realizations.

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  • A High-Speed FFT for a Solar Radio Burst Observation On a Radio Telescope

    NAKAHARA Hiroki, CHISHIKI Yohei, IWAI Kazumasa, NAKANISHI Hiroyuki

    IEICE technical report   113 ( 325 )   1 - 6   2013.11

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    Language：Japanese   Publisher：The Institute of Electronics, Information and Communication Engineers  

    A radio telescope analyzes radio frequency (RF) received from celestial objects. It consists of an antenna, a receiver, and a spectrometer. The spectrometer converts the time domain into the frequency domain by a FFT operation. A solar radio burst observation requires a high-speed FFT. This paper proposes the high-speed FFT based on Six-Step FFT algorithm. We implement P parallel FFT based on Six-Step FFT algorithm on the Xilinx Virtex 7 VC707 evaluation board. Experimental results shows that the proposed parallel FFT outperforms conventional FFTs.

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  • An Architecture for IPv6 Lookup Using Parallel Index Generation Units

    NAKAHARA Hiroki, SASAO Tsutomu, MATSUURA Munehiro

    IEICE technical report. Computer systems   112 ( 376 )   25 - 30   2013.1

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    Language：Japanese   Publisher：The Institute of Electronics, Information and Communication Engineers  

    This paper shows an area-efficiency and high-performance architecture for the IPv6 lookup using parallel index generation units (IGUs) and a priority encoder. To reduce the size of memory for the IGU, we adopt a liner transform and a row-shift decomposition. Also, this paper shows a design method for parallel IGUs with given prefixes. Experimental shows that, as for the normalized area and lookup speed, our architecture outperforms existing FPGA realizations.

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  • AS-1-3 On a Muti-Valued Processor Based on a Decomposed MTMDDs for CF

    Nakahara Hiroki, Sasao Tsutomu, Matsuura Munehiro

    Proceedings of the Society Conference of IEICE   2012   "S - 5"-"S-6"   2012.8

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    Language：Japanese   Publisher：The Institute of Electronics, Information and Communication Engineers  

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  • On a Wideband Fast Fourier Transform Using A Piecewise Linear Approximation : Applied to a Radio Telescope Spectrometer

    NAKAHARA Hiroki, NAKANISHI Hiro, SASAO Tsutomu

    Technical report of IEICE. VLD   112 ( 114 )   43 - 48   2012.6

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    Language：Japanese   Publisher：The Institute of Electronics, Information and Communication Engineers  

    In a radio telescope, the spectrometer analyzes the radio frequency (RF) received from celestial objects at the frequency domain by performing the fast fourier transform (FFT). The FFT can be realized by the radix 2^k FFT (R2^k FFT). In Radio Astronomy, the number of points for the FFT is larger than that for the general purpose one. Thus, the twiddle factor memory is too large to implement. In this paper, we implement the twiddle factor by the piecewise linear approximation circuit consisting of a small memory, a multiplier, an adder, and a small logic circuit. We analyze the approximation error for the piecewise liner approximation circuits. We implemented the 2^<30> points FFT by the R2^k FFT with the piecewise linear approximation circuit. Compared with other FFT libraries, the R2^k FFT with the piecewise linear approximation using the memory is faster and smaller. Compared with the SETI spectrometer for 2^<27>-FFT in one second, the eight parallelized proposed ones for 2^<27>-FFT is 41.62 times faster, and that for 2^<30>-FFT is 5.20 times faster.

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  • On a Decomposed MTMDDs for CF Machine

    NAKAHARA Hiroki, SASAO Tsutomu, MATSUURA Munehiro

    Technical report of IEICE. VLD   111 ( 397 )   31 - 36   2012.1

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    Language：Japanese   Publisher：The Institute of Electronics, Information and Communication Engineers  

    A decomposed multi-terminal multi-valued decision diagrams for characteristic function (MTMDDs for CF) represents decomposed circuits. A previous work shows that the decomposed MTMDDs for CF is smaller than monolithic decision diagrams for complex functions. This paper shows the decomposed MTMDDs for CF machine. First, we introduce the decomposed MTMDDs for CF. Then, we consider the instruction sets to evaluate the decomposed MTMDDs for CF. Next, we show the architecture for the decomposed MTMDDs for CF machine. We compare the decomposed MTMDDs for CF machine with other MPUs using MCNC benchmark functions. The decomposed MTMDDs for CF machine is 13.12 times faster than Altera's Nios II processor, and is 1.91 times faster than Intel's Atom N455 processor. As for the power-delay product, it is 60.84 times smaller than Nios II processor, and is 18.66 times smaller than Atom N455 processor.

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  • On a Power-Delay Product for a Heterogeneous MDD for ECFN Machine

    NAKAHARA Hiroki, SASAO Tsutomu, MATSUURA Munehiro

    IEICE technical report   111 ( 323 )   1 - 6   2011.11

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    Language：Japanese   Publisher：The Institute of Electronics, Information and Communication Engineers  

    This paper analyzes a power-delay product for a HMDD for an ECFN (Heterogeneous Multi-valued Decision Diagram for Encoded Characteristic Function for Non-zero outputs) Machine that emulates the HMDD for ECFN. First, we introduce the HMDD for ECFN representing the multi-output logic function. Then, we show an architecture for the HMDD for ECFN machine. Next, we obtain the delay time and the power consumption for the HMDD for ECFN machine using the MCNC benchmark function. Finally, we analyze the power-delay product for the HMDD for ECFN machine. Compared with the Intel's Core i5, whose clock frequency is 2.4 GHz, as for the delay time, the HMDD for ECFN machine is 1.40-4.27 times shorter than Core i5, and as for the power-delay product, it is 15.1-46.6 times smaller.

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  • A Regular Expression Matching Circuit Based on a Decomposed Automaton

    2010 ( 5 )   6p   2011.2

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  • On a Prefetching Heterogeneous MDD Machine

    NAKAHARA Hiroki, SASAO Tsutomu, MATSUURA Munehiro

    IEICE technical report   110 ( 319 )   13 - 18   2010.11

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    Language：Japanese   Publisher：The Institute of Electronics, Information and Communication Engineers  

    This paper shows a heterogeneous multi-valued decision diagram machine (HMDDM). First, we introduce a standard heterogeneous multi-valued decision diagram (HMDD). Then, we show a method to prefetch index for the HMDDM. Next, we introduce a code generation method for the HMDDM utilizing given memory size efficiently. We implemented the standard HMDDM and the prefetching HMDDM on an FPGA. The implementation results show that the prefetching HMDDM is 18.2% faster than the standard HMDDM. Also, we compared with Intel's Core2Duo (1.2 GHz) and a quartary decision diagram machine (QDDM). As for the execusion time, the prefetching HMDDM is 9.57-11.85 times faster than the QDDM, and 16.22-20.08 times faster than the Core2Duo.

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  • A Regular Expression Matching Circuit Based on an NFA with Mutli-Character Consuming

    NAKAHARA Hiroki, SASAO Tsutomu, MATSUURA Munehiro

    IEICE technical report   110 ( 204 )   13 - 18   2010.9

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    Language：Japanese   Publisher：The Institute of Electronics, Information and Communication Engineers  

    This paper shows an implementation of a regular expression circuit based on an NFA (Non-deterministic finite automaton). Also, it shows that the NFA based one is superior to the DFA (Deterministic finite automaton) based one, with respect to the area complexity and the time complexity. A regular expression matching circuit is produced as follows: First, the given regular expressions are converted into a non-deterministic finite automaton (NFA). Then, to reduce the number of states, the NFA is converted to a modular non-deterministic finite automaton (MNFA(p)) with p-character-consuming transition. Finally, a finite-input memory machine (FIMM) to detect p-characters is generated, and the matching elements (MEs) realizing the states for the MNFA(p) are generated. We designed MNFA(p) for different p on Xilinx FPGA. As for the performance per area, our method is 6.2-18.6 times better than the DFA-based methods, and is 1.8 times better than the NFA-based method. Then, we derive an optimal value p that efficiently uses both LUTs and embedded memories of the FPGA.

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  • A Quaternary Decision Diagram Machine: Optimization of Its Code

    Tsutomu Sasao, Hiroki Nakahara, Munehiro Matsuura, Yoshifumi Kawamura, Jon T. Butler

    IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS   E93D ( 8 )   2026 - 2035   2010.8

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  • A Parallel Branching Program Machine for Sequential Circuits: Implementation and Evaluation

    Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura, Yoshifumi Kawamura

    IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS   E93D ( 8 )   2048 - 2058   2010.8

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  • A Comparison of Two Approximate String Matching Algorithms Implemented on an FPGA

    SHIMIZU Keisuke, NAKAHARA Hiroki, SASAO Tsutomu, MATSUURA Munehiro

    IEICE technical report   109 ( 462 )   145 - 150   2010.3

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    Language：Japanese   Publisher：The Institute of Electronics, Information and Communication Engineers  

    An approximate string matching finds the most similar pattern in the text. A dynamic programming is used for the approximate string matching. This paper considers two algorithms: Naive method and LL method. Also, it derives area complexities with respect to the pattern length. Our implementations on an Altera's FPGA agree with the derived area complexities.

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  • A Virus Scanning Engine Using a Parallel Sieve Method and the MPU

    NAKAHARA Hiroki, SASAO Tsutomu, MATSUURA Munehiro, KAWAMURA Yoshifumi

    IEICE technical report   109 ( 320 )   25 - 30   2009.11

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    Language：Japanese   Publisher：The Institute of Electronics, Information and Communication Engineers  

    In this paper, we show a new architecture for the virus scanning machine, which is different from that of the intrusion detection machine. The proposed method uses the two-stage matching, which is area-throughput efficient. That is, in the first stage, the hardware filter quickly scans to find possible matches, and in the second stage, the MPU scans the real match by a brute-force method. To make the hardware filter simply, we will introduce finite-input memory machine(FIMM). To reduce the memory size in the FIMM, we will introduce the parallel sieve method. The proposed method uses memory, so the power consumption is lower than the TCAM-based method. The system is implemented on the Stratix III FPGA and three off chip SRAMs, where all ClamAV virus patterns(514287)are stored. Comparison with existing methods, as for the area-throughput ratio, our method is 1.41-31.36 times more efficient.

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  • Emulation of Sequential Circuits by a Parallel Branching Program Machine

    NAKAHARA Hiroki, SASAO Tsutomu, MATSUURA Munehiro, KAWAMURA Yoshifumi

    IEICE technical report   108 ( 478 )   111 - 116   2009.3

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    Language：Japanese   Publisher：The Institute of Electronics, Information and Communication Engineers  

    The parallel branching program machine (PBM128) consists of 128 branching program machines (BMs) and a programmable interconnection. To represent logic functions on BMs, we use quaternary decision diagrams. To evaluate functions, we use 3-address quaternary branch instructions. We realized many benchmark functions on PBM128, and compared its memory size and computation time with the Intel's Core2Duo microprocessor. PBM128 requires approximately quarter of the memory for the Core2Duo, and is 21.4-96.1 times faster than the Core2Duo.

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  • A parallel branching program machine for emulation of sequential circuits

    Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura, Yoshifumi Kawamura

    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)   5453   261 - 267   2009

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  • A Method of Design and Update for An Address Generator Using a Hybrid Method

    NAKAHARA Hiroki, SASAO Tsutomu, MATSUURA Munehiro

    IEICE technical report   107 ( 418 )   73 - 78   2008.1

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    Language：Japanese   Publisher：The Institute of Electronics, Information and Communication Engineers  

    An address table relates k different registered vectors to the indices from 1 to κ. An address generation function represents the address table. This paper presents a realization of an address generation function with a hybrid method using a hash memory and a look-up table(LUT) cascade. The amount of hardware of the hybrid method is shown. Also, an update method for registered vectors is presented. We compared three different realizations: the hybrid method, CAMs produced by the Xilinx Core Generator, and the multiple LUT cascades. Experimental results show that the area for hybrid method is only 8 to 12% of the area for Xilinx CAMs, and is 35% of area for the multiple LUT cascades. Although our update method is complicated, the hybrid method requires smaller area and faster than conventional methods.

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  • A Method of Design and Update for An Address Generator Using a Hybrid Method

    NAKAHARA Hiroki, SASAO Tsutomu, MATSUURA Munehiro

    2008 ( 2 )   73 - 78   2008.1

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    Language：Japanese   Publisher：Information Processing Society of Japan (IPSJ)  

    An address table relates k different registered vectors to the indices from 1 to κ. An address generation function represents the address table. This paper presents a realization of an address generation function with a hybrid method using a hash memory and a look-up table(LUT) cascade. The amount of hardware of the hybrid method is shown. Also, an update method for registered vectors is presented. We compared three different realizations: the hybrid method, CAMs produced by the Xilinx Core Generator, and the multiple LUT cascades. Experimental results show that the area for hybrid method is only 8 to 12% of the area for Xilinx CAMs, and is 35% of area for the multiple LUT cascades. Although our update method is complicated, the hybrid method requires smaller area and faster than conventional methods.

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    Other Link： http://id.nii.ac.jp/1001/00026848/

  • A Method to Evaluate Logic Functions Based On Decison Diagram Using Memory Packing

    TANAKA Hiroyuki, NAKAHARA Hiroki, MATSUURA Munehiro, SASAO Tsutomu

    IEICE technical report   106 ( 552 )   45 - 50   2007.3

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    Language：Japanese   Publisher：The Institute of Electronics, Information and Communication Engineers  

    This paper proposes a method to evaluate logic functios using decision diagrams. Quasi-Reduced Multi-valued Decision Diagrams(QRMDDs) are used for logic simulation. This paper also shows a method to reduce memory requirement and computation time by memory packing. The speedup is due to the reduction of cache miss.

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  • A PC-based logic simulator using a look-up table cascade emulator

    Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E89A ( 12 )   3471 - 3481   2006.12

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  • A Soft-Error Tolerant Look-Up Table Cascade Emulator

    NAKAHARA Hiroki, SASAO Tsutomu

    IEICE technical report   106 ( 198 )   7 - 11   2006.7

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    Language：Japanese   Publisher：The Institute of Electronics, Information and Communication Engineers  

    An LUT cascade emulator realizes an arbitrary sequential circuit. We convert the combinational part into multiple LUT cascades, and store LUT(cell) data into a memory in the LUT cascade emulator. It evaluates multi-output logic functions by reading cell data sequentially. To improve torelance to soft errors, we encode cell data stored in the memory by error correcting codes. Also, we add an error-correcting circuit. A scanning circuit periodically scans the memory. When it detects a soft error, it remove the error by write-backing the correct data into the memory. To avoid the soft error for flip-flops, we employ a TMR (Triple Module Redundancy) technique. Our method detects the soft errors in a single bit. Also, the mission time of our method is more than 1000x of an ordinary LUT cascade emulator.

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  • A memory-based programmable logic device using look-up table cascade with synchronous static random access memories

    Kazuyuki Nakamura, Tsutomu Sasao, Munehiro Matsuura, Katsumasa Tanaka, Kenichi Yoshizumi, Hiroki Nakahara, Yukihiro Iguchi

    JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS   45 ( 4B )   3295 - 3300   2006.4

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  • A Fault Tolerant Look-Up Table Cascade Emulator

    NAKAHARA Hiroki, SASAO Tsutomu

    IEICE technical report   105 ( 647 )   31 - 36   2006.3

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    Language：Japanese   Publisher：The Institute of Electronics, Information and Communication Engineers  

    An LUT cascade emulator realizes an arbitrary sequential circuit. We convert the combinational part into multiple LUT cascades, and store LUT (cell) data into a memory in the LUT cascade emulator. It evaluates multi-output logic functions by reading cell data sequentially. To improve availability of the LUT cascade emulator, we add a self-checking circuit. Cell data stored in the memory are encoded into Berger codes. The self-checking circuit watches for whether memory outputs are Berger codes. The self-checking circuit can detect uni-directional errors of the memory for logic, a single stuck-at fault of a decoder, and a single stuck-at fault of the programmable connection circuit for rails. When a fault is detected, the monitor stops the LUT cascade emulator, and goes to the fault avoidance mode. First, it diagnoses the fault of the LUT cascade emulator. Next, it rewrites memory contents by memory-packing that avoids the failure parts of the memory for logic. Therefore, our method can improve the availability of the circuit.

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  • A design algorithm for sequential circuits using LUT rings

    H Nakahara, T Sasao, M Matsuura

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E88A ( 12 )   3342 - 3350   2005.12

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  • A Logic Simulation using an Look-Up Table Cascade Emulator

    NAKAHARA Hiroki, SASAO Tsutomu, MATSUURA Munehiro

    2005 ( 121 )   185 - 190   2005.11

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    Language：Japanese   Publisher：Information Processing Society of Japan (IPSJ)  

    This paper shows a cycle-based logic simulation method using an LUT cascade emulator. The LUT cascade emulator is an architecture that emulates LUT cascades, where multiple-output LUTs (cells) are connected in series. The LUT cascade emulator has a control part, a large memory, and registers. It connects the memory to each register by a programmable interconnection circuit, and evaluates the given circuit stored in the memory. This method realizes the LUT cascade emulator on a PC by a software. Experimental results show that this method is 18-2621 times faster than the LCC.

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    Other Link： http://id.nii.ac.jp/1001/00027120/

  • A Memory-Based Programmable Logic Device Using a Look-Up Table Cascade with Synchronous SRAMs

    NAKAMURA Kazuyuki, SASAO Tsutomu, MATSUURA Munehiro, TANAKA Katsumasa, YOSHIZUMI Kenichi, NAKAHARA Hiroki, IGUCHI Yukihiro

    2005   314 - 315   2005.9

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    Language：English  

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  • A Design Algorithm for Sequential Circuit Synthesis using LUT Ring

    NAKAHARA Hiroki, SASAO Tsutomu, MATSUURA Munehiro

    IEICE technical report. Dependable computing   103 ( 482 )   145 - 150   2004.12

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    Language：Japanese   Publisher：The Institute of Electronics, Information and Communication Engineers  

    This paper shows a design method for a sequential circuit by using a Look-Up Table(LUT) ring. The method consists of two steps: The first step partitions the outputs into groups. The second step realizes them by LUT cascades, and stores the content of cells in the cascades into the memory. We also compare the method with other methods to realize sequential circuits. With the presented algorithm, we can easily design sequential circuits satisfying given specifications.

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Awards

  • 最優秀エンジニア講演賞

    2018   Design Solution Forum 2018  

    中原 啓貴

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  • Best Demo Award

    2017   IEEE/ACM International Workshop on Reconfigurable Architecture  

    NAKAHARA Hiroki

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  • 最優秀エンジニア講演賞

    2017   Design Solution Forum 2017  

    中原 啓貴

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  • 最優秀論文賞

    2016   多値論理フォーラム  

    中原 啓貴

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  • Young Researcher Award

    2015   IEEE CASS Shikoku Chapter  

    NAKAHARA Hiroki

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  • Kenneth C. Smith Early Career Award

    2014   IEEE International Symposium on ISMVL2013  

    NAKAHARA Hiroki

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  • Best Paper Award

    2013   IEEE 7th International Symposium on MCSoC-13  

    NAKAHARA Hiroki

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  • Funai Best Paper Award

    2012   FIT2012  

    NAKAHARA Hiroki

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  • SASIMI2010 Outstanding Paper Award

    2010  

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  • MEMOCODE2010 Design Contest Winner Award

    2010  

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  • デザインガイア2009最優秀ポスター発表賞

    2009  

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    Country：Japan

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  • Excellent Student Award of the IEEE Fukuoka Section Award

    2006  

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    Country：Japan

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Research Projects

  • Development of a Binary Vision Transformer Hardware

    Grant number：24K02912  2024.4 - 2029.3

    Japan Society for the Promotion of Science  Grants-in-Aid for Scientific Research  Grant-in-Aid for Scientific Research (B)

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    Grant amount：\13000000 （ Direct Cost: \10000000 、 Indirect Cost：\3000000 ）

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  • On a noise convolutional neural network

    Grant number：19H04078  2019.4 - 2024.3

    Japan Society for the Promotion of Science  Grants-in-Aid for Scientific Research  Grant-in-Aid for Scientific Research (B)

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    Grant amount：\17160000 （ Direct Cost: \13200000 、 Indirect Cost：\3960000 ）

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  • Development of Next Generation Spectrometer for Radio Telescope

    Grant number：15H05304  2015.4 - 2019.3

    Japan Society for the Promotion of Science  Grants-in-Aid for Scientific Research  Grant-in-Aid for Young Scientists (A)

    NAKAHARA HIROKI

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    Grant amount：\24700000 （ Direct Cost: \19000000 、 Indirect Cost：\5700000 ）

    We implemented an algorithm in which the operation order of spectrometers has been changed and an FFT circuit based on Residue Number System (RNS) is applied to the existing FPGA board (ROACH2 board), which is an existing facility. We compared it with the existing spectrometer released by CASPER (The Collaboration for Astronomy Signal Processing and Electronics Research). A 50 times wider and 2^16 points resolution spectrometer was realized by our development technologies. The data classifier after observation was realized for a CNN (Convolutional Neural Network). We reduced the size of CNN hardware by binary precision and sparse (Ternary, pruning zero weights) and clarified the practicability of FPGA implementation.

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  • A general purpose processor based on a multi-valued decision diagram

    Grant number：24700050  2012.4 - 2015.3

    Japan Society for the Promotion of Science  Grants-in-Aid for Scientific Research  Grant-in-Aid for Young Scientists (B)

    NAKAHARA Hiroki

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    Grant amount：\4420000 （ Direct Cost: \3400000 、 Indirect Cost：\1020000 ）

    We proposed the Multi-terminal multiple-valued decision diagram for characteristic function representing cluster decomposition (MTMDD for CF) as a new kind of a decision diagram, then presented at the international conferences. Also, we applied the edge-valued MDD(k), which is a variation of the MTMDD for CF, to realize a new embedded processor. We used it to the multi-core processor to realize the packet classification. Also, we developed the commercial packet classifier with co-development company.

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  • FPGAを用いた応用 組込みシステム（主にネットワーク機器）

    2008 - 2012

    JST地域イノベーション創出総合支援事業 

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    Grant type：Competitive

    FPGAを用いた機器の研究開発。特に、ネットワークのセキュリティ・制御機器に関する高性能・低消費電力システムについて。

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