Osaka University   Graduate School of Engineering Division of Electrical, Electronic and Information Engineering   Associate Professor

2009.4 - 2012.3

Tokyo Institute of Technology   Graduate School of Science and Engineering, Department of Communications and Integrated Systems   Associate Professor

2007.4 - 2009.3

Tokyo Institute of Technology   Graduate School of Science and Engineering, Department of Communications and Integrated Systems   Associate Professor

2000.4 - 2007.3

Tokyo Institute of Technology   Faculty of Engineering   Associate Professor

1997.11 - 2000.3

Tokyo Institute of Technology   Faculty of Engineering   Research Associate

1991.4 - 1997.10

電子情報通信学会   基礎・境界ソサイエティ ソサイエティ誌編集委員長  

2017.5 - 2019.4   

電子情報通信学会   基礎・境界ソサイエティ 副会長(システムと信号処理)  

2015.5 - 2016.4   

IEEE   Circuits and Systems Society (CASS) Board of Governors (BoG)  

2015 - 2019   

IEEE   Council on Electronic Design Automation (CEDA) All Japan Joint Chapter Chair  

2014 - 2016   

電子情報通信学会   VLSI設計技術研究会 委員長  

2009.5 - 2010.4   

電子情報通信学会   査読委員、事業担当幹事、VLSI設計技術研究専門委員会 専門委員、和文論文誌Ａ 編集委員、VLSI設計技術研究専門委員会 幹事 、査読委員  

2004 - 2005   

情報処理学会   システムLSI設計技術研究運営委員会 運営委員、設計自動化研究会 連絡委員  

2001 - 2005   

障害物を考慮したグリッドレス配線アルゴリズムの提案

下田将之, 高橋篤司, 栁平康輔, 平井美紀子, 渡邉寿和, 岩澤利光, 児玉親亮

電子情報通信学会技術研究報告 (VLD2025-13)   125 ( 78 )   63 - 68   2025.6

Rigorous Electromagnetic Simulator for Extreme Ultraviolet Lithography and Convolutional Neural Network Reproducing Electromagnetic Simulations Reviewed International journal

Hiroyoshi Tanabe, Masayuki Shimoda, Atsushi Takahashi

Journal of Micro/Nanopatterning, Materials, and Metrology (JM3)   24 ( 02 )   2025.5

A Deep Super-Resolution Mapping Network for Rice Paddy Extraction from Low-Resolution Remote Sensing Images Reviewed International coauthorship International journal

Joanna S. Abraham, Teerasit Kasetkasem, Atsushi Takahashi, Teera Phatrapornnan

Proc. International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology (ECTI-CON)   2025.5

Gap Channel Routing with Fixed Wires Reviewed International journal

Masayuki Shimoda, Atsushi Takahashi, Kosuke Yanagidaira, Mikiko Hirai, Toshikazu Watanabe, Toshimitsu Iwasawa, Chikaaki Kodama

Proc. IEEE International Symposium on Circuits and Systems (ISCAS)   2025.5

Absorber Dependence of M3D Overlay Errors in High-NA and Hyper-NA EUV Lithography Reviewed International journal

Hiroyoshi Tanabe, Atsushi Takahashi

Proc. SPIE, Optical and EUV Nanolithography XXXVIII   13424 ( 0Q )   134240Q-1 - 134240Q-6   2025.4

SDG Channel Routing to Minimize Wirelength for Generalized Channel Reviewed

Zezhong Wang, Masayuki Shimoda, Atsushi Takahashi

IEICE Trans. Fundam. Electron. Commun. Comput. Sci.   108 ( 3 )   500 - 508   2025.3

Gridless Gap Channel Routing with Variable-Width Wires Reviewed

Masayuki Shimoda, Atsushi Takahashi

IEICE Trans. Fundam. Electron. Commun. Comput. Sci.   108 ( 3 )   517 - 524   2025.3

A Fast Three-Layer One-Side Bottleneck Channel Routing with Layout Constraints Using ILP Reviewed

Kazuya Taniguchi, Satoshi Tayu, Atsushi Takahashi, Mathieu Molongo, Makoto Minami, Katsuya Nishioka

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E108-A ( 3 )   509 - 516   2025.3

Fast Droplet Routing Algorithm for MEDA-Based DMFB

Emuun Purevdagva, Masayuki Shimoda, Satoshi Tayu, Atsushi Takahashi

IEICE Technical Report (VLD2024-105)   124 ( 400 )   13 - 18   2025.3

VLSI物理設計におけるギャップチャネル配線問題

下田将之, 高橋篤司, 栁平康輔, 児玉親亮

電子情報通信学会 総合大会 講演論文集   A ( A-6-02 )   35   2025.3

A Note on 4-Layer U-shape Bottleneck Channel Routing

Yo Sakakura, Satoshi Tayu, Masayuki Shimoda, Atsushi Takahashi

IEICE Technical Report (VLD2024-108)   124 ( 400 )   31 - 36   2025.3

Gridless Gap Channel Routing to Minimize Wirelength Reviewed

Masayuki Shimoda, Atsushi Takahashi

IPSJ Transactions on System and LSI Design Methodology (TSLDM)   18   2 - 9   2025.2

プロセスばらつきを考慮した交互最小化を用いたソースマスク最適化

倉持匡希, 小平行秀, 高橋篤司, 児玉親亮

電子情報通信学会技術研究報告 (VLD2024-83)   124 ( 329 )   41 - 46   2025.1

Global Routing for CBA-based 3D Flash Memory

Masayuki Shimoda, Atsushi Takahashi, Kosuke Yanagidaira, Mikiko Hirai, Toshikazu Watanabe, Toshimitsu Iwasawa, Chikaaki Kodama

IEICE Technical Report (VLD2024-82)   124 ( 329 )   35 - 40   2025.1

Mask Pattern Modification Method for OPC to Reduce the Non-uniform Light Intensity

Shotaro Nozaki, Atsushi Takahashi

Proc. DA Symposium 2024, IPSJ Symposium Series   2024   57 - 64   2024.8

Wirelength Minimization by Gap Swap-Flip in Gridless Gap Channel Routing Reviewed International journal

Masayuki Shimoda, Atsushi Takahashi

Proc.21st International SoC Conference (ISOCC)   213 - 214   2024.8

Weakly Guiding Approximation of a Three-dimensional Waveguide Model for Extreme Ultraviolet Lithography Simulation Reviewed International journal

Hiroyoshi Tanabe, Akira Jinguji, Atsushi Takahashi

Journal of the Optical Society of America A   41 ( 8 )   1491 - 1499   2024.7

Two-layer Bottleneck Channel Track Assignment for Analog VLSI Reviewed

Kazuya Taniguchi, Satoshi Tayu, Atsushi Takahashi, Mathieu Molongo, Makoto Minami, Katsuya Nishioka

IPSJ Transactions on System LSI Design Methodology   17   67 - 76   2024.6

A Traffic Monitoring Method Using Accumulative Difference Images Reviewed International coauthorship International journal

Kornchanok Krajangyao, Toshiaki Kondo, Waree Kongprawechnon, Jessada Karnjana, Atsushi Takahashi

Proc. 21st International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology (ECTI-CON)   1 - 6   2024.5

BCA Channel Routing to Minimize Wirelength for Generalized Channel Problem Reviewed International journal

Zezhong Wang, Masayuki Shimoda, Atsushi Takahashi

Proc. IEEE International Symposium on Circuits and Systems (ISCAS)   1 - 5   2024.5

Pre-training CNN for Fast EUV Lithography Simulation including M3D Effects Reviewed International journal

Hiroyoshi Tanabe, Akira Jinguji, Atsushi Takahashi

Proc. SPIE, DTCO and Computational Patterning III   12954 ( 0I )   2024.4

A Fast Three-layer Bottleneck Channel Track Assignment with Layout Constraints using ILP Reviewed International journal

Kazuya Taniguchi, Satoshi Tayu, Atsushi Takahashi, Mathieu Molongo, Makoto Minami, Katsuya Nishioka

Proc. 25th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI)   50 - 55   2024.3

Single Trunk Routing Problem for Generalized Channel

Zezhong Wang, Masayuki Shimoda, Atsushi Takahashi

Technical report of IEICE (VLD2023-104)   123 ( 390 )   37 - 42   2024.2

A Template Routing Method Using SMT Solver for Double Via-Constrained Pair Symmetric Routing Problem

Zuan Jiyo, Satoshi Tayu, Atsushi Takahashi, Mathieu Molongo, Makoto Minami, Katsuya Nishioka

IEICE Technical Report (VLD2023-102)   123 ( 390 )   18 - 23   2024.2

Three-layer Bottleneck Channel Track Assignment for Pins Placed on Opposite Sides

Kazuya Taniguchi, Satoshi Tayu, Atsushi TAKAHASHI, Mathieu Molongo, Makoto Minami, Katsuya Nishioka

IEICE Technical Report (VLD2023-103)   123 ( 390 )   24 - 29   2024.2

Accelerating Extreme Ultraviolet Lithography Simulation with Weakly Guiding Approximation and Source Position Dependent Transmission Cross Coefficient Formula Reviewed International journal

Hiroyoshi Tanabe, Akira Jinguji, Atsushi Takahashi

Journal of Micro/Nanopatterning, Materials, and Metrology (JM3)   23 ( 1 )   2024.1

A Formulation of Mask Optimization into QUBO Model for Ising Machines Reviewed International journal

Yukihide Kohira, Haruki Nakayama, Naoki Nonaka, Tomomi Matsui, Atsushi Takahashi, Chikaaki Kodama

Proc. SPIE, Photomask Technology 2023   12751 ( 1D )   2023.11

Accelerating EUV Lithography Simulation with Weakly Guiding Approximation and STCC Formula Reviewed International journal

Hiroyoshi Tanabe, Akira Jinguji, Atsushi Takahashi

Proc. SPIE, International Conference on Extreme Ultraviolet Lithography 2023   12750 ( 0D )   2023.11

Three-layer Bottleneck Channel Track Assignment by ILP

Kazuya Taniguchi, Satoshi Tayu, Atsushi Takahashi, Mathieu Molongo, Makoto Minami, Katsuya Nishioka

Proc. DA Symposium 2023, IPSJ Symposium Series   2023   199 - 206   2023.8

Droplet routing algorithm for MEDA-based DMFB

Katsuharu Yamamoto, Akira Jinguji, Atsushi Takahashi

Proc. DA Symposium 2023, IPSJ Symposium Series   2023   173 - 179   2023.8

Pair Symmetrical Routing in Common Centroid Placement with Double Via Constraints

Zuan Jo, Satoshi Tayu, Atsushi Takahashi, Mathieu Molongo, Makoto Minami, Katsuya Nishioka

Proc. DA Symposium 2023, IPSJ Symposium Series   2023   207 - 212   2023.8

Detection Welding Performance of Industrial Robot using Machine Learning Reviewed International coauthorship International journal

Onjira Duongthipthewa, Koonlachat Meesublak, Atsushi Takahashi, Chowarit Mitsantisuk

Proc. International Technical Conference on Circuits/Systems, Computers, and Communications (ITC-CSCC)   1 - 6   2023.6

Evaluation of Convolutional Neural Network for Fast Extreme Ultraviolet Lithography Simulation using IMEC 3 nm Node Mask Patterns Reviewed International journal

Hiroyoshi Tanabe, Akira Jinguji, Atsushi Takahashi

Journal of Micro/Nanopatterning, Materials, and Metrology (JM3)   22 ( 02 )   024201   2023.6

Evaluation of CNN for Fast EUV Lithography Simulation using iN3 Logic Mask Patterns Reviewed International journal

Hiroyoshi Tanabe, Akira Jinguji, Atsushi Takahashi

Proc. SPIE, DTCO and Computational Patterning II   12495 ( 1J )   2023.4

A fast SRAF optimization using Voronoi diagram and LUT based intensity evaluation

Sota Saito, Yu Horimoto, Atsushi Takahashi, Yukihide Kohira, Chikaaki Kodama

IEICE Technical Report (VLD2022-80)   122 ( 402 )   43 - 48   2023.3

High fidelity mask pattern generation method by amplitude component evaluation

Yu Horimoto, Sota Saito, Atsushi Takahashi, Yukihide Kohira, Chikaaki Kodama

IEICE Technical Report (VLD2022-79)   122 ( 402 )   37 - 42   2023.3

Pair Symmetrical Routing in Common Centroid Placement with Common Signal Constraints

Zuan Jo, Satoshi Tayu, Atsushi Takahashi, Mathieu Molongo, Makoto Minami, Katsuya Nishioka

IEICE Technical Report (VLD2022-102)   122 ( 402 )   155 - 160   2023.3

Track Assignment considering Routing Crossing Relations to Improve Feasibility in Bottleneck Channel Routing

Kazuya Taniguchi, Satoshi Tayu, Atsushi Takahashi, Mathieu Molongo, Makoto Minami, Katsuya Nishioka

IEICE Technical Report (VLD2022-101)   122 ( 402 )   149 - 154   2023.3

Point Cloud Based Guidance for Autonomous Mobile Robot in Sugarcane Plantation Reviewed International coauthorship International journal

Surachai Rodsai, Anusorn Iamrurksiri, Chowarit Mitsantisuk, Atsushi Takahashi

Proc. Third International Symposium on Instrumentation, Control, Artificial Intelligence, and Robotics (ICA-SYMP)   15 - 18   2023.1

A fast SRAF optimization used LUT based intensity estimation

Sota Saito, Atsushi TAKAHASHI

IEICE Technical Report (VLD2022-40)   122 ( 283 )   121 - 126   2022.11

Mask Optimization Using Voronoi Partition and Iterative Improvement

Naoki Nonaka, Yukihide Kohira, Atsushi Takahashi, Chikaaki Kodama

IEICE Technical Report (VLD2022-41)   122 ( 283 )   127 - 132   2022.11

Data Augmentation in Extreme Ultraviolet Lithography Simulation using Convolutional Neural Network Reviewed International journal

Hiroyoshi Tanabe, Atsushi Takahashi

Journal of Micro/Nanopatterning, Materials, and Metrology (JM3)   21 ( 4 )   2022.10

Bottleneck Channel Routing to Reduce the Area of Analog VLSI Reviewed International journal

Kazuya Taniguchi, Satoshi Tayu, Atsushi Takahashi, Yukichi Todoroki, Makoto Minami

Proc. 24th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI)   26 - 31   2022.10

Pair Symmetrical Routing in Common Centroid Placement

Zuan Jo, Atsushi Takahashi, Yukichi Todoroki, Makoto Minami

Proc. DA Symposium 2022, IPSJ Symposium Series   2022   21 - 26   2022.8

Data Augmentation in EUV Lithography Simulation based on Convolutional Neural Network Reviewed International journal

Hiroyoshi Tanabe, Atsushi Takahashi

Proc. SPIE, DTCO and Computational Patterning   12052 ( 0T )   2022.4

Bottleneck Channel Routing to Reduce the Area of Analog VLSI

Kazuya Taniguchi, Satoshi Tayu, Atsushi Takahashi, Yukichi Todoroki, Makoto Minami

IEICE Technical Report (VLD2021-77)   121 ( 412 )   26 - 31   2022.3

Mask Optimization Method Using Simulated Quantum Annealing

Yukihide Kohira, Haruki Nakayama, Naoki Nonaka, Tomomi Matsui, Atsushi Takahashi, Chikaaki Kodama

IEICE Technical Report (VLD2021-45)   121 ( 277 )   162 - 167   2021.12

Fast EUV Lithography Simulation using Convolutional Neural Network Reviewed International journal

Hiroyoshi Tanabe, Shimpei Sato, Atsushi Takahashi

Journal of Micro/Nanopatterning, Materials, and Metrology (JM3)   20 ( 4 )   1 - 14   2021.9

Acceleration of Mask Optimization Using Gradient Deciding Method and Subgradient Method Reviewed

Naoki Nonaka, Yukihide Kohira, Rina Azuma, Tomomi Matsui, Atsushi Takahashi, Chikaaki Kodama

Proc. the 34th Workshop on Circuits and Systems   213 - 218   2021.8

Design Method of Variable-Latency Circuit with Tunable Approximate Completion-Detection Mechanism Reviewed

UKON Yuta, SATO Shimpei, TAKAHASHI Atsushi

IEICE Transactions on Electronics   E104-C ( 7 )   309 - 318   2021.7

A Fast LUT Based Point Intensity Computation for OPC Algorithm Reviewed International journal

Tahsin Shameem, Shimpei Sato, Atsushi Takahashi, Hiroyoshi Tanabe, Yukihide Kohira, Chikaaki Kodama

Proc. 23rd Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI)   92 - 97   2021.3

Fast 3D Lithography Simulation by Convolutional Neural Network Reviewed International journal

Hiroyoshi Tanabe, Shimpei Sato, Atsushi Takahashi

Proc. SPIE, Design-Process-Technology Co-optimization XV   11614 ( 0M )   1 - 8   2021.2

Fast 3D lithography simulation by convolutional neural network: POC study Reviewed International journal

Hiroyoshi Tanabe, Shimpei Sato, Atsushi Takahashi

Proc. SPIE, Photomask Technology 2020   11518 ( 0L )   2020.9

A Fast Length Matching Routing Pattern Generation Method for Set-Pair Routing Problem Using Selective Pin-Pair Connections Reviewed

Shimpei Sato, Kano Akagi, Atsushi Takahashi

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E103-A ( 9 )   1037 - 1044   2020.9

A Fast Look Up Table Based Lithography Simulator with SOCS Model for OPC Algorithm Reviewed

Tahsin Binte Shameem, Atsushi Takahashi, Hiroyoshi Tanabe, Yukihide Kohira, Chikaaki Kodama

Proc. DA Symposium 2020, IPSJ Symposium Series   2020   142 - 149   2020.9

A Pin-Pair Routing Method for Length Difference Reduction in Set-Pair Routing

Kunihiko Wada, Shimpei Sato, Atsushi Takahashi

IEICE Technical Report (VLD2019-95)   119 ( 443 )   7 - 12   2020.3

Pixel-based Mask Optimization with Lagrangian Relaxation and Boundary Flipping

Rina Azuma, Yukihide Kohira, Tomomi Matsui, Atsushi Takahashi, Chikaaki Kodama

IEICE Technical Report (VLD2019-105)   119 ( 443 )   65 - 70   2020.3

Machine Learning Based Lithography Hotspot Detection Method and Evaluation

Hidekazu Takahashi, Shimpei Sato, Atsushi Takahashi

IEICE Technical Report (VLD2019-106)   119 ( 443 )   71 - 76   2020.3

Process Variation-aware Mask Optimization with Iterative Improvement by Subgradient Method and Boundary Fipping Reviewed International journal

Rina Azuma, Yukihide Kohira, Tomomi Matsui, Atsushi Takahashi, Chikaaki Kodama

Proc. SPIE, Design-Process-Technology Co-optimization for Manufacturability XIV   11328 ( 0O )   1 - 7   2020.3

A Feature Selection Method for Weak Classifier Based Hotspot Detection Reviewed International journal

Hidekazu Takahashi, Hiroki Ogura, Shimpei Sato, Atsushi Takahashi, Chikaaki Kodama

Proc. SPIE, Design-Process-Technology Co-optimization for Manufacturability XIV   11328 ( 1E )   1 - 7   2020.3

A Low Area Overhead Design Method for High-Performance General-Synchronous Circuits with Speculative Execution Reviewed

Shimpei Sato, Eijiro Sassa, Yuta Ukon, Atsushi Takahashi

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E102-A ( 12 )   1760 - 1769   2019.12

Analysis of databases used for hot spot test cases

Hiroki Ogura, Hidekazu Takahashi, Shimpei Sato, Atsushi Takahashi

IEICE Technical Report (VLD2019-52)   119 ( 282 )   191 - 196   2019.11

グラフの位相埋め込みの配置配線パズルへの適用に関する一検討

和田邦彦, 大和田真由, 山本克治, 堀本遊, 佐藤真平, 高橋篤司

情報処理学会研究報告   2019-SLDM-189 ( 31 )   1 - 6   2019.11

Mask Optimization Considering Process Variation by Subgradient Method

Yukihide Kohira, Rina Azuma, Tomomi Matsui, Atsushi Takahashi, Chikaaki Kodama

IEICE Technical Report (VLD2019-53)   119 ( 282 )   197 - 202   2019.11

Hotspot Detection Methods and their Evaluation in Advanced Lithography Invited International journal

Atsushi Takahashi, Hidekazu Takahashi, Hiroki Ogura, Shimpei Sato

Proc. 16th International SoC Design Conference (ISOCC)   121   2019.10

A Fast Hotspot Detector Based on Local Features Using Concentric Circle Area Sampling Reviewed International journal

Hidekazu Takahashi, Shimpei Sato, Atsushi Takahashi

Proc. 22nd Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI)   316 - 321   2019.10

CCASを用いた局所特徴量に基づくリソグラフィホットスポット検出器の検討 Reviewed

高橋秀和, 佐藤真平, 高橋篤司

DAシンポジウム2019論文集，情報処理学会シンポジウムシリーズ   2019 ( 6 )   99 - 104   2019.8

An Intelligent System for Identifying Feasible Routes for Truck Routing Problem: An Application to a Thai Adhesive and Sealant Company (ATASC) Reviewed International coauthorship International journal

Pathawee Phonwiphat, Warut Pannakkong, Pisal Yenradee, Kittipong Ekkachai, Atsushi Takahashi

Proc. 16th International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology (ECTI-CON)   905 - 910   2019.7

A Low Area Overhead Design for High-Performance General-Synchronous Circuits with Speculative Execution Reviewed International journal

Shimpei Sato, Eijiro Sassa, Yuta Ukon, Atsushi Takahashi

Proc. IEEE International Symposium on Circuits and Systems (ISCAS)   1 - 5   2019.5

Indoor Room Identify and Mapping with Virtual based SLAM using Furnitures and Household Objects Relationship based on CNNs Reviewed International coauthorship International journal

Pruttapon Maolanon, Kanjanapan Sukvichai, Nattapon Chayopitak, Atsushi Takahashi

Proc. 10th International Conference of Information and Communication Technology for Embedded Systems (IC-ICTES)   1 - 6   2019.3

Set-Pair Routing Algorithm with Selective Pin-Pair Connections

Kano Akagi, Shimpei Sato, Atsushi Takahashi

IEICE Technical Report (VLD2018-99)   118 ( 457 )   37 - 42   2019.2

On Delay Optimization for Improving General Synchronous Performance

Eijiro Sassa, Shimpei Sato, Atsushi Takahashi

IEICE Technical Report (VLD2018-72)   118 ( 430 )   1 - 6   2019.1

集合対間配線問題ソルバと引きはがし再配線のADC2018問題への適用

大和田真由, 和田邦彦, 赤木佳乃, 佐藤真平, 高橋篤司

情報処理学会研究報告   2018-SLDM-185 ( 13 )   1 - 6   2018.12

集合対間配線手法のADC2018への適用に関する一考察

赤木佳乃, 大和田真由, 和田邦彦, 佐藤真平, 高橋篤司

情報処理学会研究報告   2018-SLDM-185 ( 12 )   1 - 6   2018.12

ADC2018問題の自動生成手法に関する一検討

和田邦彦, 大和田真由, 赤木佳乃, 佐藤真平, 高橋篤司

情報処理学会研究報告   2018-SLDM-185 ( 11 )   1 - 4   2018.12

Process Variation-aware Model-based OPC using 0-1 Quadratic Programming

Rina Azuma, Yukihide Kohira, Tomomi Matsui, Atsushi Takahashi, Chikaaki Kodama, Shigeki Nojima

IEICE Technical Report (VLD2018-70)   118 ( 334 )   209 - 214   2018.12

Survey of 6-University Engineering Assistant Professors

Akinori NISHIHARA, Yuji KAGOHASHI, David STEWART, Atsushi TAKAHASHI, Akira YAMADA

Proceedings of the annual conference of JSET   34   853 - 854   2018.9

Considering low-dimension features based HOG for Human Recognition Reviewed

Hidekazu Takahashi, Shimpei Sato, Atsushi Takahashi

Proc. DA Symposium 2018   2018 ( 6 )   45 - 50   2018.8

Pattern Similarity Metrics for Layout Pattern Classification and Their Validity Analysis by Lithographic Responses Invited International coauthorship International journal

Atsushi Takahashi, Shimpei Sato, Hiroki Ogura, Yu-Min Sung, Ting-Chi Wang

Proc. IEEE Computer Society Annual Symposium on VLSI (ISVLSI)   494 - 497   2018.7

Target Pin-Pair Selection Algorithm Using Minimum Maximum-Edge-Weight Matching for Set-Pair Routing Reviewed International journal

Kano Akagi, Shimpei Sato, Atsushi Takahashi

Proc. 21st Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI)   337 - 342   2018.3

A Study on Target Pin-Pairs Selection for Set-Pair Routing

Kano Akagi, Shimpei Sato, Atsushi Takahashi

IEICE Technical Report (VLD2017-59)   117 ( 273 )   235 - 240   2017.11

Six-University Human Assets Promotion Program for Innovative Education and Research (6U-HAPPIER)

Akinori NISHIHARA, David STEWART, Yuji KAGOHASHI, Atsushi TAKAHASHI, Akira YAMADA

Proceedings of the 33rd Annual Conference of JSET   2017.9

A Routing Method Using Directed Grid-Graph for Self-Aligned Quadruple Patterning Reviewed International journal

Takeshi Ihara, Toshiyuki Hongo, Atsushi Takahashi, Chikaaki Kodama

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E100-A ( 7 )   1473 - 1480   2017.7

An Idea for Maximizing Target Pin-Pair Connections in Set-Pair Routing Reviewed International journal

Kano Akagi, Shimpei Sato, Atsushi Takahashi

Proc. 32nd International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC)   62 - 65   2017.7

Evaluation of Trade-off between Performance and Area in a Variable Latency Arithmetic Circuit

Yuta Ukon, Shimpei Sato, Atsushi Takahashi

IEICE Technical Report (VLD2017-26)   117 ( 97 )   119 - 124   2017.6

Launch of IEEE CEDA All Japan Joint Chapter and Its Role Invited

Atsushi Takahashi

IEICE Technical Report (VLD2017-59)   117 ( 17 )   31 - 34   2017.5

A Set-Pair Routing Algorithm Realizing Target Pin-Pair Connections Reviewed

Kano Akagi, Shimpei Sato, Atsushi Takahashi

Proc. the 30th Workshop on Circuits and Systems   180 - 185   2017.5

A Fast Process-Variation-Aware Mask Optimization Algorithm With a Novel Intensity Modeling Reviewed International journal

Ahmed Awad, Atsushi Takahashi, Satoshi Tanaka, Chikaaki Kodama

IEEE Transactions on Very Large Scale Integration Systems (TVLSI)   25 ( 3 )   998 - 1011   2017.3

Graph is Difficult But Useful

Atsushi Takahashi

Proc. the 2017 IEICE General Conference   A ( AS-1-4 )   S6 - S7   2017.3

High-speed TPL Layout Decomposition Method based on Positive Semidefinite Relaxation using Polygon Clustering

Shohei Handa, Shimpei Sato, Atsushi Takahashi

IEICE Technical Report (VLD2016-111)   116 ( 478 )   55 - 60   2017.3

Efficient Local Pattern Modification Method using FM Algorithm in LELE Double Patterning

Atsushi Ogashira, Shimpei Sato, Atsushi Takahashi

IEICE Technical Report (VLD2016-113)   116 ( 478 )   67 - 72   2017.3

Partial Route Modification Method to Realize Target Equi-length on Single Layer PCB Routing

Shun Sugihara, Shimpei Sato, Atsushi Takahashi

IEICE Technical Report (VLD2016-114)   116 ( 478 )   73 - 78   2017.3

Intensity Difference Map (IDM) Accuracy Analysis for OPC Efficiency Verification and Further Enhancement Reviewed

Ahmed Awad, Atsushi Takahashi, Satoshi Tanaka, Chikaaki Kodama

IPSJ Transactions on System LSI Design Methodology (TSLDM)   10   28 - 38   2017.2

Investigation of the influence of input sequences on the calculation accuracy in an approximate operation using a typical circuit

Shimpei Sato, Yuta Ukon, Atsushi Takahashi

IEICE Technical Report (VLD2016-95)   116 ( 415 )   165 - 170   2017.1

A Fast Mask Manufacturability and Process Variation Aware OPC Algorithm with Exploiting a Novel Intensity Estimation Model Reviewed International journal

Ahmed Awad, Atsushi Takahashi, Chikaaki Kodama

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E99-A ( 12 )   2363 - 2374   2016.12

Manufacturability-aware mask assignment in multiple patterning lithography Reviewed International journal

Yukihide Kohira, Atsushi Takahashi, Tomomi Matsui, Chikaaki Kodama, Shigeki Nojima, Satoshi Tanaka

Proc. IEEE Asia-Pacific Conference on Circuits and Systems (APCCAS)   538 - 541   2016.10

Performance Improvement of General-Synchronous Circuits by Variable Latency Technique using Dynamic Timing-Error Detection Reviewed International journal

Shimpei Sato, Hiroshi Nakatsuka, Atsushi Takahashi

Proc. 20th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI)   60 - 65   2016.10

Flexible Two-Colorable Routing for Self-Aligned Double Patterning Reviewed

Yusuke Kimura, Shimpei Sato, Atsushi Takahashi

Proc. DA Symposium 2016   2016 ( 6 )   26 - 31   2016.9

Six University Human Assets Promotion Program for Innovative Education and Research (6U-HAPPIER)

Akinori NISHIHARA, Yuji KAGOHASHI, Atsushi TAKAHASHI, Akira YAMADA

32nd Annual Conference of JSET   ( 1a-B107-01 )   2016.9

半正定値計画緩和に基づく擬似スティッチを用いたTPLのためのレイアウト分割手法 Reviewed

半田昌平, 高橋篤司, 中田和秀, 松井知己

第29回 回路とシステムワークショップ 論文集   214 - 219   2016.5

A Lithographic Mask Manufacturability and Pattern Fidelity Aware OPC Algorithm Reviewed International journal

Ahmed Awad, Atsushi Takahashi

Proc. International Symposium on VLSI Design, Automation and Test (VLSI-DAT)   1 - 4   2016.4

Grid-based Self-Aligned Quadruple Patterning aware two dimensional routing pattern Reviewed International journal

Takeshi Ihara, Toshiyuki Hongo, Atsushi Takahashi, Chikaaki Kodama

Proc. Design, Automation and Test in Europe (DATE)   241 - 244   2016.3

A Fast Manufacturability Aware Optical Proximity Correction (OPC) Algorithm with Adaptive Wafer Image Estimation Reviewed International journal

Ahmed Awad, Atsushi Takahashi, Chikaaki Kodama

Proc. Design, Automation and Test in Europe (DATE)   49 - 54   2016.3

Yield-aware mask assignment by positive semidefinite relaxation in triple patterning using cut process Reviewed International journal

Yukihide Kohira, Chikaaki Kodama, Tomomi Matsui, Atsushi Takahashi, Shigeki Nojima, Satoshi Tanaka

Journal of Micro/Nanolithography, MEMS, and MOEMS (JM3)   15 ( 2 )   1 - 7   2016.3

Self-Aligned Quadruple Patterning-Aware Three-Color Grid Routing with Different Color Net

Toshiyuki Hongo, Atsushi Takahashi

IEICE Technical Report (VLD2015-135)   115 ( 465 )   137 - 142   2016.3

A correction term for positive semidefinite relaxation of MPL layout decomposition

Shouhei Handa, Atsushi Takahashi, Kazuhide Nakata, Tomomi Matsui

Proc. the 2016 IEICE General Conference   A ( A-6-12 )   86   2016.3

Acceleration of General Synchronous Circuits by Variable Latency Technique using Dynamic Timing-Error Detection

Hiroshi Nakatsuka, Atsushi Takahashi

IEICE Technical Report (VLD2015-140)   115 ( 465 )   167 - 172   2016.3

Passenger Estimation System using Wi-Fi Probe Request Reviewed International coauthorship International journal

Woramate Pattanusorn, Itthisek Nilkhamhang, Somsak Kittipiyakul, Kittipong Ekkachai, Atsushi Takahashi

Proc. 7th International Conference of Information and Communication Technology for Embedded Systems (IC-ICTES)   67 - 72   2016.3

A Length Matching Routing Algorithm for Set-Pair Routing Problem Reviewed International journal

Yuta Nakatani, Atsushi Takahashi

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E98-A ( 12 )   2565 - 2571   2015.12

Effective Routing Pattern Generation with an Optimum Tertiary Routing Algorithm for Self-Aligned Quadruple Patterning

Takeshi Ihara, Atsushi Takahashi

IEICE Technical Report (VLD2015-53)   115 ( 338 )   93 - 98   2015.12

Mask Manufacturability Aware Post OPC Algorithm For Optical Lithography Reviewed

Ahmed Awad, Atsushi Takahashi

Proc. DA Symposium 2015, IPSJ Symposium Series   2015   119 - 124   2015.8

Effective Routing Pattern Generation Method for Self-Aligned Quadruple Patterning Reviewed

Takeshi Ihara, Toshiyuki Hongo, Atsushi Takahashi

Proc. DA Symposium 2015, IPSJ Symposium Series   2015   125 - 130   2015.8

Mask Assignment with Tolerance for Misalignment in LELECUT Triple Patterning

Yukihide Kohira, Chikaaki Kodama, Tomomi Matsui, Atsushi Takahashi, Shigeki Nojima, Satoshi Tanaka

Collection of Abstracts, NGL 2015   35 - 36   2015.7

Effective Two-dimensional Pattern Generation for Self-aligned Double Patterning Reviewed International journal

Takeshi Ihara, Atsushi Takahashi, Chikaaki Kodama

Proc. IEEE International Symposium on Circuits and Systems (ISCAS)   2141 - 2144   2015.5

Self-Aligned Double and Quadruple Patterning Aware Grid Routing Methods Reviewed International journal

Chikaaki Kodama, Hirotaka Ichikawa, Koichi Nakayama, Fumiharu Nakajima, Shigeki Nojima, Toshiya Kotani, Takeshi Ihara, Atsushi Takahashi

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)   34 ( 5 )   753 - 765   2015.5

NP-completeness of Routing Problem with Bend Constraint

Toshiyuki Hongo, Atsushi Takahashi

IEICE Technical Report (VLD2015-3)   115 ( 21 )   13 - 18   2015.5

Yield-aware Mask Assignment using Positive Semidefinite Relaxation in LELECUT Triple Patterning Reviewed International journal

Yukihide Kohira, Chikaaki Kodama, Tomomi Matsui, Atsushi Takahashi, Shigeki Nojima, Satoshi Tanaka

Proc. SPIE, Design-Process-Technology Co-optimization for Manufacturability IX   9427 ( 0B )   1 - 9   2015.3

An Evaluation of the Performance of a Multiplier in Error-detection/correction-framework

Satoshi Ohtsuki, Atsushi Takahashi

IEICE Technical Report (VLD2014-181)   114 ( 476 )   159 - 164   2015.3

A cut-pattern reduction method for routing in Self-Aligned Double Patterning

Noriyuki Takahashi, Takeshi Ihara, Atsushi Takahashi

IEICE Technical Report (VLD2014-154)   114 ( 476 )   7 - 12   2015.3

A Fast Lithographic Mask Correction Algorithm

Ahmed Awad, Atsushi Takahashi

IEICE Technical Report (VLD2014-153)   114 ( 476 )   1 - 6   2015.3

Quadrotor tuning for attitude control based on PID controller using fictitious reference iterative tuning (FRIT) Reviewed International coauthorship International journal

Arthit Julkananusar, Itthisek Nilkhamhang, Rangsarit Vanijjirattikhan, Atsushi Takahashi

Proc. 6th International Conference of Information and Communication Technology for Embedded Systems (IC-ICTES)   1 - 5   2015.3

Rip-up and Reroute based Routing Algorithm for Self-Aligned Double Patterning Reviewed International journal

Takeshi Ihara, Atsushi Takahashi, Chikaaki Kodama

Proc. 19th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI)   83 - 88   2015.3

Zero-weighted Cycle Finding Method for Exchanging Pin Pair on Set-Pair Rouitng

Yuta Nakatani, Atsushi Takahashi

IEICE Technical Report (VLD2014-156)   114 ( 476 )   19 - 24   2015.3

Faster Numberlink solution using possibilities of topological routing

Yuichiro Tanaka, Atsushi Takahashi

IEICE Technical Report (VLD2014-155)   114 ( 476 )   13 - 18   2015.3

Fast Mask Assignment using Positive Semidefinite Relaxation in LELECUT Triple Patterning Lithography Reviewed International journal

Yukihide Kohira, Tomomi Matsui, Yoko Yokoyama, Chikaaki Kodama, Atsushi Takahashi, Shigeki Nojima, Satoshi Tanaka

Proc. 20th Asia and South Pacific Design Automation Conference (ASP-DAC)   665 - 670   2015.1

Positive Semidefinite Relaxation and Approximation Algorithm for Triple Patterning Lithography Reviewed International journal

Tomomi Matsui, Yukihide Kohira, Chikaaki Kodama, Atsushi Takahashi

Proc. Algorithms and Computation - 25th International Symposium (ISAAC)   LNCS 8889   365 - 375   2014.12

2-SAT Based Linear Time Optimum Two-Domain Clock Skew Scheduling in General-Synchronous Framework Reviewed International journal

Yukihide Kohira, Atsushi Takahashi

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E97-A ( 12 )   2459 - 2466   2014.12

A Novel High-Performance Heuristic Algorithm with Application to Physical Design Optimization Reviewed International journal

Yiqiang Sheng, Atsushi Takahashi

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E97-A ( 12 )   2418 - 2426   2014.12

A Method for Total Length and Length Difference Reduction for Set-pair Routing

NAKATANI Yuta, TAKAHASHI Atsushi

Technical report of IEICE (VLD2014-87)   114 ( 328 )   111 - 116   2014.11

A Fast Process Variation and Pattern Fidelity Aware Mask Optimization Algorithm Reviewed International journal

Ahmed Awad, Atsushi Takahashi, Satoshi Tanaka, Chikaaki Kodama

Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD)   238 - 245   2014.11

[Invited] Multi Patterning Techniques for Manufacturability Enhancement in Optical Lithography Invited International journal

Atsushi Takahashi, Ahmed Awad, Yukihide Kohira, Tomomi Matsui, Chikaaki Kodama, Shigeki Nojima, Satoshi Tanaka

Proc. the 2014 International Conference on Integrated Circuits, Design, and Verification (ICDV)   117 - 122   2014.11

A Process Variability Band Area Reduction Algorithm For Optical Lithography Reviewed

Ahmed Awad, Atsushi Takahashi, Satoshi Tanaka, Chikaaki Kodama

Proc. 2014 IEICE Society Conference (A-3-6)   A   50   2014.9

A New Intensity Based Edge Placement Error Optimization Algorithm for Optical Lithography Reviewed

Ahmed Awad, Atsushi Takahashi, Satoshi Tanaka, Chikaaki Kodama

Proc. the 27th Workshop on Circuits and Systems   422 - 427   2014.8

Mask Optimization With Minimal Number of Convolutions Using Intensity Difference Map Reviewed

Ahmed Awad, Atsushi Takahashi, Satoshi Tanaka, Chikaaki Kodama

Proc. DA Symposium 2014, IPSJ Symposium Series   2014   145 - 150   2014.8

Numberlink solver based on CHORD-LAST method with area decomposition Reviewed

Yuichiro Tanaka, Atsushi Takahashi

Proc. DA Symposium 2014, IPSJ Symposium Series   2014   221 - 226   2014.8

Fast Mask Assignment Method Considering Yield for LELE Double Patterning

Yukihide Kohira, Yoko Yokoyama, Chikaaki Kodama, Atsushi Takahashi, Shigeki Nojima, Satoshi Tanaka

Collection of Abstracts, NGL   41 - 42   2014.7

LELECUT Triple Patterning Lithography Layout Decomposition using Positive Semidefinite Relaxation

KOHIRA Yukihide, MATSUI Tomomi, YOKOYAMA Yoko, KODAMA Chikaaki, TAKAHASHI Atsushi, NOJIMA Shigeki, TANAKA Satoshi

Technical report of IEICE (VLD2014-6)   114 ( 59 )   27 - 32   2014.5

Local Pattern Modification Method for Lithographical ECO in Double Patterning

MIYABE Yutaro, TAKAHASHI Atsushi, MATSUI Tomomi, KOHIRA Yukihide, YOKOYAMA Yoko

Technical report of IEICE (VLD2013-149)   113 ( 454 )   87 - 92   2014.3

An Enhancement of Length Difference Reduction Algorithm for Set Pair Routing

Yusaku Yamamoto, Atsushi Takahashi

IEICE Technical Report (VLD2013-142)   113 ( 454 )   49 - 54   2014.3

Self-Aligned Double Patterning-Aware Modified Two-color Grid Routing

Takeshi Ihara, Atsushi Takahashi, Chikaaki Kodama

IEICE Technical Report (VLD2013-150)   113 ( 454 )   93 - 98   2014.3

Yield-aware decomposition for LELE double patterning Reviewed International journal

Yukihide Kohira, Yoko Yokoyama, Chikaaki Kodama, Atsushi Takahashi, Shigeki Nojima, Satoshi Tanaka

Proc. SPIE, Design-Process-Technology Co-optimization for Manufacturability VIII   9053 ( 0T )   1 - 10   2014.3

Localization concept of re-decomposition area to fix hotspots for LELE process Reviewed International journal

Yoko Yokoyama, Keishi Sakanushi, Yukihide Kohira, Atsushi Takahashi, Chikaaki Kodama, Satoshi Tanaka, Shigeki Nojima

Proc. SPIE, Design-Process-Technology Co-optimization for Manufacturability VIII   9053 ( 0V )   1 - 8   2014.2

2-SAT based linear time optimum two-domain clock skew scheduling Reviewed International journal

Yukihide Kohira, Atsushi Takahashi

Proc. 19th Asia and South Pacific Design Automation Conference (ASP-DAC)   173 - 178   2014.1

A New Variation of Adaptive Simulated Annealing for 2D/3D Packing Optimization Reviewed

Yiqiang Sheng, Atsushi Takahashi

IPSJ Transactions on System LSI Design Methodology (TSLDM)   6   94 - 100   2013.8

The Evaluation of Performance of Multiplier with Variable-Latency Technology on FPGA Reviewed

Satosi Otsuki, Atsushi Takahashi

Proc. DA Symposium 2013, IPSJ Symposium Series   2013 ( 3 )   157 - 162   2013.8

Overlap Area Maximization in Stitch Selection for LELE Double Patterning Reviewed

Yukihide Kohira, Yoko Takekawa, Chikaaki Kodama, Atsushi Takahashi, Shigeki Nojima, Satoshi Tanaka

Proc. the 26th Workshop on Circuits and Systems   466 - 471   2013.7

Dawn of Computer-aided Design - from Graph-theory to Place and Route - Invited International journal

Atsushi Takahashi

Proc. International Symposium on Physical Design (ISPD)   58   2013.3

Fast Performance Estimation Method for Variable Latency Circuits with Error Detection/Correction Mechanism

Kenta Ando, Atsushi Takahashi

IPSJ SIG Technical Reports   2013-SLDM-160 ( 16 )   1 - 6   2013.3

A Routing Method Considering Wirelength of Each Net for Single Layer PCB Routing

Kyosuke Shinoda, Atsushi Takahashi

IEICE Technical Report (VLD2012-149)   112 ( 451 )   77 - 82   2013.3

A Study of Effects of Length Control in Trunk Routing Problem Reviewed

Kyosuke Shinoda, Atsushi Takahashi

Proc. the 2013 IEICE General Conference   A ( A-3-6 )   66   2013.3

Self-Aligned Double and Quadruple Patterning-aware grid routing with hotspots control Reviewed International journal

Chikaaki Kodama, Hirotaka Ichikawa, Koichi Nakayama, Toshiya Kotani, Shigeki Nojima, Shoji Mimotogi, Shinji Miyamoto, Atsushi Takahashi

Proc. 18th Asia and South Pacific Design Automation Conference (ASP-DAC)   267 - 272   2013.1

A Simulated Annealing Based Approach to Integrated Circuit Layout Design

Yiqiang Sheng, Atsushi Takahashi

Simulated Annealing - Single and Multiple Objective Problems   2012.10

Fast Estimation of Dynamic Delay Distribution

Dai Akita, Kenta Ando, Atsushi Takahashi

IEICE Technical Report (VLD2012-55)   112 ( 245 )   83 - 88   2012.10

An Optimum 2-Clustering Method in General-Synchronous Framework Reviewed

Yukihide Kohira, Atsushi Takahashi

Proc. the 25th Workshop on Circuits and Systems   178 - 183   2012.7

Delay-variation Aware Adaptive Circuits - High-performance Circuits under Delay Variation Environments -

Atsushi Takahashi

Proc. the 25th Workshop on Circuits and Systems   184 - 189   2012.7

An Equi-Length Routing Method Considering Wirelength of Each Net for Single Layer PCB Routing Reviewed

Shinoda Kyosuke, Kohira Yukihide, Takahashi Atsushi

Proceedings of the IEICE General Conference   A ( A-3-3 )   87   2012.3

2-Stage Simulated Annealing with Crossover Operator for 3D-Packing Volume Minimization Reviewed International journal

Yiqiang Sheng, Atsushi Takahashi, Shuichi Ueno

Proc. 17th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI)   227 - 232   2012.3

Performance Evaluation of Various Configuration of Adder in Variable Latency Circuits with Error Detection/Correction Mechanism Reviewed International journal

Kenta Ando, Atsushi Takahashi

Proc. 17th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI)   549 - 554   2012.3

Performance of the Evaluation of a Variable-Latency-Circuit on FPGA

Yuta Ukon, Kenta Ando, Atsushi Takahashi

IEICE Technical Report (VLD2011-141)   111 ( 450 )   127 - 132   2012.3

An Any-Angle Routing Method using Quasi-Newton Method Reviewed

Yukihide Kohira, Atsushi Takahashi

Proc. 17th Asia and South Pacific Design Automation Conference (ASP-DAC)   145 - 150   2012.1

Single-Layer Trunk Routing Using Minimal 45-Degree Lines Reviewed International journal

Kyosuke Shinoda, Yukihide Kohira, Atsushi Takahashi

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E94-A ( 12 )   2510 - 2518   2011.12

An Improved Simulated Annealing for 3D Packing with Sequence Triple and Quintuple Representations

Yiqiang Sheng, Atsushi Takahashi, Shuichi Ueno

IEICE Technical Report (VLD2011-88)   111 ( 324 )   209 - 214   2011.11

A length difference reduction algorithm by using flow in set pair routing problem for single layer PCB routing

Yusaku Yamamoto, Atsushi Takahashi

IEICE Technical Report (VLD2011-87)   111 ( 324 )   203 - 208   2011.11

RRA-based multi-objective optimization to mitigate the worst cases of placement Reviewed International journal

Yiqiang Sheng, Atsushi Takahashi, Shuichi Ueno

Proc. IEEE 9th International Conference on ASIC (ASICON)   329 - 332   2011.10

An Iterative Improvement Method for Any-Angle Routing using Quasi-Newton Method Reviewed

Kohira Yukihide, Takahashi Atsushi

Proceedings of the Society Conference of IEICE   A ( A-3-20 )   94   2011.9

MSA: Mixed Stochastic Algorithm for Placement with Larger Solution Space

Yiqiang Sheng, Atsushi Takahashi, Shuichi Ueno

IEICE Technical Report (VLD2011-42)   111 ( 216 )   11 - 16   2011.9

On set pair routing problem

Atsushi Takahashi

IEICE Technical Report (VLD2011-44)   111 ( 216 )   23 - 28   2011.9

An Any-Angle Routing Method using Quasi-Newton Method Reviewed

Yukihide Kohira, Atsushi Takahashi

Proc. the 24th Workshop on Circuits and Systems   425 - 430   2011.8

A Stochastic Optimization Method to Solve General Placement Problem Effectively Reviewed

Yiqiang Sheng, Atsushi Takahashi, Shuichi Ueno

Proc. DA Symposium 2011, IPSJ Symposium Series   2011 ( 5 )   27 - 32   2011.8

Performance Evaluation of Various Configurations of Adder in Error Detection/Correction Circuits

Kenta Ando, Atsushi Takahashi

IEICE Technical Report (VLD2011-33)   111 ( 103 )   147 - 152   2011.7

Relay-Race Algorithm: A Novel Heuristic Approach to VLSI/PCB Placement Reviewed International journal

Yiqiang Sheng, Atsushi Takahashi, Shuichi Ueno

Proc. IEEE Computer Society Annual Symposium on VLSI (ISVLSI)   96 - 101   2011.4

CRP : Efficient Topology Modification for Minimum Perturbation Placement Realization

Yuki Kouno, Yasuhiro Takashima, Atsushi Takahashi

IEICE Technical Report (VLD2010-138)   110 ( 432 )   129 - 134   2011.3

Behavior Verification of a Variable Latency Circuit on FPGA

Yuuta Ukon, Masafumi Inoue, Atsushi Takahashi, Kenji Taniguchi

IEICE Technical Report (VLD2010-142)   110 ( 432 )   153 - 158   2011.3

An evaluation of error detection/correction circuits by gate level simulation

Masafumi Inoue, Yuuta Ukon, Atsushi Takahashi

IEICE Technical Report (VLD2010-141)   110 ( 432 )   147 - 152   2011.3

CAFE Router: A Fast Connectivity Aware Multiple Nets Routing Algorithm for Routing Grid with Obstacles Reviewed International journal

Yukihide Kohira, Atsushi Takahashi

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E93-A ( 12 )   2380 - 2388   2010.12

[Invited Talk] An overview of VLSI design automation and its future prospective Invited

Atsushi Takahashi

The Japan Society of Applied Physics, Silicon Technology Division   ( 128 )   42 - 43   2010.11

Single-Layer Trunk Routing Using 45-Degree Lines within Critical Areas for PCB Routing Reviewed International journal

Kyosuke Shinoda, Yukihide Kohira, Atsushi Takahashi

Proc. 16th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI)   278 - 283   2010.10

Length-Matching Routing on Single Layer for PCB Routing Design Invited

KOHIRA Yukihide, TAKAHASHI Atsushi

IEICE technical report (VLD2010-47)   110 ( 210 )   31 - 36   2010.9

An Evaluation of Clock Tree Based on Clustering in General-Synchronous Framework Reviewed

Kohira Yukihide, Takahashi Atsushi

Proceedings of the Society Conference of IEICE   A ( A-3-1 )   63   2010.9

Evaluation of Circuit Architecture and Performance of Error-Detection-Correction Mechanism Reviewed

Masafumi Inoue, Yuuta Ukon, Atsushi Takahashi, Kenji Taniguchi

Proc. DA Symposium 2010, IPSJ Symposium Series   2010 ( 7 )   123 - 128   2010.9

Fast Optimization on Minimum Perturbation Placement Realization

Yuki Kouno, Yasuhiro Takashima, Atsushi Takahashi

IEICE Technical Report (VLD2010-51)   110 ( 210 )   55 - 60   2010.9

A Congested Area Specification for Single Layer Printed Circuit Board Routing Reviewed

Kyosuke Shinoda, Yukihide Kohira, Atsushi Takahashi

Proc. the 2010 IEICE Society Conference   A ( A-3-4 )   66   2010.9

An Efficient Congested Area Specification And Congestion Relaxation by 45 Degree Line for Single Layer Printed Circuit Board Rouitng

Kyosuke Shinoda, Yukihide Kohira, Atsushi Takahashi

IEICE Technical Report (VLD2010-9)   110 ( 36 )   79 - 84   2010.5

Clustering Method for Low Power Clock Tree in General Synchronous Framework

KOHIRA Yukihide, TAKAHASHI Atsushi

IEICE technical report (VLD2009-119)   109 ( 462 )   121 - 126   2010.3

Evaluation of a Detail Via Arrangement Method for 2-Layer Ball Grid Array Packages

Masaki Kinoshita, Yoichi Tomioka, Atsushi Takahashi

IEICE Technical Report (VLD2009-117)   109 ( 462 )   109 - 114   2010.3

Fast Estimation Method of Peak Power considered Input Vector and Inner State of a Circuit

Nobuyoshi Takahashi, Yoichi Tomioka, Yukihide Kohira, Atsushi Takahashi

IEICE Technical Report (VLD2009-115)   109 ( 462 )   97 - 102   2010.3

Performance evaluation of ADDER with Error-Detection-Correction Mechanism

Yuuta Ukon, Masafumi Inoue, Atsushi Takahashi, Kenji Taniguchi

IEICE Technical Report (VLD2009-121)   109 ( 462 )   133 - 138   2010.3

CAFE router: A Fast Connectivity Aware Multiple Nets Routing Algorithm for Routing Grid with Obstacles Reviewed International journal

Yukihide Kohira, Atsushi Takahashi

Proc. 15th Asia South Pacific Design Automation Conference (ASP-DAC)   281 - 286   2010.1

A Fast Longer Path Algorithm for Routing Grid with Obstacles Using Biconnectivity Based Length Upper Bound Reviewed International journal

Yukihide Kohira, Suguru Suehiro, Atsushi Takahashi

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E92-A ( 12 )   2971 - 2978   2009.12

MILP-Based Efficient Routing Method with Restricted Route Structure for 2-Layer Ball Grid Array Packages Reviewed International journal

Yoichi Tomioka, Yoshiaki Kurata, Yukihide Kohira, Atsushi Takahashi

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E92-A ( 12 )   2998 - 3006   2009.12

[Poster Presentation] An evaluation of delay error rate of an adder in terms of clock period

Yuuta Ukon, Atsushi Takahashi, Kenji Taniguchi

IEICE Technical Report (ICD2009-91)   109 ( 336 )   77 - 81   2009.12

New Design Methodologies for Synchronous Circuits Invited International journal

Atsushi Takahashi

Special Papers of IEEJ the 2009 International Analog VLSI Workshop   I2-1 - I2-4   2009.11

A Detail Via Arrangement Method for Reduction of Wire Congestion in 2-Layer Ball Grid Array Packages

KINOSHITA Masaki, TOMIOKA Yoichi, TAKAHASHI Atsushi

IEICE technical report (VLD2009-30)   109 ( 201 )   7 - 12   2009.9

A River Routing Method for Single Layer with Obstacles by Area Partition Reviewed

Yukihide Kohira, Atsushi Takahashi

Proc. the 2009 IEICE Society Conference   A ( A-3-9 )   58   2009.9

Top Layer Plating Lead Maximization for BGA Packages Reviewed

Yoichi Tomioka, Atsushi Takahashi

Proc. the 2009 IEICE Society Conference   A ( A-3-10 )   59   2009.9

A Wall Generation for Trunk Routing of Multiple Nets on Single Layer

KOHIRA Yukihide, TAKAHASHI Atsushi

IEICE technical report (VLD2009-31)   109 ( 201 )   13 - 18   2009.9

Fast Estimation of Peak Power by Appropriate Input Vector Selection Reviewed

Nobuyoshi Takahashi, Yoichi Tomioka, Yukihide Kohira, Atsushi Takahashi

Proc. DA Symposium 2009, IPSJ Symposium Series   2009 ( 7 )   13 - 18   2009.8

Octilinear Routing Method with Congestion Relaxation by Slant Lines

Kyosuke Shinoda, Yukihide Kohira, Atsushi Takahashi

IEICE Technical Report (VLD2009-23,CAS2009-18,SIP2009-35)   109 ( 111 )   97 - 102   2009.7

Routability Driven Via Assignment Method for 2-Layer Ball Grid Array Packages Reviewed International journal

Yoichi Tomioka, Atsushi Takahashi

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E92-A ( 6 )   1433 - 1441   2009.6

A RST Construction Method for Vertices with Maximum Path Length

Masafumi Inoue, Yoichi Tomioka, Yukihide Kohira, Atsushi Takahashi

IEICE Technical Report (VLD2009-4)   109 ( 34 )   31 - 36   2009.5

Minimization of Delay Insertion in Clock Period Improvement in General-Synchronous Framework Reviewed International journal

Yukihide Kohira, Shuhei Tani, Atsushi Takahashi

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E92-A ( 4 )   1106 - 1114   2009.4

A Maximization Method of Parallel Wire Lengths in Routing Area with Obstacles

SUEHIRO Suguru, KOHIRA Yukihide, TAKAHASHI Atsushi

IEICE technical report (VLD2008-137)   108 ( 478 )   59 - 64   2009.3

A Lower Cost Clock Tree Synthesis Method in General-Synchronous Framework using an EDA tool

Hiroyoshi Hashimoto, Yukihide Kohira, Atsushi Takahashi

IEICE Technical Report (VLD2008-134)   108 ( 487 )   47 - 52   2009.3

A Delay Insertion Method for Clock Period Reduction with Fewer Delay Insertion in General-Synchronous Circuits

Shuhei Tani, Yukihide Kohira, Atsushi Takahashi

IEICE Technical Report (VLD2008-135)   108 ( 487 )   53 - 58   2009.3

A Fast Approximation Method of Maximum Operation in Statistical Static Timing Analysis for Achieving Specified Yield Reviewed International journal

Shun Gokita, Yukihide Kohira, Atsushi Takahashi

Proc. 15th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI)   364 - 369   2009.3

Fast Optimization on Minimum Perturbation Placement Realization

Yuki Kouno, Yasuhiro Takashima, Atsushi Takahashi

IEICE Technical Report (VLD2008-138)   108 ( 487 )   65 - 70   2009.3

A Routing Method based on Nearest Via Assignment for 2-Layer Ball Grid Array Packages Reviewed

Yoshiaki Kurata, Yoichi Tomioka, Yukihide Kohira, Atsushi Takahashi

Proc. 15th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI)   307 - 312   2009.3

A Fast Longer Path Algorithm for Routing Grid with Obstacles using Biconnectivity based Length Upper Bound Reviewed International journal

Yukihide Kohira, Suguru Suehiro, Atsushi Takahashi

Proc. 14th Asia South Pacific Design Automation Conference (ASP-DAC)   600 - 605   2009.1

A Fast Clock Scheduling for Peak Power Reduction in LSI Reviewed International journal

Yosuke Takahashi, Yukihide Kohira, Atsushi Takahashi

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E91-A ( 12 )   3803 - 3811   2008.12

Minimization of Delay Insertion in Clock Period Improvement in General-Synchronous Framework Reviewed International journal

Yukihide Kohira, Shuhei Tani, Atsushi Takahashi

Proc. IEEE Asia-Pacific Conference on Circuits and Systems (APCCAS)   1680 - 1683   2008.12

A Semi-Monotonic Routing Method for Fanin Type Ball Grid Array Packages Reviewed International journal

Yoichi Tomioka, Atsushi Takahashi

Proc. IEEE Asia-Pacific Conference on Circuits and Systems (APCCAS)   1550 - 1553   2008.12

Optimal Time-Multiplexing in Inter-FPGA Connections for Accelerating Multi-FPGA Prototyping Systems Reviewed International journal

Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura, Atsushi Takahashi

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E91-A ( 12 )   3539 - 3547   2008.12

CAFE router : A Fast Connectivity Aware Multi-net Routing Algorithm for Routing Grid with Obstacles

KOHIRA Yukihide, TAKAHASHI Atsushi

IEICE technical report (VLD2008-72,DC2008-40)   108 ( 298 )   73 - 78   2008.11

A Fast Gate-Level Register Relocation Method for Circuit Size Reduction in General-Synchronous Framework Reviewed International journal

Yukihide Kohira, Atsushi Takahashi

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E91-A ( 10 )   3030 - 3037   2008.10

A Routing Method based on Nearest Via Assignment for 2-Layer Ball Grid Array Packages

KURATA Yoshiaki, TOMIOKA Yoichi, KOHIRA Yukihide, TAKAHASHI Atsushi

IEICE technical report (VLD2008-55)   108 ( 224 )   49 - 54   2008.9

A Computation Method of Maximum of Achieving Specified Yield for Statistical Static Timing Analysis Reviewed

Shun Gokita, Yukihide Kohira, Atsushi Takahashi

Proc. DA Symposium 2008, IPSJ Symposium Series   2008 ( 7 )   193 - 198   2008.8

ILP-based optimization of time-multiplexed I/O assignment for multi-FPGA systems Reviewed International journal

Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura, Atsushi Takahashi

Proc. IEEE International Symposium on Circuits and Systems (ISCAS)   1800 - 1803   2008.5

A Maximum Wire Length Router in Routing Area with Obstacles using Upper Bound Estimation Considering Connectivity Reviewed

Yukihide Kohira, Suguru Suehiro, Atsushi Takahashi

Proc. the 21st Workshop on Circuits and Systems in Karuizawa   569 - 574   2008.4

Clock Scheduling Method and Delay Insertion Method for Minimization of Inserted Delay Reviewed

Yukihide Kohira, Shiyuuhei Tani, Atsushi Takahashi

Proc. the 21st Workshop on Circuits and Systems in Karuizawa   629 - 634   2008.4

Global Routing Method of Plating Lead for 2-Layer BGA Packages

Naoki Sato, Yoichi Tomioka, Atsushi Takahashi

IEICE Technical Report (VLD2007-154)   107 ( 507 )   61 - 66   2008.3

An Estimation of Maximum Wire Length in Routing Area with Obstacles

SUEHIRO Suguru, KOHIRA Yukihide, TAKAHASHI Atsushi

IEICE technical report (CAS2007-97)   107 ( 476 )   19 - 23   2008.2

A Fast Modification Algorithm for Shortest Path Tree and its Performance Evaluation

Tsutomu Ishida, Yukihide Kohira, Atsushi Takahashi

IEICE Technical Report (CAS2007-98)   107 ( 476 )   25 - 30   2008.2

Routability Driven Modification Method of Monotonic Via Assignment for 2-layer Ball Grid Array Packages Reviewed International journal

Yoichi Tomioka, Atsushi Takahashi

Proc. 13th Asia South Pacific Design Automation Conference (ASP-DAC)   238 - 243   2008.1

Low Area Pipelined Circuits by the Replacement of Registers with Delay Elements Reviewed International journal

Bakhtiar Affendi Rosdi, Atsushi Takahashi

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E90-A ( 12 )   2736 - 2742   2007.12

Fast Monotonic Via Assignment Excluding Mold Gates for 2-Layer Ball Grid Array Packages Reviewed International journal

Yoichi Tomioka, Atsushi Takahashi

Proc. 14th Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI)   192 - 197   2007.10

Evaluation of Register Relocation Method for General Synchronous Framework Reviewed

Yukihide Kohira, Atsushi Takahashi

Proc. DA Symposium 2007, IPSJ Symposium Series   2007 ( 7 )   193 - 198   2007.8

An Improved Clock Tree Synthesis Method by Using CAD Tools for General Synchronous Circuits Reviewed

Hiroyoshi Hashimoto, Yukihide Kohira, Atsushi Takahashi

Proc. DA Symposium 2007, IPSJ Symposium Series   2007 ( 7 )   199 - 204   2007.8

A Semi-Monotonic Via Assignment Method for 2-layer Ball Grid Array Packages Reviewed

Yoichi Tomioka, Atsushi Takahashi

Proc. DA Symposium 2007, IPSJ Symposium Series   2007 ( 7 )   145 - 150   2007.8

A fast maximum delay estimation method for specified yield by statistical static timing analysis

FURUYA Hiroki, KOHIRA Yukihide, TAKAHASHI Atsushi

2007 ( 39 )   75 - 79   2007.5

A Fast Register Relocation Method for Circuit Size Reduction in Generalized-Synchronous Framework Reviewed

Yukihide Kohira, Atsushi Takahashi

Proc. IEEE International Symposium on Circuits and Systems (ISCAS)   1795 - 1798   2007.5

Gate-Level Register Relocation in Generalized Synchronous Framework for Clock Period Minimization Reviewed International journal

Yukihide Kohira, Atsushi Takahashi

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E90-A ( 4 )   800 - 807   2007.4

Delay Balancing by Min-Cut Algorithm for Reducing the Area of Pipelined Circuits Reviewed

Bakhtiar Affendi Rosdi, Atsushi Takahashi

Proc. 20th Workshop on Circuits and Systems in Karuizawa   643 - 648   2007.4

A Clock Tree Synthesis Method by Using CAD Tools for General-synchronous Circuits

Yosuke Harada, Hiroyoshi Hashimoto, Yukihide Kohira, Atsushi Takahashi

IEICE Technical Report (VLD2006-127)   106 ( 548 )   49 - 53   2007.3

A Fast Clock Scheduling for Peak Power Reduction in LSI Reviewed

Yosuke Takahashi, Yukihide Kohira, Atsushi Takahashi

Proc. 17th ACM Great Lakes symposium on VLSI (GSVLSI)   582 - 587   2007.3

Replacement of Register with Delay Element for Reducing the Area of Pipelined Circuits. Reviewed International journal

Bakhtiar Affendi Rosdi, Atsushi Takahashi

Proc. IEEE Asia-Pacific Conference on Circuits and Systems (APCCAS)   802 - 805   2006.12

Routing of Monotonic Parallel and Orthogonal Netlists for Single-Layer Ball Grid Array Packages. Reviewed International journal

Yoichi Tomioka, Atsushi Takahashi

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E89-A ( 12 )   3551 - 3559   2006.12

Multi-Clock Cycle Paths and Clock Scheduling for Reducing the Area of Pipelined Circuits. Reviewed International journal

Bakhtiar Affendi Rosdi, Atsushi Takahashi

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E89-A ( 12 )   3435 - 3442   2006.12

A Fast Register Relocation Method for Circuit Size Reduction in Generalized-Synchronous Framework

Yukihide Kohira, Atsushi Takahashi

電子情報通信学会技術研究報告 (VLD2006-70)   106 ( 388 )   33 - 38   2006.11

Routability Driven Via Assignment and Routing for 2-Layer Ball Grid Array Packages

Yoichi Tomioka, Atsushi Takahashi

IEICE Technical Report (VLD2006-76)   106 ( 389 )   25 - 30   2006.11

Power Wave Smoothing by Clock Scheduling for Peak Power Reduction in LSI

Yosuke Takahashi, Atsushi Takahashi

IEICE Technical Report (VLD2006-69)   106 ( 388 )   27 - 32   2006.11

[Invited Talk] General synchronous circuits using global clock - design methodologies, tools, and prospects - Invited

Atsushi Takahashi

IPSJ SIG Technical Reports (2006-SLDM-126)   2006 ( 111 )   159 - 164   2006.10

Peak Power Reduction in LSI by Clock Scheduling

Yosuke Takahashi, Atsushi Takahashi

IEICE Technical Report (VLD2006-35)   106 ( 254 )   7 - 12   2006.9

Monotonic Parallel Routing to Reduce Maximum Congestion for Ball Grid Array Packages Reviewed

Yoichi Tomioka, Atsushi Takahashi

Proc. DA Symposium 2006, IPSJ Symposium Series   2006 ( 7 )   19 - 24   2006.7

Performance Evaluation of Negative Cycle Detection Algorithms

Tsutomu Ishida, Yukihide Kohira, Atsushi Takahashi

IPSJ SIG Technical Reports (2006-AL-107)   2006 ( 71 )   45 - 50   2006.7

Evaluation of 3D-Packing Representations for Scheduling of Dynamically Reconfigurable Systems Reviewed

Yukihide Kohira, Chikaaki Kodama, Kunihiro Fujiyoshi, Atsushi Takahashi

Proc. IEEE International Symposium on Circuits and Systems (ISCAS)   802 - 805   2006.5

Clock Period Minimization Method of Semi-Synchronous Circuits by Register Relocation Reviewed

Yukihide Kohira, Atsushi Takahashi

Proc. the 19th Workshop on Circuits and Systems in Karuizawa   259 - 264   2006.4

Global Routing by Iterative Improvements for Two-Layer Ball Grid Array Packages. Reviewed International journal

Yukiko Kubo, Atsushi Takahashi

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)   25 ( 4 )   725 - 733   2006.4

Practical Fast Clock-Schedule Design Algorithms. Reviewed International journal

Atsushi Takahashi

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E89-A ( 4 )   1005 - 1011   2006.4

Network-Flow Based Delay-Aware Partitioning Algorithm Reviewed International journal

Masato Inagi, Atsushi Takahashi

Proc. 13th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI)   417 - 422   2006.4

Optimal Register Merging Method after Register Relocation in Semi-Synchronous Framework Reviewed International journal

Yukihide Kohira, Atsushi Takahashi

Proc. 13th Workshop on Synthesis And System integration of Mixed Information technologies (SASIMI)   134 - 140   2006.4

A Clock Tree Construction Method Under Delay Variations

Masayuki Iguchi, Atsushi Takahashi

IPSJ SIG Technical Reports (2006-SLDM-124)   2006 ( 28 )   55 - 60   2006.3

Optimal Register Merging Method after Register Relocation in Semi-Synchronous Framework Reviewed

Yukihide Kohira, Atsushi Takahashi

Proc. 2006 IEICE General Conference   A ( A-3-4 )   68   2006.3

Improvement of Clustering Based Clock Scheduling Method

Yuuichi Sunahashiri, Yukihide Kohira, Atsushi Takahashi

IEICE Technical Report (VLD2005-113)   105 ( 644 )   31 - 36   2006.3

Low Area Pipelined Circuits by Multi-clock Cycle Path and Clock Scheduling Reviewed International journal

Bakhtiar Affendi Rosdi, Atsushi Takahashi

Proc. Asia and South Pacific Design Automation Conference (ASP-DAC)   260 - 265   2006.1

Monotonic Parallel and Orthogonal Routing for Single-Layer Ball Grid Array Packages Reviewed International journal

Yoichi Tomioka, Atsushi Takahashi

Proc. Asia and South Pacific Design Automation Conference (ASP-DAC)   642 - 647   2006.1

Modification of monotonic route to reduce max density for single layer BGA package

Yoshitaka Nomura, Atsushi Takahashi

IEICE Technical Report (VLD2005-95)   105 ( 513 )   43 - 48   2006.1

Analysis of Monotonic Pin Assignment and Monotonic Routing for Ball Grid Array Packages Reviewed

Yoichi Tomioka, Atsushi Takahashi

Proc. DA Symposium 2005, IPSJ Symposium Series   2005 ( 9 )   237 - 242   2005.8

A Via Assignment and Global Routing Method for 2-Layer Ball Grid Array Packages Reviewed International journal

Yukiko Kubo, Atsushi Takahashi

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E88-A ( 5 )   1283 - 1289   2005.5

An Algorithm to Calculate the Minimum Clock Period of a Semi-synchronous Circuit that Contains Multi-clock Cycle Path

Bakhtiar Affendi Rosdi, Atsushi Takahashi

IEICE Technical Report (VLD2005-8)   105 ( 58 )   13 - 18   2005.5

A Global Routing Method for 2-Layer Ball Grid Array Packages Reviewed

Yukiko Kubo, Atsushi Takahashi

Proc. International Symposium on Physical Design (ISPD)   36 - 43   2005.4

Clock Period Minimization Method of Semi-Synchronous Circuits by Delay Insertion Reviewed

Yukihide Kohira, Atsushi Takahashi

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E88-A ( 4 )   892 - 898   2005.4

Evaluation of 3D-packing representations for scheduling of dynamically reconfigurable systems. Reviewed

Yukihide Kohira, Chikaaki Kodama, Kunihiro Fujiyoshi, Atsushi Takahashi

211 - 216   2005.4

Practical Fast Clock Scheduling Design Algorithms Reviewed

Atsushi Takahashi

Proc. 18th Workshop on Circuits and Systems in Karuizawa   515 - 520   2005.4

Circuit Modification Method of Semi-Synchronous Circuits with Retiming

Eigo Kamibayashi, Yukihide Kohira, Atsushi Takahashi

IEICE Technical Report (VLD2004-146)   104 ( 709 )   55 - 60   2005.3

Clock Period Minimization Method of Semi-Synchronous Circuits by Delay Insertion Reviewed

Yukihide Kohira, Atsushi Takahashi

Proc. IEEE Asia-Pacific Conference on Circuits and Systems (APCCAS)   533 - 536   2004.12

3D-Floorplanning for Scheduling of Dynamically Reconfigurable Systems

Yukihide Kohira, Chikaaki Kodama, Kunihiro Fujiyoshi, Atsushi Takahashi

IEICE Technical Report (VLD2004-67)   104 ( 478 )   37 - 42   2004.12

Reduction on the Usage of Intermediate Registers for Pipelined Circuits Reviewed International journal

Bakhtiar Affendi Rosdi, Atsushi Takahashi

Proc. 12th Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI)   333 - 338   2004.10

Optimal Integer Delay-Budget Assignment on Directed Acyclic Graphs Reviewed International journal

Elaheh Bozorgzadeh, Soheil Ghiasi, Atsushi Takahashi, Majid Sarrafzadeh

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)   23 ( 8 )   1184 - 1199   2004.8

Incremental Timing Budget Management in Programmable Systems. Reviewed International journal

Elaheh Bozorgzadeh, Soheil Ghiasi, Atsushi Takahashi, Majid Sarrafzadeh

Proc. International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA)   240 - 246   2004.6

遅延挿入による準同期式回路のクロック周期最小化手法 Reviewed

小平行秀, 高橋篤司

第17回 回路とシステム軽井沢ワークショップ論文集   529 - 534   2004.4

A global routing method for 2-layer ball grid array packages. Reviewed

Yukiko Kubo, Atsushi Takahashi

535 - 540   2004.4

The Method to Construct Clock Tree with Low Power Consumption

Akihiko Moriya, Atsushi Takahashi

IEICE Technical Report (VLD2003-140)   103 ( 702 )   25 - 29   2004.3

Reduction of peak power in LSI by using semi-synchronous circuit design

Soji Mori, Atsushi Takahashi

IEICE Technical Report (VLD2003-141)   103 ( 702 )   31 - 36   2004.3

Improvement of Clock Scheduling Method in Consideration of Clock Tree Length

Hajime Yamasaki, Atsushi Takahashi

IEICE Technical Report (VLD2003-126)   103 ( 579 )   7 - 12   2004.1

Acceleration of Packing Using a Simulated Annealing Method with Limiting Moves in Low Temperature Region

Seiji Uchida, Atsushi Takahashi

IEICE Technical Report (VLD2003-97)   103 ( 476 )   163 - 168   2003.11

Optimal integer delay budgeting on directed acyclic graphs. Reviewed International journal

Elaheh Bozorgzadeh, Soheil Ghiasi, Atsushi Takahashi, Majid Sarrafzadeh

Proc. 40th Design Automation Conference (DAC)   920 - 925   2003.6

Network-Flow Based Delay-Aware Circuit Partitioning Algorithm Reviewed

Masato Inagi, Atsushi Takahashi

Proc. 16th Workshop on Circuits and Systems in Karuizawa   201 - 206   2003.4

A High-Speed and Low-Power Clock Tree Synthesis by Dynamic Clock Scheduling Reviewed

Keiichi Kurokawa, Takuya Yasui, Yoichi Matsumura, Masahiko Toyonaga, Atsushi Takahashi

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E85-A ( 12 )   2746 - 2755   2002.12

A Semi-Synchronous Circuit Design Method by Clock Tree Modification Reviewed

Seiichiro Ishijima, Tetsuaki Utsumi, Tomohiro Oto, Atsushi Takahashi

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E85-A ( 12 )   2596 - 2602   2002.12

A Clustering Based Fast Clock Schedule Algorithm for Light Clock-Trees Reviewed

Makoto Saitoh, Masaaki Azuma, Atsushi Takahashi

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E85-A ( 12 )   2756 - 2763   2002.12

Delay variation tolerant clock scheduling for semi-synchronous circuits. Reviewed

Hidetoshi Matsumura, Atsushi Takahashi

Proc. IEEE Asia-Pacific Conference on Circuits and Systems (APCCAS)   165 - 170   2002.10

A circuit optimization method by the register path modification in consideration of the range of feasible clock timing Reviewed

Takuya Yasui, Keiichi Kurokawa, Masahiko Toyonaga, Atsushi Takahashi

Proc. DA Symposium 2002, IPSJ Symposium Series   2002 ( 10 )   259 - 264   2002.7

A Clock Scheduling Method under Global and Local Delay Variations Reviewed

Hidetoshi Matsumura, Atsushi Takahashi

Proc. DA Symposium 2002, IPSJ Symposium Series   2002 ( 10 )   143 - 148   2002.7

Clustering Based Clock Scheduling in Consideration of Clock Tree Length

Hajime Yamasaki, Atsushi Takahashi

IEICE Technical Report (VLD2002-35)   102 ( 164 )   119 - 124   2002.6

Acceleration of Packing by Move Restriction in Simulated Annealing

Seiji Uchida, Atsushi Takahashi

IEICE Technical Report (VLD2002-31)   102 ( 164 )   95 - 100   2002.6

A Module Placement Algorithm by Force-directed Method without Overlapping Reviewed

Hiroyuki Yamazaki, Naoto Mikami, Atsushi Takahashi

IPSJ Journal   43 ( 5 )   1304 - 1314   2002.5

Network-Flow Based Delay-Aware Circuit Partitioning Algorithm

Masato INAGI, Atsushi Takahashi, Kengo R. Azegami

IEICE Technical Report (VLD2002-7)   102 ( 72 )   37 - 42   2002.5

Parameter Setting in Simulated Annealing using Q-sequence for Good Layouts in Short Time Reviewed

Masashi Tsuboi, Keishi Sakanushi, Atsushi Takahashi

Proc. the 15th Workshop on Circuits and Systems in Karuizawa   Vol.   125 - 130   2002.4

An Improvement of Network-Flow Based Multi-Way Circuit Partitioning Algorithm Reviewed International journal

Kengo R. Azegami, Masato Inagi, Atsushi Takahashi, Yoji Kajitani

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E85-A ( 3 )   655 - 663   2002.3

Hierarchical BSG floorplan for hierarchical VLSI circuit design Reviewed International journal

Zhonglin Wu, Shigetoshi Nakatake, Atsushi Takahashi, Yoji Kajitani

Electronics and Communications in Japan (Part III: Fundamental Electronic Science)   85 ( 3 )   12 - 21   2001.11

A Practical Clock Tree Synthesis for Semi-Synchronous Circuits Reviewed International journal

Keiichi Kurokawa, Takuya Yasui, Masahiko Toyonaga, Atsushi Takahashi

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E84-A ( 11 )   2705 - 2713   2001.11

MIPS互換準同期式プロセッサの試作

内海哲章, 石島誠一郎, 大戸友博, 高橋篤司

第5回システムLSIワークショップ講演資料集及びポスタ資料集   299 - 302   2001.11

An algorithm to enumerate all floorplans by using Q-sequence and its applications to the boundary constraint problam

Li Yan Jin, Keishi Sakanushi, Atsushi Takahashi, Hiroshi Murata

IEICE Technical Report (VLD2001-102)   101 ( 467 )   79 - 84   2001.11

High-Performance Clock Synchronous Circuits and Non-Clock Synchronous Circuits

Atsushi Takahashi

IPSJ SIG Technical Reports (2001-SLDM-102)   2001 ( 113 )   19 - 22   2001.11

耐遅延変動クロックスケジュールの提案

松村秀敏, 高橋篤司

電子情報通信学会技術研究報告 (VLD2001-121)   101 ( 468 )   57 - 62   2001.11

Semi-Synchronous Circuit Design Method by Clock Tree Modification Reviewed International journal

Seiichiro Ishijima, Tetsuaki Utsumi, Tomohiro Oto, Atsushi Takahashi

Proc. Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI)   382 - 386   2001.10

Linear Time Decodable Rectangular Dissection to Represent Arbitrary Packing Using Q-Sequence Reviewed International journal

Masashi Tsuboi, Chikaaki Kodama, Keishi Sakanushi, Kunihiro Fujiyoshi, Atsushi Takahashi

Proc. Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI)   272 - 278   2001.10

Module Placement for Safe Routing using Sequence-Pair

Takashi Nojima, Keishi Sakanushi, Atsushi Takahashi, Yoji Kajitani

IEICE Technical Report (VLD2001-54)   101 ( 144 )   59 - 65   2001.6

An Efficient Algorithm to Extract an Optimal Sub-Circuit by the Minimum Cut Reviewed

Kengo R. Azegami, Atsushi Takahashi, Yoji Kajitani

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E84-A ( 5 )   1301 - 1308   2001.5

Comparison among various synthesis methods on semi-synchronous framework

Tetsuaki Utsumi, Seiichiro Ishijima, Atsushi Takahashi

IEICE Technical Report (VLD2001-11)   101 ( 46 )   23 - 26   2001.5

A Feasible Condition for Semi-Synchronous Circuits under Delay Variation Reviewed

Hidetoshi Matsumura, Atsushi Takahashi

Proc. the 14th Workshop on Circuits and Systems in Karuizawa   101 - 106   2001.4

Clustering Based Fast Clock Scheduling for Light Clock-Tree Reviewed International journal

Makoto Saitoh, Masaaki Azuma, Atsushi Takahashi

Proc. Conference on Design, Automation and Test in Europe (DATE)   240 - 245   2001.3

Module Placement algorithm by Force-directed Method without Overlapping

Hiroyuki Yamazaki, Naoto Mikami, Atsushi Takahashi, Yoji Kajitani

IEICE Technical Report (VLD2000-136)   100 ( 646 )   13 - 18   2001.3

Clock scheduling Method to Reduce the Peak Power for Semi-synchronous Circuits

Tsutomu Utagawa, Atsushi Takahashi

IEICE Technical Report (VLD2000-143)   100 ( 646 )   55 - 60   2001.3

Semi-Synchronous Clock Tree Construction Under Synchronous Circuit Design Environment

Seiichiro Ishijima, Atsushi Takahashi

IPSJ SIG Technical Reports (2000-SLDM-99)   2001 ( 2 )   73 - 79   2001.1

Clock schedule design for minimum realization cost Reviewed International journal

Tomoyuki Yoda, Atsushi Takahashi

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E83-A ( 12 )   2552 - 2557   2000.12

Processor Design by Semi-synchronous Design Method

Tomohiro Oto, Seiichiro Ishijima, Tetsuaki Utsumi, Kengo R. Azegami, Atsushi Takahashi

IEICE Technical Report (VLD2000-101)   100 ( 473 )   191 - 196   2000.11

A Fast Clock-scheduling Algorithm based on a Clustering in Consideration of Constructing a Clock-tree

Makoto Saitoh, Masaaki Azuma, Atsushi Takahashi

IEICE Technical Report (VLD2000-100)   100 ( 473 )   185 - 190   2000.11

Hierarchical BSG Floorplan for Hierarchical VLSI Circuit Design Reviewed

Zhonglin Wu, Shigetoshi Nakatake, Atsushi Takahashi, Yoji Kajitani

IEICE Trans. Fundamentals (Japanese Edition)   J83-A ( 10 )   1161 - 1168   2000.10

Placement Algorithm for Routing with Minimum Switches of a Special FPGA with Directional Architecture Reviewed

Takashi Nojima, Yoji Kajitani, Atsushi Takahashi

Proc. the 2000 Engineering Sciences Society Conference of IEICE   A ( A-3-4 )   71   2000.9

I/O Pin Assignment Algorithm Based on the Closeness Reviewed

Masato Inagi, Yoji Kajitani, Atsushi Takahashi

Proc. the 2000 Engineering Sciences Society Conference of IEICE   A ( A-3-1 )   68   2000.9

A Clock-Tree Routing Algorithm for Low Power Using Feasible Range of Clock Schedule

Masaaki Azuma, Makoto Saitoh, Atsushi Takahashi

IPSJ SIG Technical Reports (2000-SLDM-97)   2000 ( 79 )   63 - 68   2000.9

Clustering based Clock Scheduling in Consideration of Layout Reviewed

Makoto Saitoh, Atsushi Takahashi

Proc. DA Symposium 2000, IPSJ Symposium Series   2000 ( 8 )   39 - 42   2000.7

A semi-synchronous clock tree synthesis by dynamical clock scheduling Reviewed

Takuya Yasui, Keiichi Kurokawa, Masahiko Toyonaga, Atsushi Takahashi

Proc. DA Symposium 2000, IPSJ Symposium Series   2000 ( 8 )   43 - 48   2000.7

A Practical Clock Tree Synthesis for Semi-Synchronous Circuits Reviewed

Masahiko Toyonaga, Keiichi Kurokawa, Takuya Yasui, Atsushi Takahashi

Proc. International Symposium on Physical Design (ISPD)   159 - 164   2000.5

A synthesis of multiplier based on semi-synchronous design

Tetsuaki Utsumi, Atsushi Takahashi

IEICE Technical Report (VLD2000-2)   100 ( 35 )   9 - 14   2000.5

A Report on Design, Automation and Test in Europe Conference 2000 (DATE2000)

Atsushi Takahashi

IEICE Technical Report (VLD2000-4)   100 ( 35 )   23 - 24   2000.5

A fast algorithm to compute the minimum clock period of Semi-Synchronous Circuits

Ryosuke Oishi, Atsushi Takahashi

IEICE Technical Report (VLD99-125)   99 ( 659 )   63 - 68   2000.3

Partition, Packing and Clock Distribution-A New Paradigm of Physical Design. Reviewed

Yoji Kajitani, Atsushi Takahashi, Kengo R. Azegami, Shigetoshi Nakatake

Proc. 13th International Conference on VLSI Design (VLSI Design)   11   2000.1

An Efficient Algorithm to Extract an Optimal Sub-Circuit by the Minimum Cut

Kengo R. Azegami, Atsushi Takahashi, Yoji Kajitani

電子情報通信学会技術研究報告 (VLD99-93)   99 ( 529 )   49 - 56   2000.1

疑似気圧モデルに基づくVLSIフロアプランの局所修正

大戸 友博, 高橋 篤司, 梶谷 洋司

情報処理学会研究報告 (99-SLDM-93)   99 ( 101 )   127 - 134   1999.11

Clock Period Minimization of Semi-Synchronous Circuits by Gate-Level Delay Insertion Reviewed

Tomoyuki Yoda, Atsushi Takahashi

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E82-A ( 11 )   2383 - 2389   1999.11

Schedule-Clock-Tree Routing for Semi-Synchronous Circuits Reviewed

Kazunori Inoue, Wataru Takahashi, Atsushi Takahashi, Yoji Kajitani

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E82-A ( 11 )   2431 - 2439   1999.11

Three-layer L-shaped Channel Routing Algorithm with Nets Sharing

Tsutomu Utagawa, Atsushi Takahashi

IEICE Technical Report (VLD99-67)   99 ( 317 )   23 - 29   1999.9

Evaluation of Clock Tree Layout in Consideration of Delay Variations

Masaaki Azuma, Atsushi Takahashi

IEICE Technical Report (VLD99-52)   99 ( 262 )   1 - 8   1999.8