Organization
Institute of Integrated Research Laboratory for Future Interdisciplinary Research of Science and Technology Researcher
Title
Researcher
External link
SHIOTSU YUSAKU
Education
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Tokyo Institute of Technology
2020.4 - 2023.3
Country： Japan
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Tokyo Institute of Technology
2018.3 - 2020.3
Country： Japan
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Tokyo Institute of Technology
2016.4 - 2018.3
Country： Japan
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Tokyo National College of Technology
2011.4 - 2016.3
Country： Japan
Research History
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Institute of Science Tokyo Researcher
2024.10
Country：Japan
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Tokyo Institute of Technology Researcher
2023.4 - 2024.9
Country：Japan
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Japan Society for the Promotion of Science
2021.4 - 2023.3
Papers
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Yusaku Shiotsu, Satoshi Sugahara
IEEE Journal on Exploratory Solid-State Computational Devices and Circuits 11 25 - 33 2025.2
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Yusaku Shiotsu, Satoshi Sugahara
IEEE Journal on Exploratory Solid-State Computational Devices and Circuits 8 ( 2 ) 134 - 144 2022.12
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A New Ultralow-Voltage Retention SRAM Cell Enhancing Noise Immunity Reviewed
Katsutoshi Ito, Yusaku Shiotsu, Satoshi Sugahara
IEEE Open Journal of Circuits and Systems 6 370 - 382 2025
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Spin Injection Behavior of CoFe/MgO/Si Tunnel Contacts: Effects of Radical Oxygen Annealing Reviewed
Taiju Akushichi, Yota Takamura, Yusaku Shiotsu, Shuu’ichirou Yamamoto, Satoshi Sugahara
Journal of Electronic Materials 52 ( 10 ) 6902 - 6910 2023.8
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Ultralow-Voltage Retention SRAM With a Power Gating Cell Architecture Using Header and Footer Power-Switches Reviewed
Hayato Yoshida, Yusaku Shiotsu, Daiki Kitagata, Shuu'ichirou Yamamoto, Satoshi Sugahara
IEEE Open Journal of Circuits and Systems 2 520 - 533 2021
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Modeling and Design of Thin-Film π-Type Micro Thermoelectric Generator Using Vacuum/Insulator-Hybrid Isolation for Self-Powered Wearable Devices Reviewed
Yusaku Shiotsu, Toshimasa Seino, Tsuyoshi Kondo, Satoshi Sugahara
IEEE Transactions on Electron Devices 67 ( 9 ) 3834 - 3842 2020.9
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Modeling and Design of a New Piezoelectronic Transistor for Ultralow-Voltage High-Speed Integrated Circuits Reviewed
Yusaku Shiotsu, Shuu'ichirou Yamamoto, Yusuke Shuto, Hiroshi Funakubo, Minoru Kuribayashi Kurosawa, Satoshi Sugahara
IEEE Transactions on Electron Devices 67 ( 9 ) 3852 - 3860 2020.9
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Y Shiotsu, T Seino, N Chiwaki, S Sugahara
Journal of Physics: Conference Series 1407 ( 1 ) 012099-1 - 012099-4 2019.11
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Enhancement of magnetic circular dichroism in bi-layered ZnO-Bi:YIG thin films Reviewed
Shinichiro Mito, Yusaku Shiotsu, Junji Sasano, Hiroyuki Takagi, Mitsuteru Inoue
AIP Advances 7 ( 5 ) 056316-1 - 056316-4 2017.2
Presentations
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An energy-efficient parallel-processing in-memory BNN accelerator macro using XNOR-SRAM
近藤慶音, 塩津勇作, 菅原聡
The 73rd JSAP Spring Meeting 2026 2026.3
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Design of parallel-processing in-memory neural-network accelerator macro for INT4 inference
塩津勇作, 菅原聡
The 73rd JSAP Spring Meeting 2026 2026.3
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Design of parallel-READ single-ended SRAM macros for near energy-minimum-point operation
矢口忠勝, 塩津勇作, 菅原聡
The 73rd JSAP Spring Meeting 2026 2026.3
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Design and performance of single-ended SRAM cell for near energyminimum-point operation International conference
T. Yaguchi, Y. Shiotsu, S. Sugahara
IEEE International Meeting for Future of Electron Devices, Kansai 2025.11 IEEE EDS Kansai Chapter
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Design methodology for a radiation-hardened SRAM cell
野見山敏輝, 塩津勇作, 菅原聡
The 86th JSAP Autumn Meeting 2025 2025.9
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A high-noise-immunity SRAM cell for energy-minimum-point-operation PIMs
伊藤克俊, 藤原拓真, 塩津勇作, 菅原聡
The 86th JSAP Autumn Meeting 2025 2025.9
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Design of asymmetric SRAM cell for energy-minimum-point operation
藤下涼, 塩津勇作, 菅原聡
The 86th JSAP Autumn Meeting 2025 2025.9
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Design and performance of single-ended SRAM cells for near energy-minimum-point operation
矢口忠勝, 塩津勇作, 菅原聡
The 86th JSAP Autumn Meeting 2025 2025.9
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A parallel-processing-in-memory BNN accelerator macro using XNOR-SRAM
近藤慶音, 塩津勇作, 菅原聡
The 86th JSAP Autumn Meeting 2025 2025.9
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Energy-minimum point for PIM-type neural-network accelerator macros having parallelized MAC units
Yusaku Shiotsu, Satoshi Sugahara
The 72nd JSAP Spring Meeting 2025 2025.3
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Comparative Study of Gain Cells for Pseudo-SRAM International conference
S. Yoshida, Y. Shiotsu, S. Sugahara
IEEE International Meeting for Future of Electron Devices, Kansai 2024.11 IEEE EDS Kansai Chapter
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Design of Highly-Stable Energy-Minimum-Point SRAM Using Ultralow-Voltage Retention Cell International conference
K. Ito, Y. Shiotsu, S. Sugahara
IEEE International Meeting for Future of Electron Devices, Kansai 2024.11 IEEE EDS Kansai Chapter
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Design and performance of a 10T-SRAM cell using isolated read ports for low voltage operation
Tadakatsu Yaguchi, Yusaku Shiotsu, Satoshi Sugahara
The 85th JSAP Autumn Meeting 2024 2024.9
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A processing-in-memory SRAM cell with XNOR function for energy minimum-point operation
近藤慶音, 塩津勇作, 菅原聡
The 85th JSAP Autumn Meeting 2024 2024.9
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Comparative study of gain cells for pseudo-SRAM
吉田誠, 塩津勇作, 菅原聡
The 85th JSAP Autumn Meeting 2024 2024.9
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Design of a ULVR-SRAM cell for highly stable energy minimum-point operation
伊藤克俊, 塩津勇作, 菅原聡
The 85th JSAP Autumn Meeting 2024 2024.9
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Power-gating architecture and performance of nonvolatile SRAM
加藤豪人, 大木治弥, 塩津勇作, 山本修一郎, 菅原聡
The 85th JSAP Autumn Meeting 2024 2024.9
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Design of an INT4-inference neural-network accelerator macro for energy minimum point operation
塩津勇作, 菅原聡
The 85th JSAP Autumn Meeting 2024 2024.9
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Variation tolerance analysis of ultralow-voltage SRAM cells configured with piezoelectronic transistors
塩津勇作, 菅原聡
The 71st JSAP Spring Meeting 2024 2024.3
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Power-gating performance of nonvolatile SRAM using FinFETs for low-voltage operation
塩津勇作, 山崎修, 菅原聡
The 71st JSAP Spring Meeting 2024 2024.3
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Design and analysis of an 8kB macro for a new ultralow-voltage retention SRAM
Katsutoshi Ito, Yusaku Shiotsu, Satoshi Sugahara
The 84th JSAP Autumn Meeting 2023 2023.9
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A binarized neural network accelerator macro with parallelized MAC units using ULVR-SRAM
塩津勇作, 菅原聡
The 84th JSAP Autumn Meeting 2023 2023.9
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Power-gating performance of ultralow-voltage-retention SRAM for near-threshold-voltage operation
Taketo Kato, Yusaku Shiotsu, Syuu'ichirou Yamamoto, Satoshi Sugahara
The 83rd JSAP Autumn meeting 2022 2022.9
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Design of nonvolatile SRAM using FinFETs for low-voltage operation
Osamu Yamazaki, Yusaku Shiotsu, Shuu'ichirou Yamamoto, Satoshi Sugahara
The 83rd JSAP Autumn meeting 2022 2022.9
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Proposal of a new ultralow-voltage-retention SRAM (ULVR-SRAM) cell
Katsutoshi Ito, Yusaku Shiotsu, Shuu'ichirou Yamamoto, Satoshi Sugahara
The 83rd JSAP Autumn meeting 2022 2022.9
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超低電圧リテンションSRAMのエネルギー最小点動作とそのBNNアクセラレータへの応用 Invited
塩津勇作, 原拓実, 菅原聡
電子情報通信学会集積回路研究会 メモリ技術と集積回路技術一般 2022.4 電子情報通信学会
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Power-gating performance and architecture of ultralow-voltage-retention SRAM
Hiroki Yano, Yusaku Shiotsu, Shuu'ichirou Yamamoto, Satoshi Sugahara
The 69th JSAP Spring Meeting 2022 2022.3
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Modeling of transverse-type thin-film micro-TEG modules using various interlayer insulators
Kaito Sanuki, Hiroyuki Endou, Yusaku Shiotsu, Satoshi Sugahara
The 69th JSAP Spring Meeting 2022 2022.3
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Performance of a binarized neural network accelerator using ULVR-SRAM
Yusaku Shiotsu, Satoshi Sugahara
The 69th JSAP Spring Meeting 2022 2022.3
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Design and analysis of ULVR-SRAM using automatic body-bias control
斎藤修平, 塩津勇作, 原拓実, 山本修一郎, 菅原聡
The 82nd JSAP Autumn Meeting 2021 2021.9
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Design and analysis of an 8kB ULVR-SRAM macro for near-threshold voltage operations
原拓実, 塩津勇作, 山本修一郎, 菅原聡
The 82nd JSAP Autumn Meeting 2021 2021.9
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Simplified lumped-constant-circuit model of transverse-type thin-film micro-TEG modules
Hiroyuki Endou, Yusaku Shiotsu, Satoshi Sugahara
The 82nd JSAP Autumn Meeting 2021 2021.9
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Proposal and performance prediction of a BNN accelerator using ULVR-SRAM
Yusaku Shiotsu, Shuu'ichirou Yamamoto, Satoshi Sugahara
The 82nd JSAP Autumn Meeting 2021 2021.9
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Design and analysis of ultralow-voltage-retention Flip-Flop configured with bulk devices
Tsubasa Matsuzaki, Yusaku Shiotsu, Shuu'ichirou Yamamoto, Satoshi Sugahara
The 82nd JSAP Autumn Meeting 2021 2021.9
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ボディバイアス効果を用いたULVR-SRAMセルの設計とそのパワーゲーティング性能
塩津 勇作, 吉田 隼, 山本 修一郎, 菅原 聡
LSIとシステムのワークショップ2021 2021.5 電子情報通信学会
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ニアスレッショルド電圧動作超低電圧リテンションSRAMの設計と性能解析
原拓実, 塩津勇作, 山本修一郎, 菅原聡
LSIとシステムのワークショップ2021 2021.5 電子情報通信学会
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Power-gating performance of caches using ultralow-voltage-retention SRAM
Hayato Yoshida, Yusaku Shiotsu, Shuu'ichiro Yamamoto, Satoshi Sugahara
The 68th JSAP Spring Meeting 2021 2021.3
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High-accuracy modeling of transverse-type thin-film micro-TEG modules
Hiroyuki Endou, Yusaku Shiotsu, Hayato Kumagai, Satoshi Sugahara
The 68th JSAP Spring Meeting 2021 2021.3
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Modeling of transverse-type Si-nanowire micro-TEG modules
Hayato Kumagai, Yusaku Shiotsu, Hiroyuki Endou, Satoshi Sugahara
The 68th JSAP Spring Meeting 2021 2021.3
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Energy-efficient operation at energy minimum point for ultralow-voltage-retention SRAM
Yusaku Shiotsu, Shuu'ichirou Yamamoto, Satoshi Sugahara
The 68th JSAP Spring Meeting 2021 2021.3
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Design of ULVR-SRAM cell for near-threshold voltage operation
Takumi Hara, Hayato Yoshida, Yusaku Shiotsu, Shuu'ichirou Yamamoto, Satoshi Sugahara
The 68th JSAP Spring Meeting 2021 2021.3
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Energy-efficient operation at energy minimum point for ultra-low-voltage-retention FF
Kenichiro Takiguchi, Yusaku Shiotsu, Tsubasa Matsuzaki, Shuu'ichirou Yamamoto, Satoshi Sugahara
The 68th JSAP Spring Meeting 2021 2021.3
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MODELING AND DESIGN OF TRANSVERSE-TYPE MICRO THERMOELECTRIC GENERATOR USING SILICON NANOWIRES International conference
T. Kumagai, Y. Shiotsu, S. Sugahara
IEEE International Conference on Micro Electro Mechanical Systems 2021.1 IEEE
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Design and analysis of a new ultralow-voltage-retention SRAM cell
Daiki Kitagata, Hayato Yoshida, Yusaku Shiotsu, Shuu'ichirou Yamamoto, Satoshi Sugahara
The 81st JSAP Autumn Meeting 2020 2020.9
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Design methodology of transverse-type micro-TEG modules using Si-nanowires for high output power
Hayato Kumagai, Yusaku Shiotsu, Hiroyuki Endou, Satoshi Sugahara
The 81st JSAP Autumn Meeting 2020 2020.9
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Design and analysis of 8kB SRAM macro using a new ultralow-voltage-retention architecture
Yusaku Shiotsu, Daiki Kitagata, Shuu'ichirou Yamamoto, Satoshi Sugahara
The 81st JSAP Autumn Meeting 2020 2020.9
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Fully optimized design and performance of transverse-type micro-TEG modules using Si-nanowires
Hayato Kumagai, Yusaku Shiotsu, Hiroyuki Endou, Satoshi Sugahara
The 81st JSAP Autumn Meeting 2020 2020.9
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Design optimization of thin-film transverse-type micro-TEG modules using Heusler alloy
Yusaku Shiotsu, Hiroyuki Endou, Hayato Kumagai, Satoshi Sugahara
The 67th JSAP Spring Meeting 2020 2020.3
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Design and performance of Flip-Flops configured with piezoelectronic transistors
Yusaku Shiotsu, Shuu'ichirou Yamamoto, Hiroshi Funakubo, Minoru Kuribayashi Kurosawa, Satoshi Sugahara
The 80th JSAP Autumn Meeting 2019 2019.9
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Optimized design of transverse-type micro-TEG modules using silicon nanowires
Hayato Kumagai, Yusaku Shiotsu, Hiroyuki Endou, Satoshi Sugahara
The 80th JSAP Autumn Meeting 2019 2019.9
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Design optimization of transverse-type thin-film μTEG modules: Effects of interlayer materials
Hiroyuki Endou, Hayato Kumagai, Yusaku Shiotsu, Satoshi Sugahara
The 80th JSAP Autumn Meeting 2019 2019.9
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Low-leakage design of a new piezoelectronic transistor and its SRAM application
Yusaku Shiotsu, Shuu'ichiro Yamamoto, Hiroshi Funakubo, Minoru Kuribayashi Kurosawa, Satoshi Sugahara
The 66th JSAP Spring Meeting 2019 2019.3
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Design optimization of π-type thin-film micro-TEG modules: Effects of thickness of the thermoelectric material
Hayato Kumagai, Yusaku Shiotsu, Takashi Okubo, Satoshi Suguhara
The 66th JSAP Spring Meeting 2019 2019.3
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Design and Performance of Silicon Nanowire Micro Thermoelectric Generators International conference
Y. Shiotsu, T. Okubo, H. Kumagai, S. Sugahara
Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon 2019.3
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Design of New Piezoelectronic Transistors and Their Ultralow-Voltage SRAM Application International conference
Y. Shiotsu, S. Yamamoto, H. Funakubo, M. K. Kurosawa, S. Sugahara
Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon 2019.3
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Thin-Film π-Type Micro TEG Using Vacuum/Insulator-Hybrid Isolation with Convex-Shape Hot-Plate Module Structure for Wearable Device Applications International conference
Y. Shiotsu, T. Seino, N. Chiwaki, S. Sugahara
Micro and Nanotechnology for Power Generation and Energy Conversion Applications 2018.12
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Design methodology of a new piezoelectronic transistor
Yusaku Shiotsu, Shuu'ichiro Yamamoto, Hiroshi Funakubo, Minoru Kuribayashi Kurosawa, Satoshi Sugahara
The 79th JSAP Autumn Meeting 2018 2018.9
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Design optimization of π-type thin-film micro-TEG modules using various interlayer insulators
Hayato Kumagai, Yusaku Shiotsu, Takashi Okubo, Satoshi Sugahara
The 79th JSAP Autumn Meeting 2018 2018.9
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Design and Circuit Performance of a New Piezoelectronic Transistor International conference
Y. Shiotsu, S. Yamamoto, H. Funakubo, M. K. Kurosawa, S. Sugahara
IEEE Silicon Nanoelectronics Workshop 2018.6 IEEE
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Design of a new piezoelectronic transistor and its device and circuit performances
Yusaku Shiotsu, Shuu'ichiro Yamamoto, Yusuke Shuto, Hiroshi Hunakubo, Minoru Kurosawa, Satoshi Sugahara
The 65th JSAP Spring Meeting 2018 2018.3
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Magnetic Circular Dichroism in Bi-layered ZnO-Bi:YIG Thin Films
菊地颯希, 水戸慎一郎, 塩津勇作, 笹野順司
2016.11
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Enhancement of Magnetic Circular Dichroism in Bi-layered ZnO-Bi:YIG Thin Films International conference
S. Mito, Y. Shiotsu, J. Sasano, H. Takagi, M. Inoue
61st Annual Conference on Magnetism and Magnetic Materials 2016.11
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Magneto-optical response of ZnO nanocrystals on magnetic garnet thin films
Yusaku Shiotsu, Shinichiro Mito, Junji Sasano
The 63rd JSAP Spring Meeting 2016 2016.3
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不揮発性SRAM：エッジコンピューティングの革新的低消費電力技術 Invited
塩津勇作, 山本修一郎, 菅原聡
日本学術振興会 先進薄膜界面機能創成委員会 第6回研究会 2021.10 日本学術振興会
Industrial property rights
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処理装置
菅原 聡, 塩津 勇作
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記憶回路
菅原 聡, 塩津 勇作
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双安定回路および電子回路
菅原 聡, 塩津 勇作
Research Projects
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新型ゲインセルを用いた擬似SRAMの研究開発
Grant number：26K14753 2026.4 - 2029.3
日本学術振興会 科学研究費助成事業 基盤研究(C)
塩津 勇作
Grant amount：\4550000 （ Direct Cost: \3500000 、 Indirect Cost：\1050000 ）
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CMOSロジックの低消費電力技術に関する研究
Grant number：21J10430 2021.4 - 2023.3
日本学術振興会 科学研究費助成事業 特別研究員奨励費
塩津 勇作
Grant amount：\1500000 （ Direct Cost: \1500000 ）
本年度は前年度設計した3M-SRAMを用いたProcessing-in-memory(PIM)型ニューラルネットワーク(NN)アクセラレータマクロの設計およびその性能評価・検証を中心に研究を進めた．NNのアーキテクチャには2値化NN(BNN)を用いた．開発したPIM型BNNアクセラレータ(BNA)マクロは重みデータとバイアスデータを3M-SRAMマクロに格納する．メモリ部に3M-SRAMを用いることで，通常のSRAMでは実現できないエネルギー最小点(EMP)での動作が可能となり，さらに0.2V程度の超低電圧（ULV）でデータ保持を行うULVリテンションを用いたパワーゲーティング（PG）も導入できる．また，このBNAマクロを用いれば，任意のサイズ・形状のネットワークを複数マクロで構成できる．
BNAマクロの性能を寄生抵抗・容量を考慮した高速SPICEによる大規模シミュレーションにより評価を行った．開発したBNAマクロは0.2VのULVリテンションを用いた実質的なPGによって，待機時電力を84%削減できることを示した．さらに，0.4VのEMP動作により動作時電力を通常電圧動作(1.2V)と比べて1/100にまで削減できることを示した．3M-SRAMのEMP動作に基づく推論によって，エネルギー効率(TOPS/W)は最大化し，許容される積和演算の並列数も大幅に増大されることから，演算能力(TOPS)も飛躍的に向上できることを示した．例えば，通常電圧動作時に比べて，演算性能(TOPS)が同じであれば，1/10程度の消費電力で済み，消費電力が同じであれば，10倍程度の演算性能を実現できる．全結合層を用いたベンチマークから，このBNAマクロを用いれば，並列数に応じて0.5-4TOPSの高い演算能力を61-65TOPS/Wの高いエネルギー効率で実現できることを明らかにした．