論文
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A Time-Division MIMO Phased-Array Receiver Utilizing Nyquist-Rate Fast Beam Switching With Minimized Hardware for 5G and Beyond
Minzhe Tang, Yi Zhang, Jian Pang, Zheng Li, Dongfan Xu, Dingxin Xu, Yuncheng Zhang, Kazuaki Kunihiro, Hiroyuki Sakai, Atsushi Shirane, Kenichi Okada
IEEE Journal of Solid-State Circuits 2026年7月
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A Low-Spur Fractional-N DPLL With Analog Pre-Distortion DTC Implementing Second-/Third-Order Calibration
Daxu Zhang, Yuncheng Zhang, Dingxin Xu, Hongye Huang, Waleed Madany, Zezheng Liu, Wenqian Wang, Yuang Xiong, Ashbir Aviat Fadila, Duo Li, Minzhe Tang, Dongfan Xu, Atsushi Shirane, Kenichi Okada
IEEE Journal of Solid-State Circuits 2026年
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A 52Gb/s 8.9-dBm EIRP 300-GHz-Band Amplifier-Last Outphasing Transmitter With Path Mismatch Calibration in 65-nm CMOS
Yuncheng Zhang
IEEE JOURNAL OF SOLID-STATE CIRCUITS 2026年
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A 300-GHz-Band 16.2-dBm EIRP Four-Element Amplifier-Last Phased-Array Transmitter With On-Chip Vivaldi Antenna in 65-nm CMOS
Chun Wang, Hans Herdian, Wenbin Zheng, Olivia Angel Yong, Chenxin Liu, Jill Mayeda, Yuxuan Liu, Wenqian Wang, Yuncheng Zhang, Carrel da Gomez, Abanob Shehata, Sena Kato, Ibrahim Abdo, Teruo Jyo, Hiroshi Hamada, Hiroyuki Takahashi, Hiroyuki Sakai, Atsushi Shirane, Kenichi Okada
IEEE Journal of Solid-State Circuits 2026年
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A 9-GHz Digital Fractional-N PLL With Dynamic-Threshold DTC
Daxu Zhang, Yuncheng Zhang, Zezheng Liu, Yuang Xiong, Wenqian Wang, Duo Li, Minzhe Tang, Dongfan Xu, Dingxin Xu, Kazuaki Kunihiro, Hiroyuki Sakai, Kenichi Okada
IEEE Solid-State Circuits Letters 2026年
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A 9.7GHz Self-Linearized-VCO-Based FMCW Chirp Generator Achieving 1.56GHz/μs Slope and 0.57μs Duration with 0.094% rms Frequency Error
Yuncheng Zhang
2026 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE, ISSCC 2026年
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A Ka-Band Time-Modulated Phase-Invariant Variable-Gain Amplifier With 30-dB Gain Tuning Based on Duty-Cycle Control
Yuncheng Zhang
IEEE JOURNAL OF SOLID-STATE CIRCUITS 2026年
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A Ka-Band Eight-Stream Phased-Array MIMO Receiver With Time-Hopping Blocker Rejection for 6G
Yuncheng Zhang
IEEE JOURNAL OF SOLID-STATE CIRCUITS 2026年
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A 142--164-GHz Phased-Array AiP Module With High-Power-Density and High-Efficiency Transceiver in 65-nm CMOS for 6G UE
Yamazaki, Yudai, Morishita, Yohei, Park, Sunghwan, Uchino, Takaya, Liu, Chenxin, Sakamaki, Jun, Egami, Akihiro, Hasaba, Ryosuke, Takahashi, Ken, Abe, Tomoki, others
IEEE Journal of Solid-State Circuits 2026年
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A DPD/Dither-Free DPLL Based on a Cascaded Fractional Divider and Pseudo-Differential DTCs Achieving a —62.1-dBc Fractional Spur
Dingxin Xu, Zezheng Liu, Yifeng Kuai, Hongye Huang, Yuncheng Zhang, Zheng Sun, Bangan Liu, Wenqian Wang, Yuang Xiong, Junjun Qiu, Waleed Madany, Yi Zhang, Ashbir Aviat Fadila, Atsushi Shirane, Kenichi Okada
IEEE Journal of Solid-State Circuits 2025年6月
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NLJM: A Simplified Jitter Model of Digital Standard Cells for Rapid Automatic Design of Frequency Synthesizers
Yuncheng Zhang
IEEE ACCESS 2025年
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CORDIC-Less Digital Polar Transmitter Architecture Based on Delta-Sigma Modulator
Yuncheng Zhang, Zezheng Liu, Duo Li, Minzhe Tang, Yi Zhang, Hóngyè Huáng, Dingxin Xu, Waleed Madany, Ashbir Aviat Fadila, Wenqian Wang, Yuang Xiong, Daxu Zhang, Garry Pranata Kusuma, Hiroyuki Sakai, Kazuaki Kunihiro, Atsushi Shirane, Kenichi Okada
IEEE Journal of Solid-State Circuits 2025年
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A 0.8--1.4-GHz synthesizable DPLL using a background gain mismatch calibrated feedforward phase noise cancellation
Madany, Waleed, Zhang, Yuncheng, Fadila, Ashbir Aviat, Huang, Hongye, Qiu, Junjun, Mayeda, Jill, Shirane, Atsushi, Okada, Kenichi
IEEE Access 13 40210 - 40225 2025年
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A Multi-Phase Frequency Synthesizer with Injection-Locking Ring Oscillator
ZHANG, DAXU, Zhang, Daxu, Zhang, Yuncheng, HUANG, Hongye, Huang, Hongye, XU, Dingxin, Xu, Dingxin, Shirane, Atsushi, Okada, Kenichi
(No Title) 2024年
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A 7GHz digital PLL with cascaded fractional divider and pseudo-differential DTC achieving-62.1 dBc fractional spur and 143.7 fs integrated jitter
XU, Dingxin, Xu, Dingxin, LIU, Zezheng, Liu, Zezheng, KUAI, Yifeng, Kuai, Yifeng, HUANG, Hongye, Huang, Hongye, Zhang, Yuncheng, Sun, Zheng, others
(No Title) 2024年
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A time-mode-modulation digital quadrature power amplifier based on 1-bit delta--sigma modulator and hybrid FIR filter
Zhang, Yuncheng, Sun, Zheng, Liu, Bangan, Qiu, Junjun, Xu, Dingxin, Zhang, Yi, Fu, Xi, You, Dongwon, Huang, Hongye, Madany, Waleed, others
IEEE Journal of Solid-State Circuits 59 ( 4 ) 993 - 1005 2024年
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A Compact Class-F LC Oscillator with Multi-resonance Mode for Low Jitter PLL Designs
XIONG, Yuang, Xiong, Yuang, XU, Dingxin, Xu, Dingxin, Zhang, Yuncheng, Shirane, Atsushi, Okada, Kenichi
(No Title) 2024年
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A VCO With Robust Implicit Common-Mode Resonance Against Nonideal Decoupling Network
Yuncheng Zhang
IEEE SOLID-STATE CIRCUITS LETTERS 2024年
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Digital Phase-Locked Loops: Exploring Different Boundaries
Yuncheng Zhang, Dingxin Xu, Kenichi Okada
IEEE Open Journal of the Solid-State Circuits Society 2024年
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Design of synthesizable digital phase locked loops
Zhang, Yuncheng, Okada, Kenichi
IPSJ Transactions on System and LSI Design Methodology 17 44 - 54 2024年
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A Fully Synthesizable Fractional-N MDLL With Energy-Efficient Ring-Oscillator-Based DTC of Large Tuning Range
Yuncheng Zhang
IEEE SOLID-STATE CIRCUITS LETTERS 2024年
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A 6.5-to-8-GHz cascaded dual-fractional-N digital PLL achieving- 52.79-dBc fractional spur with 50-MHz reference
Xu, Dingxin, Zhang, Yuncheng, Huang, Hongye, Sun, Zheng, Liu, Bangan, Fadila, Ashbir Aviat, Qiu, Junjun, Liu, Zezheng, Wang, Wenqian, Xiong, Yuang, others
IEEE Journal of Solid-State Circuits 60 ( 3 ) 1043 - 1055 2024年
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A Nonlinearity Compensation Technique for Digital-to-Time Converter in All-Digital PLLs
LIU, Zezheng, Liu, Zezheng, HUANG, Hongye, Huang, Hongye, Zhang, Yuncheng, Shirane, Atsushi, Okada, Kenichi
(No Title) 2024年
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A Low-Power 256-Element -Band CMOS Phased-Array Receiver With On-Chip Distributed Radiation Sensors for Small Satellite Constellations
Yuncheng Zhang
IEEE JOURNAL OF SOLID-STATE CIRCUITS 2023年12月
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A Fully Synthesizable DPLL with Background Gain Mismatch Calibrated Feedforward Phase Noise Cancellation Path
Yuncheng Zhang
IEEE 49TH EUROPEAN SOLID STATE CIRCUITS CONFERENCE, ESSCIRC 2023 2023年
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A Time-Mode-Modulation Digital Quadrature Power Amplifier Based on 1-bit DSM and Transformer Combined FIR
Zhang, Yuncheng, Sun, Zheng, Liu, Bangan, Qiu, Junjun, XU, Dingxin, Xu, Dingxin, ZHANG, Yi, Zhang, Yi, Fu, Xi, YOU, Dongwon, others
(No Title) 2023年
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A 1-Bit-DSM-Based Digital Polar Power Amplifier Supporting 1024-QAM
Yuncheng Zhang
IEEE SOLID-STATE CIRCUITS LETTERS 5 130 - 133 2022年
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A 0.37 mm 2 Fully-Integrated Wide Dynamic Range Sub-GHz Receiver Front-End without Off-Chip Matching Components
Zhang, Yuncheng, Liu, Bangan, Someya, Teruki, Wu, Rui, Qiu, Junjun, Shirane, Atsushi, Okada, Kenichi
IEICE Transactions on Electronics 105 ( 7 ) 334 - 342 2022年
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A CMOS 24-30-GHz Low-Phase-Variation Variable Gain Amplifier Design for 5G New Radio
Yuncheng Zhang
IEEE SOLID-STATE CIRCUITS LETTERS 5 146 - 149 2022年
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A low-power digital baseband circuit for GMSK demodulation in sub-GHz application
Yuncheng Zhang
IEICE ELECTRONICS EXPRESS 2022年
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A 32-kHz-Reference 2.4-GHz Fractional-N Oversampling PLL With 200-kHz Loop Bandwidth
Yuncheng Zhang
IEEE JOURNAL OF SOLID-STATE CIRCUITS 56 ( 12 ) 3741 - 3755 2021年12月
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A Fully Synthesizable Fractional-N MDLL With Zero-Order Interpolation-Based DTC Nonlinearity Calibration and Two-Step Hybrid Phase Offset Calibration
Yuncheng Zhang
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 68 ( 2 ) 603 - 616 2021年2月
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A CMOS Dual-Polarized Phased-Array Beamformer Utilizing Cross-Polarization Leakage Cancellation for 5G MIMO Systems
Yuncheng Zhang
IEEE JOURNAL OF SOLID-STATE CIRCUITS 2021年
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A 32kHz-Reference 2.4GHz Fractional-N Oversampling PLL with 200kHz Loop Bandwidth
Yuncheng Zhang
2021 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE (ISSCC) 2021年
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A 0.25 mm2 BLE Transmitter with Direct Antenna Interface and 19% System Efficiency Using Duty-Cycled Edge-Timing Calibration
Yuncheng Zhang
ESSCIRC 2021 - IEEE 47TH EUROPEAN SOLID STATE CIRCUITS CONFERENCE (ESSCIRC) 2021年
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A Ka-Band SATCOM Transceiver in 65-nm CMOS With High-Linearity TX and Dual-Channel Wide-Dynamic-Range RX for Terrestrial Terminal
Yun Wang, Dongwon You, Xi Fu, Takeshi Nakamura, Ashbir Aviat Fadila, Teruki Someya, Atsuhiro Kawaguchi, Junjun Qiu, Jian Pang, Kiyoshi Yanagisawa, Bangan Liu, Yuncheng Zhang, Haosheng Zhang, Rui Wu, Shunichiro Masaki, Daisuke Yamazaki, Atsushi Shirane, Kenichi Okada
IEEE Journal of Solid-State Circuits 1 - 1 2021年
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A DSM-based Polar Transmitter with 23.8% System Efficiency
Yuncheng Zhang
2021 26TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC) 2021年
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A 29% PAE 1.5bit-DSM-Based Polar Transmitter with Spur-Mitigated Injection-Locked PLL
Yuncheng Zhang
2020 IEEE SYMPOSIUM ON VLSI CIRCUITS 2020年
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A 28-GHz CMOS Phased-Array Beamformer Supporting Dual-Polarized MIMO with Cross-Polarization Leakage Cancellation
Yuncheng Zhang
2020 IEEE SYMPOSIUM ON VLSI CIRCUITS 2020年
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A 1.5 b-DSM-Based Polar Transmitter Using Standard-Cell-Based Fractional-N Injection-Locked PLL and Class-D Power Amplifier
Zhang, Yuncheng, Liu, Bangan, Shirane, Atsushi, Okada, Kenichi
(No Title) 2020年
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A Fully-Synthesizable Fractional-N Injection-Locked PLL for Digital Clocking with Triangle/Sawtooth Spread-Spectrum Modulation Capability in 5-nm CMOS
Yuncheng Zhang
IEEE SOLID-STATE CIRCUITS LETTERS 3 34 - 37 2020年
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A CMOS Ka-Band SATCOM Transceiver with ACI-Cancellation Enhanced Dual-Channel Low-NF Wide-Dynamic-Range RX and High-Linearity TX
Yuncheng Zhang
2020 IEEE RADIO FREQUENCY INTEGRATED CIRCUITS SYMPOSIUM (RFIC) 2020年
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Millimeter-wave CMOS High-linearity Transmitter for Satellite Communication System
Fu, Xi, Wang, Yun, YOU, Dongwon, You, Dongwon, Nakamura, Takeshi, Fadila, Ashbir Aviat, Kawaguchi, Atsuhiro, Pang, Jian, Jian, Pang, Liu, Bangan, others
(No Title) 2020年
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A 0.4-ps-Jitter −52-dBc-Spur Synthesizable Injection-Locked PLL With Self-Clocked Nonoverlap Update and Slope-Balanced Subsampling BBPD
Yuncheng Zhang
IEEE Solid-State Circuits Letters 2019年1月
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A Fully Synthesizable Symbol Timing Recovery Circuit for Low Power Wireless Receiver
邱俊俊, 劉邦安, 張云程, 染谷晃基, 白根篤史, 岡田健一
電子情報通信学会技術研究報告= IEICE technical report: 信学技報 2019年
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An HDL-described Fully-synthesizable Sub-GHz IoT Transceiver with Ring Oscillator based Frequency Synthesizer and Digital Background EVM Calibration
Yuncheng Zhang
2019 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC) 2019年
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A Fully-synthesizable Ring Oscillator Based Frequency Synthesizer for Sub-GHz IoT Application
Liu, Bangan, Zhang, Yuncheng, Qiu, Junjun, Shirane, Atsushi, Okada, Kenichi
(No Title) ( 507 ) 67 - 71 2019年
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A Low-Power Area Efficient Sub-GHz IoT Receiver without Off-Chip Components
Zhang, Yuncheng, Liu, Bangan, Qiu, Junjun, Someya, Teruki, Shirane, Atsushi, Okada, Kenichi
IEICE Technical Report; IEICE Tech. Rep. 118 ( 507 ) 77 - 80 2019年
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A 1.2 ps-Jitter Fully-Synthesizable Fully-Calibrated Fractional-N Injection-Locked PLL Using True Arbitrary Nonlinearity Calibration Technique
Yuncheng Zhang
2018 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC) 2018年
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A Multibit Delta-Sigma Modulator With Double Noise-Shaped Segmentation
Yuncheng Zhang
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS 62 ( 3 ) 241 - 245 2015年
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Digital Noise-Coupling Technique for Delta-Sigma Modulators With Segmented Quantization
Yuncheng Zhang
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS 61 ( 6 ) 403 - 407 2014年6月
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A General Cascaded Noise-Coupled Architecture for ΔΣ Modulators with Segmented Quantization
Yuncheng Zhang
2014 12TH IEEE INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT) 2014年