WhiteDwarf: 12.24 TFLOPS/W 40 nm Versatile Neural Inference Engine for Ultra-Compact Execution of CNNs and MLPs Through Triple Unstructured Sparsity Exploitation and Triple Model Compression

Yasuyuki Okoshi, Ángel López García-Arias, Jaehoon Yu, Junnnosuke Suzuki, Hikari Otsuka, Thiem Van Chu, Kazushi Kawamura, Daichi Fujiki, Masato Motomura

2024 IEEE Asian Solid-State Circuits Conference (A-SSCC)   1 - 3   2024.11

Classical Thermodynamics-based Parallel Annealing Algorithm for High-speed and Robust Combinatorial Optimization

Kyo Kuroki, Satoru Jimbo, Thiem Van Chu, Masato Motomura, Kazushi Kawamura

Proceedings of the Genetic and Evolutionary Computation Conference   196 - 205   2024.7

ETreeNet: Ensemble Model Fusing Decision Trees and Neural Networks for Small Tabular Data

Tsukasa Yamakura, Kazushi Kawamura, Masato Motomura, Thiem Van Chu

2024 International Joint Conference on Neural Networks (IJCNN)   1 - 8   2024.6

Progressive Variable Precision DNN With Bitwise Ternary Accumulation

Junnosuke Suzuki, Mari Yasunaga, Kazushi Kawamura, Thiem Van Chu, Masato Motomura

2024 IEEE 6th International Conference on AI Circuits and Systems (AICAS)   377 - 381   2024.4

Sparse-Sparse Matrix Multiplication Accelerator on FPGA featuring Distribute-Merge Product Dataflow Reviewed

Yuta Nagahara, Jiale Yan, Kazushi Kawamura, Masato Motomura, Thiem Van Chu

Asia and South Pacific Design Automation Conference (ASP-DAC)   2024.1

An Accurate FPGA-Based ORB Feature Extractor for SLAM with Row-Wise Keypoint Selection Reviewed

Yuki Ichikawa, Akihiro Shioda, Kazushi Kawamura, Thiem Van Chu, Masato Motomura

International Conference on Consumer Electronics (ICCE)   2024.1

Efficient COO to CSR Conversion for Accelerating Sparse Matrix Processing on FPGA Reviewed

Yuta Nagahara, Jiale Yan, Kazushi Kawamura, Masato Motomura, Thiem Van Chu

International Conference on Consumer Electronics (ICCE)   2024.1

Exploration of Hyperdimensional Computing Using Locality-Sensitive Hashing Mechanism on FPGA Reviewed

Masato Watanabe, Shungo Kumazawa, Thiem Van Chu, Kazushi Kawamura, Jaehoon Yu, Masato Motomura

International Conference on Consumer Electronics (ICCE)   2024.1

High Throughput Datapath Design for Vision Permutator FPGA Accelerator Reviewed

Mari Yasunaga, Junnosuke Suzuki, Masato Watanabe, Kazushi Kawamura, Thiem Van Chu, Masato Motomura

International Conference on Consumer Electronics (ICCE)   2024.1

Efficient Stereo Visual Odometry on FPGA Featuring On-Chip Map Management and Pipelined Descriptor-Based Block Matching

Yuki Ichikawa, Kazushi Kawamura, Masato Motomura, Thiem van Chu

IEEE Access   12   171458 - 171471   2024

Toward Improving Ensemble-Based Collaborative Inference at the Edge

Shungo Kumazawa, Jaehoon Yu, Kazushi Kawamura, Thiem Van Chu, Masato Motomura

IEEE Access   12   6926 - 6940   2024

Pianissimo: A Sub-mW Class DNN Accelerator With Progressively Adjustable Bit-Precision

Junnosuke Suzuki, Jaehoon Yu, Mari Yasunaga, Ángel López García-Arias, Yasuyuki Okoshi, Shungo Kumazawa, Kota Ando, Kazushi Kawamura, Thiem Van Chu, Masato Motomura

IEEE Access   12   2057 - 2073   2024

Partial Search in a Frozen Network is Enough to Find a Strong Lottery Ticket.

Hikari Otsuka, Daiki Chijiwa, Ángel López García-Arias, Yasuyuki Okoshi, Kazushi Kawamura, Thiem Van Chu, Daichi Fujiki, Susumu Takeuchi, Masato Motomura

CoRR   abs/2402.14029   2024

A Fully-Parallel Annealing Algorithm with Autonomous Pinning Effect Control for Various Combinatorial Optimization Problems Reviewed

Daiki Okonogi, Satoru Jimbo, Kota Ando, Thiem Van Chu, Jaehoon Yu, Masato Motomura, Kazushi Kawamura

IEICE Transactions on Information and Systems   E106.D ( 12 )   2023.12

A Highly Accurate and Parallel Vision MLP FPGA Accelerator based on FP7/8 SIMD Operations Reviewed

Mari Yasunaga, Junnosuke Suzuki, Masato Watanabe, Kazushi Kawamura, Thiem Van Chu, Jaehoon Yu, Masato Motomura

International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC)   2023.12

Pianissimo: A Sub-mW Class DNN Accelerator with Progressive Bit-by-Bit Datapath Architecture for Adaptive Inference at Edge Reviewed

Junnosuke Suzuki, Jaehoon Yu, Mari Yasunaga, Ángel López García-Arias, Yasuyuki Okoshi, Shungo Kumazawa, Kota Ando, Kazushi Kawamura, Thiem Van Chu, Masato Motomura

Symposium on VLSI Technology and Circuits (VLSI)   2023.6

Decision Forest Training Accelerator Based on Binary Feature Decomposition Reviewed

Thiem Van Chu, Yu Mizutani, Yuta Nagahara, Shungo Kumazawa, Kazushi Kawamura, Jaehoon Yu, Masato Motomura

International Symposium on Field-Programmable Custom Computing Machines (FCCM)   2023.5

Flexibly Controllable Dynamic Cooling Methods for Solid-State Annealing Processors to Improve Combinatorial Optimization Performance Reviewed

Genta Inoue, Daiki Okonogi, Thiem Van Chu, Jaehoon Yu, Masato Motomura, Kazushi Kawamura

Symposium in Low-Power and High-Speed Chips (COOL Chips)   2023.4

Amorphica: 4-Replica 512 Fully Connected Spin 336MHz Metamorphic Annealer with Programmable Optimization Strategy and Compressed-Spin-Transfer Multi-Chip Extension Reviewed

Kazushi Kawamura, Jaehoon Yu, Daiki Okonogi, Satoru Jimbo, Genta Inoue, Akira Hyodo, Ángel López García-Anas, Kota Ando, Bruno Hideki Fukushima-Kimura, Ryota Yasudo, Thiem Van Chu, Masato Motomura

International Solid- State Circuits Conference (ISSCC)   2023.2

An Exploration of State-of-the-Art Automation Frameworks for FPGA-Based DNN Acceleration Reviewed

Fumio Hamanaka, Takashi Odan, Kenji Kise, Thiem Van Chu

IEEE Access   11   5701 - 5713   2023.1

Multicoated and Folded Graph Neural Networks with Strong Lottery Tickets.

Jiale Yan, Hiroaki Ito, Ángel López García-Arias, Yasuyuki Okoshi, Hikari Otsuka, Kazushi Kawamura, Thiem Van Chu, Masato Motomura

CoRR   abs/2312.03236   2023

A Hybrid Integer Encoding Method for Obtaining High-Quality Solutions of Quadratic Knapsack Problems on Solid-State Annealers Reviewed

Satoru JIMBO, Daiki OKONOGI, Kota ANDO, Thiem Van CHU, Jaehoon YU, Masato MOTOMURA, Kazushi KAWAMURA

IEICE Transactions on Information and Systems   E105.D ( 12 )   2019 - 2031   2022.12

APC-SCA: A Fully-Parallel Annealing Algorithm with Autonomous Pinning Effect Control Reviewed

Daiki Okonogi, Satoru Jimbo, Kota Ando, Thiem Van Chu, Jaehoon Yu, Masato Motomura, Kazushi Kawamura

International Parallel and Distributed Processing Symposium Workshops (IPDPSW)   2022.5

Hiddenite: 4K-PE Hidden Network Inference 4D-Tensor Engine Exploiting On-Chip Model Construction Achieving 34.8-to-16.0TOPS/W for CIFAR-100 and ImageNet Reviewed

Kazutoshi Hirose, Jaehoon Yu, Kota Ando, Yasuyuki Okoshi, Angel Lopez Garcia-Arias, Junnosuke Suzuki, Thiem Van Chu, Kazushi Kawamura, Masato Motomura

International Solid- State Circuits Conference (ISSCC)   2022.2

Multicoated Supermasks Enhance Hidden Networks. Reviewed

Yasuyuki Okoshi, Ángel López García-Arias, Kazutoshi Hirose, Kota Ando, Kazushi Kawamura, Thiem Van Chu, Masato Motomura, Jaehoon Yu

International Conference on Machine Learning (ICML)   17045 - 17055   2022

A High-Performance and Flexible FPGA Inference Accelerator for Decision Forests Based on Prior Feature Space Partitioning Reviewed

Thiem Van Chu, Ryuichi Kitajima, Kazushi Kawamura, Jaehoon Yu, Masato Motomura

International Conference on Field-Programmable Technology (FPT)   2021.12

GPU-Based Acceleration of Fully Parallel Annealing Algorithm for Combinatorial Optimization Reviewed

Kazushi Kawamura, Kaisei Okawa, Gregory Gutmann, Thiem Van Chu, Jaehoon Yu, Masato Motomura

International System-on-Chip Conference (SOCC)   2021.9

Edge Inference Engine for Deep & Random Sparse Neural Networks with 4-bit Cartesian-Product MAC Array and Pipelined Activation Aligner Reviewed

Kota Ando, Jaehoon Yu, Kazutoshi Hirose, Hiroki Nakahara, Kazushi Kawamura, Thiem Van Chu, Masato Motomura

Hot Chips   2021.8

ProgressiveNN: Achieving Computational Scalability with Dynamic Bit-Precision Adjustment by MSB-first Accumulative Computation Reviewed

Junnosuke Suzuki, Tomohiro Kaneko, Kota Ando, Kazutoshi Hirose, Kazushi Kawamura, Thiem Van Chu, Masato Motomura, Jaehoon Yu

International Journal of Networking and Computing   11 ( 2 )   338 - 353   2021.7

ExtraFerns: Fully Parallel Ensemble Learning Technique with Random Projection and Non-Greedy yet Minimal Memory Access Training Reviewed

Shungo Kumazawa, Kazushi Kawamura, Thiem Van Chu, Masato Motomura, Jaehoon Yu

International Journal of Networking and Computing   11 ( 2 )   215 - 230   2021.7

ProgressiveNN: Achieving Computational Scalability without Network Alteration by MSB-first Accumulative Computation Reviewed

Junnosuke Suzuki, Kota Ando, Kazutoshi Hirose, Kazushi Kawamura, Thiem Van Chu, Masato Motomura, Jaehoon Yu

International Symposium on Computing and Networking (CANDAR)   2020.11

ExtraFerns: Fully Parallel Ensemble Learning Technique with Non-Greedy yet Minimal Memory Access Training Reviewed

Shungo Kumazawa, Kazushi Kawamura, Thiem Van Chu, Masato Motomura, Jaehoon Yu

International Symposium on Computing and Networking (CANDAR)   2020.11

Dependency-Driven Trace-Based Network-on-Chip Emulation on FPGAs Reviewed

Thiem Van Chu, Kenji Kise, Kiyofumi Tanaka

International Symposium on Field-Programmable Gate Arrays (FPGA)   211 - 221   2020.2

LEF: An Effective Routing Algorithm for Two-Dimensional Meshes Reviewed

Thiem Van Chu, Kenji Kise

IEICE Transactions on Information and Systems   E102-D ( 10 )   1925 - 1941   2019.12

An Effective Architecture for Trace-Driven Emulation of Networks-on-Chip on FPGAs Reviewed

Thiem Van Chu, Kenji Kise

International Conference on Field-Programmable Logic and Applications (FPL)   419 - 426   2018.8

A High-Performance and Cost-Effective Hardware Merge Sorter without Feedback Datapath Reviewed

Makoto Saitoh, Elsayed A. Elsayed, Thiem Van Chu, Susumu Mashimo, Kenji Kise

International Symposium on Field-Programmable Custom Computing Machines (FCCM)   197 - 204   2018.4

Fast and cycle-accurate emulation of large-scale networks-on-chip using a single FPGA Reviewed

Thiem Van Chu, Shimpei Sato, Kenji Kise

ACM Transactions on Reconfigurable Technology and Systems   10 ( 4 )   27:1 - 27:27   2017.12

Enhanced Long Edge First Routing Algorithm and Evaluation in Large-Scale Networks-on-Chip Reviewed

Thiem Van Chu, Myeonggu Kang, Shi FA, Kenji Kise

International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC)   83 - 90   2017.9

High-Performance Hardware Merge Sorter Reviewed

Susumu Mashimo, Thiem Van Chu, Kenji Kise

International Symposium on Field-Programmable Custom Computing Machines (FCCM)   1 - 8   2017.5

Cost-Effective and High-Throughput Merge Network Architecture for the Fastest FPGA Sorting Accelerator Reviewed

Susumu Mashimo, Thiem Van Chu, Kenji Kise

ACM SIGARCH Computer Architecture News - HEART'16   44 ( 4 )   8 - 13   2017.1

A Cost-Effective and Scalable Merge Sorter Tree on FPGAs Reviewed

Takuma Usui, Thiem Van Chu, Kenji Kise

International Symposium on Computing and Networking (CANDAR)   47 - 56   2016.11

The Synchronous vs. Asynchronous NoC Routers: An Apple-to-Apple Comparison between Synchronous and Transition Signaling Asynchronous Designs Reviewed

Masashi Imai, Thiem Van Chu, Kenji Kise, Tomohiro Yoneda

International Symposium on Networks-on-Chip (NOCS)   1 - 8   2016.9

Ultra-Fast NoC Emulation on a Single FPGA Reviewed

Thiem Van Chu, Shimpei Sato, Kenji Kise

International Conference on Field-Programmable Logic and Applications (FPL)   1 - 8   2015.9

Enabling Fast and Accurate Emulation of Large-scale Network on Chip Architectures on a Single FPGA Reviewed

Thiem Van Chu, Shimpei Sato, Kenji Kise

International Symposium on Field-Programmable Custom Computing Machines (FCCM)   60 - 63   2015.5

KNoCEmu: High Speed FPGA Emulator for Kilo-Node Scale NoCs Reviewed

Thiem Van Chu, Shimpei Sato, Kenji Kise

International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC)   215 - 222   2014.9

Ultrasmall: The Smallest MIPS Soft Processor Reviewed

Hiroshi Nakatsuka, Yuichiro Tanaka, Thiem Van Chu, Shinya Takamaeda-Yamazaki, Kenji Kise

International Conference on Field Programmable Logic and Applications (FPL)   1 - 4   2014.9