東京大学   VDEC全国運営協議会委員  

2016   

ISSCC   Technology Direction Subcommittee member  

2016 - 2017   

Symposium on VLSI Circuits   Symposium Chair  

2016 - 2017   

IEEE   JSSC Associate Editor  

2015 - 2019   

Symposium on VLSI Circuits   Program Chair  

2014 - 2015   

電子情報通信学会   集積回路研究会 専門委員  

2013.4 - 2018.3   

電子情報通信学会   リコンフィギャラブル研究会 副委員長  

2013.4 - 2017.3   

Symposium on VLSI Circuits   Short Course Chair  

2012 - 2013   

Exploiting N:M Sparsity in Quantized-Folded ResNets: Signed Multicoat Supermasks and Iterative Pruning-Quantization

Akihiro Shioda, Ángel López García-Arias, Hikari Otsuka, Yuki Ichikawa, Yasuyuki Okoshi, Kazushi Kawamura, Thiem Van Chu, Daichi Fujiki, Masato Motomura

2024 Twelfth International Symposium on Computing and Networking (CANDAR)   224 - 230   2024.11

WhiteDwarf: 12.24 TFLOPS/W 40 nm Versatile Neural Inference Engine for Ultra-Compact Execution of CNNs and MLPs Through Triple Unstructured Sparsity Exploitation and Triple Model Compression

Yasuyuki Okoshi, Ángel López García-Arias, Jaehoon Yu, Junnnosuke Suzuki, Hikari Otsuka, Thiem Van Chu, Kazushi Kawamura, Daichi Fujiki, Masato Motomura

2024 IEEE Asian Solid-State Circuits Conference (A-SSCC)   1 - 3   2024.11

Classical Thermodynamics-based Parallel Annealing Algorithm for High-speed and Robust Combinatorial Optimization

Kyo Kuroki, Satoru Jimbo, Thiem Van Chu, Masato Motomura, Kazushi Kawamura

Proceedings of the Genetic and Evolutionary Computation Conference   196 - 205   2024.7

ETreeNet: Ensemble Model Fusing Decision Trees and Neural Networks for Small Tabular Data

Tsukasa Yamakura, Kazushi Kawamura, Masato Motomura, Thiem Van Chu

2024 International Joint Conference on Neural Networks (IJCNN)   1 - 8   2024.6

Progressive Variable Precision DNN With Bitwise Ternary Accumulation

Junnosuke Suzuki, Mari Yasunaga, Kazushi Kawamura, Thiem Van Chu, Masato Motomura

2024 IEEE 6th International Conference on AI Circuits and Systems (AICAS)   377 - 381   2024.4

Sparse-Sparse Matrix Multiplication Accelerator on FPGA featuring Distribute-Merge Product Dataflow

Yuta Nagahara, Jiale Yan, Kazushi Kawamura, Masato Motomura, Thiem Van Chu

2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC)   785 - 791   2024.1

Efficient Stereo Visual Odometry on FPGA Featuring On-Chip Map Management and Pipelined Descriptor-Based Block Matching

Yuki Ichikawa, Kazushi Kawamura, Masato Motomura, Thiem van Chu

IEEE Access   12   171458 - 171471   2024

A GPU-Based Ising Machine With a Multi-Spin-Flip Capability for Constrained Combinatorial Optimization

Satoru Jimbo, Tatsuhiko Shirai, Nozomu Togawa, Masato Motomura, Kazushi Kawamura

IEEE Access   12   43660 - 43673   2024

Pianissimo: A Sub-mW Class DNN Accelerator With Progressively Adjustable Bit-Precision

Junnosuke Suzuki, Jaehoon Yu, Mari Yasunaga, Ángel López García-Arias, Yasuyuki Okoshi, Shungo Kumazawa, Kota Ando, Kazushi Kawamura, Thiem Van Chu, Masato Motomura

IEEE Access   12   2057 - 2073   2024

Toward Improving Ensemble-Based Collaborative Inference at the Edge

Shungo Kumazawa, Jaehoon Yu, Kazushi Kawamura, Thiem Van Chu, Masato Motomura

IEEE Access   12   6926 - 6940   2024

A Highly Accurate and Parallel Vision MLP FPGA Accelerator based on FP7/8 SIMD Operations

Mari Yasunaga, Junnosuke Suzuki, Masato Watanabe, Kazushi Kawamura, Thiem Van Chu, Jaehoon Yu, Masato Motomura

2023 IEEE 16th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC)   2023.12

A Fully-Parallel Annealing Algorithm with Autonomous Pinning Effect Control for Various Combinatorial Optimization Problems

Daiki OKONOGI, Satoru JIMBO, Kota ANDO, Thiem Van CHU, Jaehoon YU, Masato MOTOMURA, Kazushi KAWAMURA

IEICE Transactions on Information and Systems   E106.D ( 12 )   1969 - 1978   2023.12

Pianissimo: A Sub-mW Class DNN Accelerator with Progressive Bit-by-Bit Datapath Architecture for Adaptive Inference at Edge

Junnosuke Suzuki, Jaehoon Yu, Mari Yasunaga, Ángel López García-Arias, Yasuyuki Okoshi, Shungo Kumazawa, Kota Ando, Kazushi Kawamura, Thiem Van Chu, Masato Motomura

2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)   2023.6

Decision Forest Training Accelerator Based on Binary Feature Decomposition

Thiem Van Chu, Yu Mizutani, Yuta Nagahara, Shungo Kumazawa, Kazushi Kawamura, Jaehoon Yu, Masato Motomura

2023 IEEE 31st Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)   2023.5

Flexibly Controllable Dynamic Cooling Methods for Solid-State Annealing Processors to Improve Combinatorial Optimization Performance

Genta Inoue, Daiki Okonogi, Thiem Van Chu, Jaehoon Yu, Masato Motomura, Kazushi Kawamura

2023 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS)   2023.4

Amorphica: 4-Replica 512 Fully Connected Spin 336MHz Metamorphic Annealer with Programmable Optimization Strategy and Compressed-Spin-Transfer Multi-Chip Extension

Kazushi Kawamura, Jaehoon Yu, Daiki Okonogi, Satoru Jimbo, Genta Inoue, Akira Hyodo, Ángel López García-Anas, Kota Ando, Bruno Hideki Fukushima-Kimura, Ryota Yasudo, Thiem Van Chu, Masato Motomura

2023 IEEE International Solid- State Circuits Conference (ISSCC)   2023.2

Multicoated and Folded Graph Neural Networks with Strong Lottery Tickets.

Jiale Yan, Hiroaki Ito, Ángel López García-Arias, Yasuyuki Okoshi, Hikari Otsuka, Kazushi Kawamura, Thiem Van Chu, Masato Motomura

CoRR   abs/2312.03236   2023

Recurrent Residual Networks Contain Stronger Lottery Tickets

Ángel López García-Arias, Yasuyuki Okoshi, Masanori Hashimoto, Masato Motomura, Jaehoon Yu

IEEE Access   11   16588 - 16604   2023

A Hybrid Integer Encoding Method for Obtaining High-Quality Solutions of Quadratic Knapsack Problems on Solid-State Annealers

Satoru JIMBO, Daiki OKONOGI, Kota ANDO, Thiem Van CHU, Jaehoon YU, Masato MOTOMURA, Kazushi KAWAMURA

IEICE Transactions on Information and Systems   E105.D ( 12 )   2019 - 2031   2022.12

APC-SCA: A Fully-Parallel Annealing Algorithm with Autonomous Pinning Effect Control

Daiki Okonogi, Satoru Jimbo, Kota Ando, Thiem Van Chu, Jaehoon Yu, Masato Motomura, Kazushi Kawamura

2022 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)   2022.5

Hiddenite: 4K-PE Hidden Network Inference 4D-Tensor Engine Exploiting On-Chip Model Construction Achieving 34.8-to-16.0TOPS/W for CIFAR-100 and ImageNet

Kazutoshi Hirose, Jaehoon Yu, Kota Ando, Yasuyuki Okoshi, Angel Lopez Garcia-Arias, Junnosuke Suzuki, Thiem Van Chu, Kazushi Kawamura, Masato Motomura

2022 IEEE International Solid- State Circuits Conference (ISSCC)   2022.2

Multicoated Supermasks Enhance Hidden Networks.

Yasuyuki Okoshi, Ángel López García-Arias, Kazutoshi Hirose, Kota Ando, Kazushi Kawamura, Thiem Van Chu, Masato Motomura, Jaehoon Yu

ICML   17045 - 17055   2022

A High-Performance and Flexible FPGA Inference Accelerator for Decision Forests Based on Prior Feature Space Partitioning

Thiem Van Chu, Ryuichi Kitajima, Kazushi Kawamura, Jaehoon Yu, Masato Motomura

2021 International Conference on Field-Programmable Technology (ICFPT)   2021.12

Edge Inference Engine for Deep & Random Sparse Neural Networks with 4-bit Cartesian-Product MAC Array and Pipelined Activation Aligner

Kota Ando, Jaehoon Yu, Kazutoshi Hirose, Hiroki Nakahara, Kazushi Kawamura, Thiem Van Chu, Masato Motomura

2021 IEEE Hot Chips 33 Symposium (HCS)   2021.8

A 96-MB 3D-Stacked SRAM Using Inductive Coupling With 0.4-V Transmitter, Termination Scheme and 12:1 SerDes in 40-nm CMOS

Kota Shiba, Tatsuo Omori, Kodai Ueyoshi, Shinya Takamaeda-Yamazaki, Masato Motomura, Mototsugu Hamada, Tadahiro Kuroda

IEEE Transactions on Circuits and Systems I: Regular Papers   68 ( 2 )   692 - 703   2021.2

Selective Fine-Tuning on a Classifier Ensemble: Realizing Adaptive Neural Networks With a Diversified Multi-Exit Architecture

Kazutoshi Hirose, Shinya Takamaeda-Yamazaki, Jaehoon Yu, Masato Motomura

IEEE Access   9   6179 - 6187   2021

Hidden-Fold Networks: Random Recurrent Residuals Using Sparse Supermasks.

Ángel López García-Arias, Masanori Hashimoto, Masato Motomura, Jaehoon Yu

BMVC   205 - 205   2021

ProgressiveNN: Achieving Computational Scalability with Dynamic Bit-Precision Adjustment by MSB-first Accumulative Computation

Junnosuke Suzuki, Tomohiro Kaneko, Kota Ando, Kazutoshi Hirose, Kazushi Kawamura, Thiem Van Chu, Masato Motomura, Jaehoon Yu

International Journal of Networking and Computing   11 ( 2 )   338 - 353   2021

ExtraFerns: Fully Parallel Ensemble Learning Technique with Random Projection and Non-Greedy yet Minimal Memory Access Training

Shungo Kumazawa, Kazushi Kawamura, Thiem Van Chu, Masato Motomura, Jaehoon Yu

International Journal of Networking and Computing   11 ( 2 )   215 - 230   2021

Real-time tone mapping: a survey and cross-implementation hardware benchmark

Yafei Ou, Prasoon Ambalathankandy, Shinya Takamaeda, Masato Motomura, Tetsuya Asai, Masayuki Ikebe

IEEE Transactions on Circuits and Systems for Video Technology   1 - 1   2021

ExtraFerns: Fully Parallel Ensemble Learning Technique with Non-Greedy yet Minimal Memory Access Training

Shungo Kumazawa, Kazushi Kawamura, Thiem Van Chu, Masato Motomura, Jaehoon Yu

2020 Eighth International Symposium on Computing and Networking (CANDAR)   2020.11

ProgressiveNN: Achieving Computational Scalability without Network Alteration by MSB-first Accumulative Computation

Junnosuke Suzuki, Kota Ando, Kazutoshi Hirose, Kazushi Kawamura, Thiem Van Chu, Masato Motomura, Jaehoon Yu

2020 Eighth International Symposium on Computing and Networking (CANDAR)   2020.11

A 3D-Stacked SRAM using Inductive Coupling with Low-Voltage Transmitter and 12:1 SerDes

Kota Shiba, Tatsuo Omori, Kodai Ueyoshi, Kota Ando, Kazutoshi Hirose, Shinya Takamaeda-Yamazaki, Masato Motomura, Mototsugu Hamada, Tadahiro Kuroda

2020 IEEE International Symposium on Circuits and Systems (ISCAS)   2020.10

Real-time Tone Mapping: A State of the Art Report

Yafei Ou, Prasoon Ambalathankandy, Masayuki Ikebe, Shinya Takamaeda, Masato Motomura, Tetsuya Asai

2020.3

Hardware/Algorithm Co-optimization for Fully-Parallelized Compact Decision Tree Ensembles on FPGAs. Reviewed

Taiga Ikeda, Kento Sakurada, Atsuyoshi Nakamura, Masato Motomura, Shinya Takamaeda-Yamazaki

Applied Reconfigurable Computing. Architectures, Tools, and Applications - 16th International Symposium(ARC)   345 - 357   2020

7.3 STATICA: A 512-Spin 0.25M-Weight Full-Digital Annealing Processor with a Near-Memory All-Spin-Updates-at-Once Architecture for Combinatorial Optimization with Complete Spin-Spin Interactions. Reviewed

Kasho Yamamoto, Kota Ando, Normann Mertig, Takashi Takemoto, Masanao Yamaoka, Hiroshi Teramoto, Akira Sakai, Shinya Takamaeda-Yamazaki, Masato Motomura

2020 IEEE International Solid- State Circuits Conference(ISSCC)   138 - 140   2020

A hardware-efficient weight sampling circuit for Bayesian neural networks Reviewed

Hirayama Y., Asai T., Motomura M., Takamaeda-Yamazaki S.

International Journal of Networking and Computing   10   2020

STATICA: A 512-Spin 0.25M-Weight Annealing Processor With an All-Spin-Updates-at-Once Architecture for Combinatorial Optimization With Complete Spin-Spin Interactions

Kasho Yamamoto, Kazushi Kawamura, Kota Ando, Normann Mertig, Takashi Takemoto, Masanao Yamaoka, Hiroshi Teramoto, Akira Sakai, Shinya Takamaeda-Yamazaki, Masato Motomura

IEEE Journal of Solid-State Circuits   56 ( 1 )   1 - 1   2020

An Adaptive Global and Local Tone Mapping Algorithm Implemented on FPGA.

Prasoon Ambalathankandy, Masayuki Ikebe, Takayuki Yoshida, Takeshi Shimada, Shinya Takamaeda, Masato Motomura, Tetsuya Asai

IEEE Transactions on Circuits and Systems for Video Technology   30 ( 9 )   3015 - 3028   2020

FPGA-based annealing processor with time-division multiplexing Reviewed

Yamamoto K., Ikebe M., Asai T., Motomura M., Takamaeda-Yamazaki S.

IEICE Transactions on Information and Systems   E102-D ( 12 )   2295 - 2305   2019.12

Dither NN: hardware/algorithm co-design for accurate quantized neural networks Reviewed

Ando K., Ueyoshi K., Oba Y., Hirose K., Uematsu R., Kudo T., Ikebe M., Asai T., Takamaeda-Yamazaki S., Motomura M.

IEICE Transactions on Information and Systems   E102 ( 12 )   2341 - 2353   2019.12

A Resource-Efficient Weight Sampling Method for Bayesian Neural Network Accelerators

Yuki Hirayama, Tetsuya Asai, Masato Motomura, Shinya Takamaeda-Yamazaki

Proceedings - 2019 7th International Symposium on Computing and Networking, CANDAR 2019   137 - 142   2019.11

A study on a low power optimization algorithm for an edge-AI Device Reviewed

Kaneko T., Orimo K., Hida I., Takamaeda-Yamazaki S., Ikebe M., Motomura M., Asai T.

Nonlinear Theory and Its Applications   E10-N ( 4 )   373 - 389   2019.10

Hardware-oriented algorithm and architecture for generative adversarial networks Reviewed

Kaneko T., Ikebe M., Takamaeda-Yamazaki S., Motomura M., Asai T.

Journal of Signal Processing   23 ( 4 )   151 - 154   2019.7

DeltaNet: Differential binary neural network

Yuka Oba, Kota Ando, Tetsuya Asai, Masato Motomura, Shinya Takamaeda-Yamazaki

Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors   2019-   39   2019.7

QUEST: Multi-Purpose Log-Quantized DNN Inference Engine Stacked on 96-MB 3-D SRAM Using Inductive Coupling Technology in 40-nm CMOS

Kodai Ueyoshi, Kota Ando, Kazutoshi Hirose, Shinya Takamaeda-Yamazaki, Mototsugu Hamada, Tadahiro Kuroda, Masato Motomura

IEEE Journal of Solid-State Circuits   54 ( 1 )   186 - 196   2019.1

Radiography Contrast Enhancement: Smoothed LHE Filter a Practical Solution for Digital X-Rays with Mach Band.

Prasoon Ambalathankandy, Yafei Ou, Jyotsna Kochiyil, Shinya Takamaeda, Masato Motomura, Tetsuya Asai, Masayuki Ikebe

2019 Digital Image Computing: Techniques and Applications(DICTA)   1 - 8   2019

Real-time HDTV to 4K and 8K-UHD conversions using anti-aliasing based super resolution algorithm on FPGA Reviewed

Ambalathankandy P, Takamaeda-Yamazaki S, Motomura M, Asai T, Ikebe M, Kusano H

Microprocessors and Microsystems   60   21 - 31   2018.12

Quantization error-based regularization for hardware-aware neural network training Reviewed

Hirose K, Uematsu R, Ando K, Ueyoshi K, Ikebe M, Asai T, Motomura M, Takamaeda-Yamazaki S

Nonlinear Theory and Its Applications   E9-N ( 4 )   453 - 465   2018.10

BRein Memory: A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W Reviewed

Kota Ando, Kodai Ueyoshi, Kentaro Orimo, Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Tetsuya Asai, Tadahiro Kuroda, Masato Motomura

IEEE Journal of Solid-State Circuits   53 ( 4 )   983 - 994   2018.4

Proto-computing architecture over a digital medium aiming at real-time video processing Reviewed

Tanibata A, Schmid A, Takamaeda-Yamazaki S, Ikebe M, Motomura M, Asai T

Complexity   2018   3618621-1 - 11   2018.2

New Generation Dynamically Reconfigurable Processor Technology for Accelerating Embedded AI Applications. Reviewed

Taro Fujii, Takao Toi, Teruhito Tanaka, Katsumi Togawa, Toshiro Kitaoka, Kengo Nishino, Noritsugu Nakamura, Hiroki Nakahara, Masato Motomura

2018 IEEE Symposium on VLSI Circuits, Honolulu, HI, USA, June 18-22, 2018   41 - 42   2018

Analysis of Smoothed LHE Methods for Processing Images with Optical Illusions.

Prasoon Ambalathankandy, Takeshi Shimada, Shinya Takamaeda, Masato Motomura, Tetsuya Asai, Masayuki Ikebe

IEEE Visual Communications and Image Processing(VCIP)   1 - 4   2018

Sparse Disparity Estimation Using Global Phase Only Correlation for Stereo Matching Acceleration.

Takeshi Shimada, Masayuki Ikebe, Prasoon Ambalathankandy, Shinya Takamaeda-Yamazaki, Masato Motomura, Tetsuya Asai

2018 IEEE International Conference on Acoustics, Speech and Signal Processing(ICASSP)   1842 - 1846   2018

Area and Energy Optimization for Bit-Serial Log-Quantized DNN Accelerator with Shared Accumulators.

Takumi Kudo, Kodai Ueyoshi, Kota Ando, Kazutoshi Hirose, Ryota Uematsu, Yuka Oba, Masayuki Ikebe, Tetsuya Asai, Masato Motomura, Shinya Takamaeda-Yamazaki

12th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip(MCSoC)   237 - 243   2018

QUEST: A 7.49TOPS Multi-Purpose Log-Quantized DNN Inference Engine Stacked on 96MB 3D SRAM Using Inductive-Coupling Technology in 40nm CMOS Reviewed

Kodai Ueyoshi, Kota Ando, Kazutoshi Hirose, Shinya Takamaeda-Yamazaki, Junichiro Kadomoto, Tomoki Miyata, Mototsugu Hamada, Tadahiro Kuroda, Masato Motomura

2018 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE - (ISSCC)   216 - +   2018

Dither NN: An Accurate Neural Network with Dithering for Low Bit-Precision Hardware.

Kota Ando, Kodai Ueyoshi, Yuka Oba, Kazutoshi Hirose, Ryota Uematsu, Takumi Kudo, Masayuki Ikebe, Tetsuya Asai, Shinya Takamaeda-Yamazaki, Masato Motomura

International Conference on Field-Programmable Technology(FPT)   6 - 13   2018

Live demonstration: Feature extraction system using restricted Boltzmann machines on FPGA Reviewed

Kodai Ueyoshi, Takao Marukame, Tetsuya Asai, Masato Motomura, Alexandre Schmid

Proceedings - IEEE International Symposium on Circuits and Systems   2017.9

6-DoF camera position and posture estimation based on local patches of image sequence Reviewed

Tsuji T, Ikebe M, Takamaeda-Yamazaki S, Motomura M, Asai T

Journal of Signal Processing   21 ( 4 )   191 - 194   2017.7

A multithreaded CGRA for convolutional neural network processing Reviewed

Ando K, Takamaeda-Yamazaki S, Ikebe M, Asai T, Motomura M

Circuits and Systems   8 ( 6 )   149 - 170   2017.6

A high performance and energy efficient microprocessor with a novel restricted dynamically reconfigurable accelerator Reviewed

Hida I, Takamaeda-Yamazaki S, Ikebe M, Motomura M, Asai T

Circuits and Systems   8 ( 5 )   134 - 147   2017.5

An energy-efficient dynamic branch predictor with a two-clock-cycle naive Bayes classifier for pipelined RISC microprocessors Reviewed

Hida I, Takamaeda-Yamazaki S, Ikebe M, Motomura M, Asai T

Nonlinear Theory and Its Applications   E8-N ( 3 )   235 - 245   2017.5

Error Tolerance Analysis of Deep Learning Hardware Using a Restricted Boltzmann Machine Toward Low-Power Memory Implementation Reviewed

Takao Marukame, Kodai Ueyoshi, Tetsuya Asai, Masato Motomura, Alexandre Schmid, Masamichi Suzuki, Yusuke Higashi, Yuichiro Mitani

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS   64 ( 4 )   462 - 466   2017.4

Low Latency Divider using Ensemble of Moving Average Curves Reviewed

Yuhan Fu, Masayuki Ikebe, Takeshi Shimada, Tetsuya Asai, Masato Motomura

PROCEEDINGS OF THE EIGHTEENTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED)   397 - 402   2017

In-memory area-efficient signal streaming processor design for binary neural networks.

Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara, Kota Ando, Kodai Ueyoshi, Kazutoshi Hirose, Kentaro Orimo, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Tetsuya Asai, Masato Motomura

IEEE 60th International Midwest Symposium on Circuits and Systems(MWSCAS)   116 - 119   2017

Quantization Error-Based Regularization in Neural Networks.

Kazutoshi Hirose, Kota Ando, Kodai Ueyoshi, Masayuki Ikebe, Tetsuya Asai, Masato Motomura, Shinya Takamaeda-Yamazaki

Artificial Intelligence XXXIV - 37th SGAI International Conference on Artificial Intelligence   137 - 142   2017

Logarithmic Compression for Memory Footprint Reduction in Neural Network Training.

Kazutoshi Hirose, Ryota Uematsu, Kota Ando, Kentaro Orimo, Kodai Ueyoshi, Masayuki Ikebe, Tetsuya Asai, Shinya Takamaeda-Yamazaki, Masato Motomura

Fifth International Symposium on Computing and Networking(CANDAR)   291 - 297   2017

Exploring optimized accelerator design for binarized convolutional neural networks.

Kodai Ueyoshi, Kota Ando, Kentaro Orimo, Masayuki Ikebe, Tetsuya Asai, Masato Motomura

2017 International Joint Conference on Neural Networks(IJCNN)   2510 - 2516   2017

FPGA implementation of edge-guided pattern generation for motion-vector estimation of textureless objects.

Aoi Tanibata, Alexandre Schmid, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Masato Motomura, Tetsuya Asai

27th International Conference on Field Programmable Logic and Applications(FPL)   1 - 1   2017

A Time-Division Multiplexing Ising Machine on FPGAs.

Kasho Yamamoto, Weiqiang Huang, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Tetsuya Asai, Masato Motomura

Proceedings of the 8th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies(HEART)   3 - 6   2017

An FPGA Realization of a Deep Convolutional Neural Network Using a Threshold Neuron Pruning. Reviewed

Tomoya Fujii, Simpei Sato, Hiroki Nakahara, Masato Motomura

Applied Reconfigurable Computing - 13th International Symposium, ARC 2017, Delft, The Netherlands, April 3-7, 2017, Proceedings   268 - 280   2017

A Batch Normalization Free Binarized Convolutional Deep Neural Network on an FPGA (Abstract Only). Reviewed

Hiroki Nakahara, Haruyoshi Yonekawa, Hisashi Iwamoto, Masato Motomura

Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA 2017, Monterey, CA, USA, February 22-24, 2017   290   2017

Accelerating deep learning by binarized hardware.

Shinya Takamaeda-Yamazaki, Kodai Ueyoshi, Kota Ando, Ryota Uematsu, Kazutoshi Hirose, Masayuki Ikebe, Tetsuya Asai, Masato Motomura

2017 Asia-Pacific Signal and Information Processing Association Annual Summit and Conference(APSIPA)   1045 - 1051   2017

An Image Sensor/Processor 3D Stacked Module featuring ThruChip Interfaces Reviewed

Masayuki Ikebe, Tetsuya Asai, Masafumi Mori, Toshiyuki Itou, Daisuke Uchida, Yasuhiro Take, Tadahiro Kuroda, Masato Motomura

2017 22ND ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC)   7 - 8   2017

FPGA-based stream processing for frequent itemset mining with incremental multiple hashes Reviewed

Yamamoto K, Ikebe M, Asai T, Motomura M

Circuits and Systems   7 ( 10 )   3299 - 3309   2016.8

Memory-error tolerance of scalable and highly parallel architecture for restricted Boltzmann machines in Deep Belief Network Reviewed

Kodai Ueyoshi, Takao Marukame, Tetsuya Asai, Masato Motomura, Alexandre Schmid

Proceedings - IEEE International Symposium on Circuits and Systems   2016-   357 - 360   2016.7

FPGA implementation of a scalable and highly parallel architecture for restricted Boltzmann machines Reviewed

Ueyoshi K, Marukame T, Asai T, Motomura M, Schmid A

Circuits and Systems   7 ( 9 )   2132 - 2141   2016.7

Robustness of hardware-oriented restricted Boltzmann machines in deep belief networks for reliable processing Reviewed

Ueyoshi K, Marukame T, Asai T, Motomura M, Schmid A

Nonlinear Theory and Its Applications   E7-N ( 3 )   395 - 406   2016.7

Stochastic resonance induced by internal noise in a unidirectional network of excitable FitzHugh-Nagumo neurons Reviewed

Ishimura K, Schmid A, Asai T, Motomura M

Nonlinear Theory and Its Applications   7 ( 2 )   164 - 175   2016.4

Memory-error tolerance of Scalable and Highly Parallel Architecture for Restricted Boltzmann Machines in Deep Belief Network Reviewed

Kodai Ueyoshi, Takao Marukame, Tetsuya Asai, Masato Motomura, Alexandre Schmid

2016 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)   357 - 360   2016

An FPGA-Optimized Architecture of Anti-Aliasing based Super Resolution for Real-Time HDTV to 4K-and 8K-UHD Conversions Reviewed

Hotaka Kusano, Masayuki Ikebe, Tetsuya Asai, Masato Motomura

2016 INTERNATIONAL CONFERENCE ON RECONFIGURABLE COMPUTING AND FPGAS (RECONFIG16)   2016

FPGA Architecture for Feed-Forward Sequential Memory Network targeting Long-Term Time-Series Forecasting Reviewed

Kentaro Orimo, Kota Ando, Kodai Ueyoshi, Masayuki Ikebe, Tetsuya Asai, Masato Motomura

2016 INTERNATIONAL CONFERENCE ON RECONFIGURABLE COMPUTING AND FPGAS (RECONFIG16)   2016

A 2-Clock-Cycle Naive Bayes Classifier for Dynamic Branch Prediction in Pipelined RISC Microprocessors Reviewed

Itaru Hida, Masayuki Ikebe, Tetsuya Asai, Masato Motomura

2016 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS)   297 - 300   2016

Motion-Vector Estimation and Cognitive Classification on an Image Sensor/Processor 3D Stacked System featuring ThruChip Interfaces Reviewed

Tetsuya Asai, Masafumi Mori, Toshiyuki Itou, Yasuhiro Take, Masayuki Ikebe, Tadahiro Kuroda, Masato Motomura

ESSCIRC CONFERENCE 2016   105 - 108   2016

3D stacked imager featuring inductive coupling channels for high speed/low-noise image transfer Reviewed

Masayuki Ikebe, Daisuke Uchida, Yasuhiro Take, Makito Someya, Satoshi Chikuda, Kento Matsuyama, Tetsuya Asai, Tadahiro Kuroda, Masato Motomura

ITE Transactions on Media Technology and Applications   4 ( 2 )   142 - 148   2016

A Memory-Based Realization of a Binarized Deep Convolutional Neural Network Reviewed

Hiroki Nakahara, Haruyoshi Yonekawa, Tsutomu Sasao, Hisashi Iwamoto, Masato Motomura

2016 INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE TECHNOLOGY (FPT)   277 - 280   2016

Motion Vector Estimation of Textureless Objects Exploiting Reaction-Diffusion Cellular Automata Reviewed

Miho Ushida, Alexandre Schmid, Tetsuya Asai, Kazuyoshi Ishimura, Masato Motomura

INTERNATIONAL JOURNAL OF UNCONVENTIONAL COMPUTING   12 ( 2-3 )   169 - 187   2016

Crosstalk Rejection in 3-D-Stacked Interchip Communication With Blind Source Separation Reviewed

Kamal El-Sankary, Tetsuya Asai, Masato Motomura, Tadahiro Kuroda

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS   62 ( 8 )   726 - 730   2015.8

FPGA implementation of hardware-oriented reaction-diffusion cellular automata models Reviewed

Ishimura K, Komuro K, Schmid A, Asai T, Motomura M

Nonlinear Theory and Its Applications   6 ( 2 )   252 - 262   2015.4

Through Chip Interface Based Three-Dimensional FPGA Architecture Exploration Reviewed

Li-Chung Hsu, Masato Motomura, Yasuhiro Take, Tadahiro Kuroda

IEICE TRANSACTIONS ON ELECTRONICS   E98C ( 4 )   288 - 297   2015.4

3D Stacked Imager featuring Inductive Coupling Channels for High Speed/Low-Noise Image Transfer

IKEBE Masayuki, UCHIDA Daisuke, TAKE Yasuhiro, SOMEYA Makito, CHIKUDA Satoshi, MATSUYAMA Kento, ASAI Tetsuya, KURODA Tadahiro, MOTOMURA Masato

ITE Technical Report   39   17 - 20   2015

Enhancing memcached by caching its data and functionalities at network interface Reviewed

Eric S. Fukuda, Hiroaki Inoue, Takashi Takenaka, Dahoo Kim, Tsunaki Sadahisa, Tetsuya Asai, Masato Motomura

Journal of Information Processing   23 ( 2 )   143 - 152   2015

Image Sensor/Digital Logic 3D Stacked Module featuring Inductive Coupling Channels for High Speed/Low-Noise Image Transfer Reviewed

Masayuki Ikebe, Daisuke Uchida, Yasuhiro Take, Makito Someya, Satoshi Chikuda, Kento Matsuyama, Tetsuya Asai, Tadahiro Kuroda, Masato Motomura

2015 SYMPOSIUM ON VLSI CIRCUITS (VLSI CIRCUITS)   2015

Reducing power and energy consumption of nonvolatile microcontrollers with transparent on-chip instruction cache Reviewed

Kim D, Hida I, Fukuda E.S, Asai T, Motomura M

Circuits and Systems   5 ( 11 )   253 - 264   2014.10

Caching memcached at reconfigurable network interface

Eric S. Fukuda, Hiroaki Inoue, Takashi Takenaka, Dahoo Kim, Tsunaki Sadahisa, Tetsuya Asai, Masato Motomura

Conference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014   2014.10

Image steganography based on reaction diffusion models toward hardware implementation Reviewed

Ishimura K, Komuro K, Schmid A, Asai T, Motomura M

Nonlinear Theory and Its Applications   5 ( 4 )   456 - 465   2014.10

Application of nonlinear systems for designing low-power logic gates based on stochastic resonance Reviewed

Gonzalez-Carabarin L, Asai T, Motomura M

Nonlinear Theory and Its Applications   5 ( 4 )   445 - 455   2014.10

FPGA-based design for motion-vector estimation exploiting high-speed imaging and its application to motion classification with neural networks Reviewed

Mori M, Itou T, Ikebe M, Asai T, Kuroda T, Motomura M

Journal of Signal Processing   18 ( 4 )   165 - 168   2014.7

Achieving Higher Performance of Memcached by Caching at Network Interface Reviewed

Eric S. Fukuda, Hiroaki Inoue, Takashi Takenaka, Dahoo Kim, Tsunaki Sadahisa, Tetsuya Asai, Masato Motomura

PROCEEDINGS OF THE 2014 INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE TECHNOLOGY (FPT)   288 - 289   2014

A 4.5 to 13 Times Energy-Efficient Embedded Microprocessor with Mainly-Static/Partially-Dynamic Reconfigurable Array Accelerator Reviewed

Itaru Hida, Dahoo Kim, Tetsuya Asai, Masato Motomura

2014 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC)   37 - 40   2014

Low-power asynchronous digital pipeline based on mismatch-tolerant logic gates Reviewed

Gonzalez-Carabarin Lizeth, Tetsuya Asai, Masato Motomura

IEICE ELECTRONICS EXPRESS   11 ( 15 )   20140632/1 - 9   2014

Chaotic resonance in forced Chua's oscillators Reviewed

Ishimura K, Asai T, Motomura M

Journal of Signal Processing   17 ( 6 )   231 - 238   2013.11

Hardware design for C-based complex event processing Reviewed

Hiroaki Inoue, Takashi Takenaka, Masato Motomura

Embedded Systems Design with FPGAs   9781461413622   79 - 100   2013.11

C-Based Complex Event Processing on Reconfigurable Hardware Reviewed

Hiroaki Inoue, Takashi Takenaka, Masato Motomura

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS   21 ( 5 )   971 - 974   2013.5

C-based design of window join for dynamically reconfigurable hardware Reviewed

Fukuda E.S, Kawashima H, Inoue H, Asai T, Motomura M

Journal of Computer Science and Engineering   20 ( 2 )   1 - 9   2013

FPGA implementation of single-image super resolution based on frame-bufferless box filtering Reviewed

Sanada Y, Ohira T, Chikuda S, Igarashi M, Ikebe M, Asai T, Motomura M

Journal of Signal Processing   17 ( 4 )   111 - 114   2013

C-Based Adaptive Stream Processing on Dynamically Reconfigurable Hardware: A Case Study on Window Join Reviewed

Eric Shun Fukuda, Hideyuki Kawashima, Hiroaki Inoue, Taro Fujii, Koichiro Furuta, Tetsuya Asai, Masato Motomura

RECONFIGURABLE COMPUTING: ARCHITECTURES, TOOLS AND APPLICATIONS   7806   220 - 220   2013

Hardware-Oriented Stereo Vision Algorithm based on 1-D Guided Filtering and its FPGA Implementation. Reviewed

Katsuki Ohata, Yuki Sanada, Tetsuro Ogaki, Kento Matsuyama, Takanori Ohira, Satoshi Chikuda, Masaki Igarashi, Masayuki Ikebe, Tetsuya Asai, Masato Motomura, Tadahiro Kuroda

2013 IEEE 20TH INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS, AND SYSTEMS (ICECS)   169 - 172   2013

A Restricted Dynamically Reconfigurable Architecture for Low Power Processors Reviewed

Takeshi Hirao, Dahoo Kim, Itaru Hida, Tetsuya Asai, Masato Motomura

2013 INTERNATIONAL CONFERENCE ON RECONFIGURABLE COMPUTING AND FPGAS (RECONFIG)   2013

Excitable reaction-diffusion media with memristors Reviewed

Gong X, Asai T, Motomura M

Journal of Signal Processing   16 ( 4 )   283 - 286   2012

Noise-induced phase synchronization among simple digital counters Reviewed

Matsuura M, Asai T, Motomura M

Journal of Signal Processing   16 ( 4 )   279 - 282   2012

Reaction-Diffusion Media with Excitable Oregonators Coupled by Memristors Reviewed

Xiyuan Gong, Tetsuya Asai, Masato Motomura

2012 13TH INTERNATIONAL WORKSHOP ON CELLULAR NANOSCALE NETWORKS AND THEIR APPLICATIONS (CNNA)   2012

Impact of noise on spike transmission through serially-connected electrical FitzHugh-Nagumo circuits with subthreshold and suprathreshold interconductances Reviewed

Gonzalez-Carabarin L, Asai T, Motomura M

Journal of Signal Processing   16 ( 6 )   503 - 509   2012

Test Compression for Dynamically Reconfigurable Processors Reviewed

Hiroaki Inoue, Junya Yamada, Hideyuki Yoneda, Katsumi Togawa, Masato Motomura, Koichiro Furuta

ACM TRANSACTIONS ON RECONFIGURABLE TECHNOLOGY AND SYSTEMS   4 ( 4 )   40:01:00 - 15   2011.12

20Gbps C-based complex event processing Reviewed

Hiroaki Inoue, Takashi Takenaka, Masato Motomura

Proceedings - 21st International Conference on Field Programmable Logic and Applications, FPL 2011   97 - 102   2011

Time and Space-multiplexed Compilation Challenges for Dynamically Reconfigurable Processors Reviewed

Takao Toi, Toru Awashima, Masato Motomura, Hideharu Amano

2011 IEEE 54TH INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS)   2011

Spatial-temporal mapping of real applications on a dynamically reconfigurable logic engine (DRLE) LSI

Koichiro Furuta, Taro Fujii, Masato Motomura, Kazutoshi Wakabayashi, Msakazu Yamashina

Proceedings of the Custom Integrated Circuits Conference   151 - 154   2000

Quantization Error-aware Neural Network Training

104   1 - 4   2017.8

依頼講演 BRein Memory : バイナリ・インメモリ再構成型深層ニューラルネットワークアクセラレータ (集積回路)

安藤 洸太, 植吉 晃大, 折茂 健太郎, 米川 晴義, 佐藤 真平, 中原 啓貴, 池辺 将之, 浅井 哲也, 高前田 伸也, 黒田 忠広, 本村 真人

電子情報通信学会技術研究報告 = IEICE technical report : 信学技報   117 ( 167 )   101 - 106   2017.7

SOI image sensor for ion flight time measurement using thermal noise suppressing sample hold circuit

117 ( 166 )   35 - 38   2017.7

Time variation reduction of shoot-through current for TDC + Single-Slope ADC architecture

117 ( 166 )   27 - 30   2017.7

高次数イジングネットワークの時分割処理方式の検討 (コンピュータシステム)

山本 佳生, 熊澤 輝顕, 池辺 将之, 浅井 哲也, 本村 真人, 高前田 伸也

電子情報通信学会技術研究報告 = IEICE technical report : 信学技報   117 ( 153 )   83 - 88   2017.7

依頼講演 BRein Memory : バイナリ・インメモリ再構成型深層ニューラルネットワークアクセラレータ (情報センシング)

安藤 洸太, 植吉 晃大, 折茂 健太郎, 米川 晴義, 佐藤 真平, 中原 啓貴, 池辺 将之, 浅井 哲也, 高前田 伸也, 黒田 忠広, 本村 真人

映像情報メディア学会技術報告 = ITE technical report   41 ( 25 )   101 - 106   2017.7

Time variation reduction of shoot-through current for TDC+Single-Slope ADC architecture

41 ( 25 )   27 - 30   2017.7

SOI image sensor for ion flight time measurement using thermal noise suppressing sample hold circuit

41 ( 25 )   35 - 38   2017.7

時分割多重機構を用いた高密度FPGAイジングマシン (ディペンダブルコンピューティング)

山本 佳生, 高前田 伸也, 池辺 将之, 浅井 哲也, 本村 真人

電子情報通信学会技術研究報告 = IEICE technical report : 信学技報   117 ( 45 )   21 - 26   2017.5

動的再構成ハードウェアアーキテクチャを活かしたCNNの実装と評価 (リコンフィギャラブルシステム)

植松 瞭太, 廣瀬 一俊, 安藤 洸太, 折茂 健太郎, 植吉 晃大, 高前田 伸也, 池辺 将之, 浅井 哲也, 本村 真人

電子情報通信学会技術研究報告 = IEICE technical report : 信学技報   117 ( 46 )   1 - 6   2017.5

対数量子化による深層ニューラルネットワークのメモリ量削減 (コンピュータシステム)

廣瀬 一俊, 植松 瞭太, 安藤 洸太, 折茂 健太郎, 植吉 晃大, 高前田 伸也, 池辺 将之, 浅井 哲也, 本村 真人

電子情報通信学会技術研究報告 = IEICE technical report : 信学技報   117 ( 44 )   39 - 44   2017.5

FPGAを用いたCNNの最適ハードウェア構成とその二値化検討 (リコンフィギャラブルシステム)

植吉 晃大, 安藤 洸太, 折茂 健太郎, 高前田 伸也, 池辺 将之, 本村 真人, 浅井 哲也

電子情報通信学会技術研究報告 = IEICE technical report : 信学技報   117 ( 46 )   31 - 36   2017.5

二値化ニューラルネットワークアクセラレータのアーキテクチャ検討 (リコンフィギャラブルシステム)

安藤 洸太, 植吉 晃大, 廣瀬 一俊, 折茂 健太郎, 植松 瞭太, 高前田 伸也, 池辺 将之, 浅井 哲也, 本村 真人

電子情報通信学会技術研究報告 = IEICE technical report : 信学技報   117 ( 46 )   13 - 16   2017.5

時分割多重機構を用いた高密度FPGAイジングマシン (コンピュータシステム)

山本 佳生, 高前田 伸也, 池辺 将之, 浅井 哲也, 本村 真人

電子情報通信学会技術研究報告 = IEICE technical report : 信学技報   117 ( 44 )   21 - 26   2017.5

Accelerated Ternarized Deep Neural Network by sparse matrix calculation

117 ( 46 )   7 - 11   2017.5

Accelerating ZDD Construction by Lazy Evaluation for Optimizing Memory Access Patterns

30   71 - 74   2017.5

A Memory Reduction with Neuron Pruning for a Convolutional Neural Network : Its FPGA Realization

116 ( 417 )   55 - 60   2017.1

Implementation of Binarized Deep Neural Network for FPGA Considering Power Performance Enhancement

116 ( 417 )   127 - 132   2017.1

ハードウェアディープラーニングアクセラレータの研究動向

植吉晃大, 高前田伸也, 池辺将之, 浅井哲也, 本村真人

電子情報通信学会大会講演論文集(CD-ROM)   2017   2017

A Memory Based Realization of the Binarized Deep Convolutional Neural Network

116 ( 210 )   63 - 68   2016.9

長期時系列予測が可能な順伝播時系列メモリネットワークのFPGAアーキテクチャ (リコンフィギャラブルシステム)

折茂 健太郎, 安藤 洸太, 植吉 晃大, 浅井 哲也, 本村 真人

電子情報通信学会技術研究報告 = IEICE technical report : 信学技報   116 ( 53 )   85 - 90   2016.5

深層畳込みニューラルネットワークに向けたデータ流再構成型演算器アレイアーキテクチャ (リコンフィギャラブルシステム)

安藤 洸太, 折茂 健太郎, 植吉 晃大, 浅井 哲也, 本村 真人

電子情報通信学会技術研究報告 = IEICE technical report : 信学技報   116 ( 53 )   29 - 34   2016.5

FPGAによる多重ハッシュを用いた頻出アイテムセットマイニングのストリームプロセッシング (リコンフィギャラブルシステム)

山本 佳生, 浅井 哲也, 本村 真人

電子情報通信学会技術研究報告 = IEICE technical report : 信学技報   116 ( 53 )   47 - 52   2016.5

深層畳み込みニューラルネットワークの転移学習による個人識別システム

廣瀬一俊, 高前田伸也, 池辺将之, 浅井哲也, 本村真人

電子情報通信学会技術研究報告   116 ( 364(ICD2016 51-99) )   2016

視線推定における黒目中心検出処理を行うセルオートマトンLSIアーキテクチャ

岩丸直登, 池辺将之, 浅井哲也, 本村真人

電子情報通信学会大会講演論文集(CD-ROM)   2016   2016

オーバーサンプリング・アンチエリアス技術を用いた8K解像度向け超解像

草野穂高, 池辺将之, 浅井哲也, 本村真人

Optics & Photonics Japan講演予稿集(CD-ROM)   2016   2016

局所移動平均を用いた除算器の効率的な実装手法

FU Yuhan, 池辺将之, 島田武, 浅井哲也, 本村真人

電子情報通信学会大会講演論文集(CD-ROM)   2016   2016

高エネルギー効率プロセッサの実現に向けたナイーブベイズ分類器による動的分岐予測

肥田格, 池辺将之, 浅井哲也, 本村真人

電子情報通信学会大会講演論文集(CD-ROM)   2016   2016

アンチエイリアシングによるUHDTV向け単一画像超解像のFPGA実装

草野穂高, 池辺将之, 浅井哲也, 本村真人

電子情報通信学会大会講演論文集(CD-ROM)   2016   2016

無地物体の動き検出のための縞模様形成アーキテクチャ

谷端蒼, 池辺将之, 浅井哲也, 本村真人

電子情報通信学会大会講演論文集(CD-ROM)   2016   2016

直交位相検出TDCを用いたシングルスロープADCの回路構成検討

横山紗由里, 羅晰珍, 内田大輔, 池辺将之, 浅井哲也, 本村真人

電子情報通信学会技術研究報告   116 ( 364(ICD2016 51-99) )   2016

大局および局所適応型輝度補正技術の効率的なハードウェア化の検討

吉田嵩志, 池辺将之, 島田武, 高前田伸也, 浅井哲也, 本村真人

電子情報通信学会技術研究報告   116 ( 364(ICD2016 51-99) )   2016

局所移動平均を用いた補間曲線の性質とその回路応用

島田武, 池辺将之, 付宇かん, 高前田伸也, 浅井哲也, 本村真人

電子情報通信学会技術研究報告   116 ( 364(ICD2016 51-99) )   2016

ナイーブベイズ分類器を用いた動的分岐予測器の設計と評価

肥田格, 高前田伸也, 池辺将之, 本村真人, 浅井哲也

電子情報通信学会技術研究報告   116 ( 364(ICD2016 51-99) )   2016

輪郭情報からテクスチャを自動形成する非線形画像処理アルゴリズムとそのFPGA実装

谷端蒼, 牛田実穂, 高前田伸也, 池辺将之, 本村真人, 浅井哲也

電子情報通信学会技術研究報告   116 ( 364(ICD2016 51-99) )   2016

Development of multi-tap CMOS lock-in pixel imager with a high time-resolution for time-resolved measurements (Information Sensing Technologies)

IKEBE Masayuki, UCHIDA Daisuke, TAKE Yasuhiro, SOMEYA Makito, CHIKUDA Satoshi, MATSUYAMA Kento, ASAI Tetsuya, KURODA Tadahiro, MOTOMURA Masato

ITE Technical Report   39 ( 44 )   17 - 20   2015.11

A-1-20 A Low Power TDC with Intermittent Operation for CMOS Image Sensor

Uchida Daisuke, Ikebe Masayuki, Someya Makito, Chikuda Satoshi, Asai Tetsuya, Motomura Masato

Proceedings of the IEICE Engineering Sciences Society/NOLTA Society Conference   2015   20 - 20   2015.8

Scalable FPGA-based Accelerator of Locality-Sensitive Hashing for Similarity Search

28   232 - 236   2015.8

Enhancing Memcached by Caching Its Data and Functionalities at Network Interface

EricS.Fukuda, Hiroaki Inoue, Takashi Takenaka, Dahoo Kim, Tsunaki Sadahisa, Tetsuya Asai, Masato Motomura

IPSJ Journal   56 ( 3 )   2015.3

D-6-8 A Scalable FPGA-based Architecture of Locality-Sensitive Hashing

Sadahisa Tsunaki, Yamamoto Kasho, Kim Dahoo, Fukuda Eric S., Asai Tetsuya, Motomura Masato

Proceedings of the IEICE General Conference   2015 ( 1 )   72 - 72   2015.2

CMOSイメージセンサ用低電力間欠動作カラムTDC

内田大輔, 池辺将之, 染谷槙人, 築田聡史, 浅井哲也, 本村真人

電子情報通信学会大会講演論文集(CD-ROM)   2015   2015

A transparent on-chip instruction cache for reducing power and energy consumption of NV microcontrollers

KIM Dahoo, HIDA Itaru, ASAI Tetsuya, MOTOMURA Masato

IEICE technical report. Computer systems   114 ( 346 )   43 - 43   2014.11

A Scalable Hardware Architecture of Locality-Sensitive Hashing for Similarity Search

SADAHISA Tsunaki, YAMAMOTO Kasho, KIM Dahoo, FUKUDA Eric S., ASAI Tetsuya, MOTOMURA Masato

IEICE technical report. Computer systems   114 ( 346 )   45 - 45   2014.11

D-23-1 Dynamic Load Generator for Memcached

Sadahisa Tsunaki, Fukuda Eric S., Asai Tetsuya, Motomura Masato

Proceedings of the IEICE General Conference   2014 ( 2 )   201 - 201   2014.3

二重キャッシングによるMemcached高速化の提案 (リコンフィギャラブルシステム)

福田 エリック駿, 定久 紀基, 井上 浩明, 竹中 崇, 浅井 哲也, 本村 真人

電子情報通信学会技術研究報告 = IEICE technical report : 信学技報   113 ( 418 )   91 - 96   2014.1

二重キャッシングによるMemcached高速化の提案 (VLSI設計技術)

福田 エリック駿, 定久 紀基, 井上 浩明, 竹中 崇, 浅井 哲也, 本村 真人

電子情報通信学会技術研究報告 = IEICE technical report : 信学技報   113 ( 416 )   91 - 96   2014.1

二重キャッシングによるMemcached高速化の提案(FPGA応用,FPGA応用及び一般)

福田 エリック駿, 定久 紀基, 井上 浩明, 竹中 崇, 浅井 哲也, 本村 真人

電子情報通信学会技術研究報告. CPSY, コンピュータシステム   113 ( 417 )   91 - 96   2014.1

二重キャッシングによるMemcached高速化の提案

福田エリック駿, 定久紀基, 井上浩明, 竹中崇, 浅井哲也, 本村真人

研究報告システムLSI設計技術（SLDM）   2014 ( 16 )   1 - 6   2014.1

FPGA-based Design for Motion-Vector Estimation exploiting High-Speed imaging and its Application to Machine Learning

MORI Masafumi, ITOU Toshiyuki, IKEBE Masayuki, ASAI Tetsuya, KURODA Tadahiro, MOTOMURA Masato

Technical report of IEICE. ICD   113 ( 419 )   25 - 25   2014.1

A Restricted Dynamically Reconfiguration Architecture for Low Power Processors

HIRAO Takeshi, KIM Dahoo, Hida ITARU, ASAI Tetsuya, MOTOMURA Masato

IEICE technical report   113 ( 221 )   25 - 30   2013.9

An Implementation of High Performance Stream Processing on a Reconfigurable Hardware

FUKUOKA Eric-shun, KAWASHIMA Hideyuki, INOUE Hiroaki, FUJII Taro, FURUTA Koichiro, ASAI Tetsuya, MOTOMURA Masato

IEICE technical report   113 ( 221 )   7 - 12   2013.9

Writing Window Join Processor in C

FUKUDA Eric shun, KAWASHIMA Hideyuki, INOUE Hiroaki, ASAI Tetsuya, MOTOMURA Masato

IEICE technical report. Information networks   113 ( 92 )   7 - 12   2013.6

Array Enhanced Chaotic Resonance among Forced Chua's Oscillators

ISHIMURA Kazuyoshi, ASAI Tetsuya, MOTOMURA Masato

IEICE technical report. Nonlinear problems   112 ( 389 )   131 - 136   2013.1

C-12-10 Multi-Scale Wavelet Shrinkage for Image Denoising and its LSI Architecture : Part I

Yin Zhengyi, Sanada Yuki, Asai Tetsuya, Motomura Masato, Takenaka Takashi

Proceedings of the IEICE General Conference   2012 ( 2 )   82 - 82   2012.3

A-2-36 Chaotic Resonance in Forced Chua's Oscillator

Ishimura Kazuyoshi, Asai Tetsuya, Motomura Masato

Proceedings of the IEICE General Conference   2012   81 - 81   2012.3

C-12-17 LSI Architectures for LDPC Error Correction based on Stochastic Logic

Gong Xiyuan, Asai Tetsuya, Motomura Masato

Proceedings of the IEICE General Conference   2012 ( 2 )   89 - 89   2012.3

C-12-18 A Chained Datapath for Low Power Processors : Part I

Adachi Taku, Hirao Takeshi, Asai Tetsuya, Motomura Masato

Proceedings of the IEICE General Conference   2012 ( 2 )   90 - 90   2012.3

A-1-17 Noise-Induced Phase Synchronization in Digital Oscillators

Matsuura Masakazu, Asai Tetsuya, Motomura Masato

Proceedings of the IEICE General Conference   2012   17 - 17   2012.3

C-12-11 Multi-Scale Wavelet Shrinkage for Image Denoising and its LSI Architecture : Part II

Sanada Yuki, Yin Zhengyi, Asai Tetsuya, Motomura Masato, Takenaka Takashi

Proceedings of the IEICE General Conference   2012 ( 2 )   83 - 83   2012.3

C-12-19 A Chained Datapath for low power processors : Part II

Hirao Takeshi, Adachi Taku, Asai Tetsuya, Motomura Masato

Proceedings of the IEICE General Conference   2012 ( 2 )   91 - 91   2012.3

A-2-36 Chaotic resonance in Chua's double scroll system

Ishimura Kazuyoshi, Asai Tetsuya, Motomura Masato

Proceedings of the Society Conference of IEICE   2011   73 - 73   2011.8

A-2-28 Numerical Simulations of Excitable Medium with Memristive Coupling

Gong Xiyuan, Asai Tetsuya, Motomura Masato

Proceedings of the Society Conference of IEICE   2011   65 - 65   2011.8

A-1-29 Phase Modulation in Crystal Oscillators toward an Application of Noise-induced Phase Synchronization

Matsuura Masakazu, Asai Tetsuya, Motomura Masato

Proceedings of the Society Conference of IEICE   2011   29 - 29   2011.8

A-1-5 An analog STDP synaptic device consisting of a Resistive RAM and CMOS Circuits

Adachi Taku, Asai Tetsuya, Motomura Masato

Proceedings of the Society Conference of IEICE   2011   5 - 5   2011.8

A-1-28 Evaluation of Ultra Low-power Low-supply-voltage Memory Cell utilizing Hysteresis Characteristic of Positive-feedback Operational Transconductance Amplifier

Yoshida Kazunori, Utagawa Akira, Asai Tetsuya, Motomura Masato

Proceedings of the Society Conference of IEICE   2011   28 - 28   2011.8

Circuit-Oriented Chaos Dynamics based on the Duffing Equation and Experiments of Chaotic Resonance with Analog Electronic Circuits

ISHIMURA Kazuyoshi, ASAI Tetsuya, MOTOMURA Masato

IEICE technical report   111 ( 106 )   1 - 6   2011.6

Noise-Induced Phase Synchronization among Current-Noise-Sensitive Analog CMOS Oscillators

MATSUURA Masakazu, UTAGAWA Akira, ASAI Tetsuya, MOTOMURA Masato

IEICE technical report   111 ( 106 )   23 - 28   2011.6

An Analog Gadget for Path Discovery with a Unipolar ReRAM Network

GONG Xiyuan, AKOU Nobuo, ASAI Tetsuya, MOTOMURA Masato

IEICE technical report   111 ( 106 )   47 - 51   2011.6

A Memristor-based Synaptic Device having an Asymmetric STDP Time Window

ADACHI Taku, AKOU Nobuo, ASAI Tetsuya, MOTOMURA Masato

IEICE technical report   111 ( 106 )   65 - 70   2011.6

A Dynamically Reconfigurable Processor Architecture

MOTOMURA Masato

Microprocessor Forum, 2002   2002

A Virtual Hardware System on a Dynamically Reconfigurable Logic Device

UNO M., SHIBATA Y., AMANO H., FURUTA K., FUJII T., MOTOMURA M.

CPSY   99 ( 532 )   53 - 60   2000.1

A Virtual Hardware System on a Dynamically Reconfigurable Logic Device

UNO M., SHIBATA Y., AMANO H., FURUTA K., FUJII T., MOTOMURA M.

Technical report of IEICE. VLD   99 ( 530 )   53 - 60   2000.1

A Virtual Hardware System on a Dynamically Reconfigurable Logic Device

UNO M., SHIBATA Y., AMANO H., FURUTA K., FUJII T., MOTOMURA M.

94   133 - 140   2000.1

イメージセンサ用複数位相型TDCに向けたCDS機構

Watanabe K, Uchida D, Someya M, Ikebe M, Asai T, Motomura M

LSIとシステムのワークショップ  2014.5 

Noise-driven computing architectures for coarse-grained devices towards molecular architectonics

Gonzalez-Carabarin L, Asai T, Motomura M

文部科学省科学研究費補助金「新学術領域研究」分子アーキテクトニクス領域会議  2014.6 

興奮場における持続的集団ノイズ生成のメカニズム：外部雑音源を使わない確率共鳴

Ishimura K, Komuro K, Asai T, Motomura M

文部科学省科学研究費補助金「新学術領域研究」分子アーキテクトニクス領域会議  2014.6 

反応拡散モデルを応用した生物的ステガノグラフィシステムとその回路実装

Komuro K, Ishimura K, Asai T, Motomura M

文部科学省科学研究費補助金「新学術領域研究」分子アーキテクトニクス領域会議  2014.6 

Mismatch-tolerant stochastic logic gates and their application to low-power asynchronous VLSI circuits

Gonzalez-Carabarin L, Asai T, Motomura M

LSIとシステムのワークショップ  2014.5 

統計的解析法に耐性のあるステガノグラフィアルゴリズムとそのFPGA実装

Ishimura K, Komuro K, Schmid A, Asai T, Motomura M

LSIとシステムのワークショップ  2014.5 

組み込みプロセッサの低電力化に向けた限定的動的再構成アクセラレータの設計と評価

Hida I, Hirao T, Kim D, Asai T, Motomura M

LSIとシステムのワークショップ  2014.5 

興奮性媒体の自発的活動による自己確率共鳴

Ishimura K, Komuro K, Schmid A, Asai T, Motomura M

第3回 情報ネットワーク科学研究会・複雑コミュニケーションサイエンス研究会合同ワークショップ  2014.8 

Caching memcached at reconfigurable network interface International conference

Fukuda E.S, Inoue H, Takenaka T, Kim D, Sadahisa T, Asai T, Motomura M

24th International Conference on Field Programmable Logic and Applications  2014.9 

Stochastic resonance in a unidirectional network of nonlinear oscillators driven by internal noise International conference

Ishimura K, Komuro K, Schmid A, Asai T, Motomura M

2014 International Symposium on Nonlinear Theory and its Applications  2014.9 

A study of transparent on-chip instruction cache for NV microcontrollers International conference

Kim D, Hida I, Fukuda E.S, Asai T, Motomura M

7th International Conference on Advances in Circuits, Electronics and Micro-electronics  2014.11 

類似検索を行うLocality-Sensitive Hashingのスケーラブルなハードウェアアーキテクチャ

Sadahisa T, Yamamoto K, Kim D, Fukuda E.S, Asai T, Motomura M

電子情報通信学会集積回路研究会・コンピュータシステム研究会合同 平成26年度若手研究会  2014.12 

不揮発性メモリ搭載マイコンの低電力化を目的とした透過型命令キャッシュの提案と評価

Kim D, Hida I, Asai T, Motomura M

電子情報通信学会集積回路研究会・コンピュータシステム研究会合同 平成26年度若手研究会  2014.12 

ビッグデータ時代のリコンフィギュラブルハードウェア技術 Invited

Motomura M

東北大学電気通信研究所 第三回ブレインウェア工学研究会  2014.12 

Dual-rail asynchronous pipeline based on stochastic resonance logic gates International conference

Gonzalez-Carabarin L, Asai T, Motomura M

2014 International Symposium on Nonlinear Theory and its Applications  2014.9 

Hardware architecture for accelerating key-value retrieval implemented on FPGA International conference

Kim D, Fukuda E.S, Sadahisa T, Asai T, Motomura M

3rd Japan-Korea Joint Workshop on Complex Communication Sciences  2014.10 

ムーア則の終焉とビッグデータの勃興：RHW視点での一考察 Invited

Motomura M

JApan Consortium for the Reconfigurable-hardware Next generation (JACORN) 2014 次世代RHW創造研究会  2014.10 

A 4.5 to 13 times energy-efficient embedded microprocessor with mainly-static/partially-dynamic reconfigurable array accelerator International conference

Hida I, Kim D, Asai T, Motomura M

Asian Solid-State Circuits Conference 2014  2014.11 

Achieving higher performance of memcached by caching at network interface International conference

Fukuda E.S, Inoue H, Takenaka T, Kim D, Sadahisa T, Asai T, Motomura M

2014 International Conference on Field Programmable Technology  2014.12 

動きベクトルの機械学習アーキテクチャとそのFPGA実装

Mori M, Itou T, Ikebe M, Asai T, Kuroda T, Motomura M

STARCシンポジウム2015  2015.1 

A memory-based realization of a binarized deep convolutional neural network International conference

Nakahara H, Yonekawa H, Sasao T, Iwamoto H, Motomura M

International Conference on Field-Programmable Technology  2016.12 

抵抗変化型メモリを用いたアナログ STDP シナプスデバイス

安達 琢, 浅井 哲也, 本村 真人

電子情報通信学会ソサイエティ大会  2011.9 

大局および局所適応型輝度補正技術の効率的なハードウェア化の検討

Yoshida T, Ikebe M, Shimada T, Takamaeda-Yamazaki S, Motomura M, Asai T

電子情報通信学会 ICD/CPSY 学生・若手研究会  2016.12 

Chuaのダブルスクロール系におけるカオス共鳴

石村 憲意, 浅井 哲也, 本村 真人

電子情報通信学会ソサイエティ大会  2011.9 

直交位相検出TDCを用いたシングルスロープADCの回路構成検討

Yokoyama S, Na S, Uchida D, Ikebe M, Motomura M, Asai T

電子情報通信学会 ICD/CPSY 学生・若手研究会  2016.12 

メモリスタを拡散結合に用いた興奮場モデルの数値解析

宮 曦媛, 浅井 哲也, 本村 真人

電子情報通信学会ソサイエティ大会  2011.9 

輪郭情報からテクスチャを自動生成する非線形画像処理アルゴリズムとそのFPGA実装

Tanibata A, Ushida M, Takamaeda-Yamazaki S, Ikebe M, Motomura M, Asai T

電子情報通信学会 ICD/CPSY 学生・若手研究会  2016.12 

雑音誘起位相同期の応用に向けた水晶発振器の位相変調回路

松浦 正和, 浅井 哲也, 本村 真人

電子情報通信学会ソサイエティ大会  2011.9 

FPGA architecture for feed-forward sequential memory network targeting long-term time-series forecasting International conference

Orimo K, Ando K, Ueyoshi K, Ikebe M, Asai T, Motomura M

2016 International Conference on Reconfigurable Computing and FPGAs  2016.11 

電力性能効率に優れた二値化ディープニューラルネットワークのFPGA実装

Yonekawa H, Nakahara H, Motomura M

電子情報通信学会リコンフィギャラブルシステム研究会  2017.1 

外力を受けるチュア発振回路におけるカオス共鳴

石村 憲意, 浅井 哲也, 本村 真人

電子情報通信学会総合大会  2012.3 

パルス演算に基づくLDPCエラー訂正処理とそのアーキテクチャ

宮 曦媛, 浅井 哲也, 本村 真人

電子情報通信学会総合大会  2012.3 

深層畳み込みニューラルネットワークの転移学習による個人識別システム

Hirose K, Takamaeda-Yamazaki S, Ikebe M, Asai T, Motomura M

電子情報通信学会 ICD/CPSY 学生・若手研究会  2016.12 

20Gbps C-based complex event processing

Inoue H, Takenaka T, Motomura M

21st International Conference on Field Programmable Logic and Applications (FPL)  2011.9 

ナイーブベイズ分類器を用いた動的分岐予測器の設計と評価

Hida I, Takamaeda-Yamazaki S, Ikebe M, Motomura M, Asai T

電子情報通信学会 ICD/CPSY 学生・若手研究会  2016.12 

A subthreshold memory cell utilizing nonlinear characteristics of positive-feedback operational transconductance amplifier

Yoshida K, Asai T, Motomura M

2011 Kyoto Workshop on NOLTA  2011.11 

局所移動平均を用いた補間曲線の性質とその回路応用

Shimada T, Ikebe M, Fu Y, Takamaeda-Yamazaki S, Motomura M, Asai T

電子情報通信学会 ICD/CPSY 学生・若手研究会  2016.12 

低消費電力プロセッサのための連鎖型データパスの提案I

安達 琢, 平尾 岳志, 浅井 哲也, 本村 真人

電子情報通信学会総合大会  2012.3 

ディープニューラルネットワークの2値化と3値化の比較

Yonekawa H, Nakahara H, Motomura M

第30回多値論理とその応用研究会  2017.1 

低消費電力プロセッサのための連鎖型データパスの提案II

平尾 岳志, 安達 琢, 浅井 哲也, 本村 真人

電子情報通信学会総合大会  2012.3 

Throughput analysis of a data-flow reconfigurable array architecture for convolutional neural networks International conference

Ando K, Ueyoshi K, Orimo K, Ikebe M, Takamaeda-Yamazaki S, Asai T, Motomura M

The 5th RIEC International Symposium on Brain Functions and Brain Computer  2017.2 

ウェーブレット縮退の多段化によるデノイズ画像処理とそのLSIアーキテクチャ: Part I

尹 征一, 真田 祐樹, 浅井 哲也, 本村 真人, 竹中 崇

電子情報通信学会総合大会  2012.3 

6-DoF camera-position and posture estimation based on local patches of image sequence International conference

Tsuji T, Ikebe M, Takamaeda-Yamazaki S, Motomura M, Asai T

2017 RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing  2017.2 

ウェーブレット縮退の多段化によるデノイズ画像処理とそのLSIアーキテクチャ: Part II

真田 祐樹, 尹 征一, 浅井 哲也, 本村 真人, 竹中 崇

電子情報通信学会総合大会  2012.3 

AI応用がもたらすプロセッサLSIのゲームチェンジ Invited

Motomura M

CRDSシンポジウム IoT/AI時代にむけたテクノロジー革新?大変革時代の新機軸とは?  2017.3 

A memristor-based synaptic device having an asymmetric STDP time window

Adachi T, Asai T, Motomura M

2012 RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing  2012.3 

知的情報処理が導く情報処理ハードウェアの革新 Invited

Motomura M

JEITAデバイス技術分科会  2017.3 

Chaotic resonance in forced Chua's oscillator

Ishimura K, Asai T, Motomura M

2012 RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing  2012.3 

畳込みニューラルネットワークのニューロン刈りによるメモリ量削減とFPGA実現について

Fujii T, Sato S, Nakahara H, Motomura M

電子情報通信学会リコンフィギャラブルシステム研究会  2017.1 

A batch normalization free binarized convolutional deep neural network on an FPGA International conference

Nakahara H, Yonekawa H, Iwamoto H, Motomura M

International Symposium on Field-Programmable Gate Array  2017.2 

ディジタル発振器群における雑音誘起位相同期

松浦 正和, 浅井 哲也, 本村 真人

電子情報通信学会総合大会  2012.3 

プロセッサの低電力化に向けた連鎖型データパスの実装と電力評価

平尾 岳志, 安達 琢, 浅井 哲也, 本村 真人

LSIとシステムのワークショップ  2012.5 

Low latency divider using ensemble of moving average curves International conference

Fu Y, Ikebe M, Shimada T, Motomura M, Asai T

The 18th International Symposium on Quality Electronic Design (ISQED 2017)  2017.3 

Excitable reaction-diffusion media with memristors

Gong X, Asai T, Motomura M

2012 RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing  2012.3 

ハードウェアディープラーニングアクセラレータの研究動向 Invited

Ueyoshi K, Takamaeda-Yamazaki S, Ikebe M, Asai T, Motomura M

2017年電子情報通信学会総合大会 シンポジウムセッション「神経回路ハードウェア研究の最前線」  2017.3 

Noise-induced phase synchronization in digital counters

Matsuura M, Asai T, Motomura M

2012 RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing  2012.3 

Rise of deep neural network accelerators Invited International conference

Motomura M

Workshop on Brain-inspired Hardware  2017.3 

Noise-assisted spike transmission on an array of electrical FitzHugh-Nagumo models

Gonzalez-Carabarin L, Asai T, Motomura M

2012 RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing  2012.3 

An FPGA realization of a deep convolutional neural network using a threshold neuron pruning International conference

Fujii T, Sato S, Nakahara H, Motomura M

International Symposium on Applied Reconfigurable Computing  2017.4 

ウェーブレット縮退の多段化に基づくデノイズLSIの省メモリアーキテクチャ

真田 祐樹, 尹 征一, 浅井 哲也, 本村 真人, 竹中 崇

LSIとシステムのワークショップ  2012.5 

Spike transmission in locally coupled excitable circuits enhanced by membrane-potential-dependent noise

Gonzalez-Carabarin L, Asai T, Motomura M

Asia Conference on Nanoscience and Nanotechnology 2012  2012.9 

Spatio-temporal pattern formation on memristive reaction-diffusion systems

Gong X, Asai T, Motomura M

Asia Conference on Nanoscience and Nanotechnology 2012  2012.9 

Spike propagation in excitable systems enhanced by membrane-potential-dependent noise

Gonzalez-Carabarin L, Asai T, Motomura M

The 2012 International Symposium on Nonlinear Theory and its Applications  2012.10 

強制Chua発振器の集団におけるArray-Enhancedカオス共鳴

石村 憲意, 浅井 哲也, 本村 真人

電子情報通信学会非線形問題研究会  2013.1 

Noise impact on spike transmission through serially-connected electrical FitzHugh-Nagumo model with subthreshold and suprathreshold interconductances

Gonzalez-Carabarin L, Asai T, Motomura M

The 16th International Conference On Cognitive and Neural Systems  2012.5 

Reaction-diffusion media with excitable Oregonators coupled by memristors

Gong X, Asai T, Motomura M

The 13th International Workshop on Cellular Nanoscale Networks and their Applications (The 3rd Memristor and Memristive Symposium)  2012.8 

イメージセンサ-プロセッサ三次元集積システムにおける深度マップ生成：アルゴリズムと回路アーキテクチャ

真田 祐樹, 五十嵐 正樹, 池辺 将之, 浅井 哲也, 本村 真人, 大畑 克樹, 黒田 忠広

STARCシンポジウム2013  2013.1 

複数位相型TDCを用いたCMOSイメージセンサ用 Single-Slope ADC

内田 大輔, 池辺 将之, 浅井 哲也, 本村 真人, 竹 康宏, 黒田 忠広

STARCシンポジウム2013  2013.1 

FPGA implementation of single-image super resolution based on frame-bufferless box filtering

Sanada Y, Ohira T, Chikuda S, Igarashi M, Ikebe M, Asai T, Motomura M

2013 RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing  2013.3 

C-based adaptive stream processing on dynamically reconfigurable hardware: window join case study

Fukuda E.S, Kawashima H, Inoue H, Fujii T, Furuta K, Asai T, Motomura M

The 9th International Symposium on Applied Reconfigurable Computing  2013.3 

C言語による動的リコンフィギュラブルハードウェアへのWindow Joinの実装

福田 駿, 川島 英之, 井上 浩明, 浅井 哲也, 本村 真人

電子情報通信学会 情報ネットワーク研究会  2013.6 

ハードウェア実装に向けた反応拡散ステガノグラフィモデル

石村 憲意, Alexandre Schmid, 浅井 哲也, 本村 真人

2013年度第1回電子情報通信学会複雑コミュニケーションサイエンス時限研究会  2013.6 

Exploiting hardware reconfigurability on window join

Fukuda E.S, Kawashima H, Inoue H, Asai T, Motomura M

The 2013 International Conference on High Performance Computing & Simulation  2013.7 

Image steganography on digital reaction-diffusion processor

Ishimura K, Schmid A, Asai T, Motomura M

Nonlinear Dynamics of Electronic Systems 2013  2013.7 

低消費電力プロセッサのための限定的動的再構成アーキテクチャの提案

平尾 岳志, 安達 琢, 浅井 哲也, 本村 真人

先進的計算基盤システムシンポジウム  2013.5 

省メモリ指向一枚超解像 アーキテクチャとそのFPGA実装

大平 貴徳, 真田 祐樹, 築田 聡史, 五十嵐 正樹, 池辺 将之, 浅井 哲也, 本村 真人

LSIとシステムのワークショップ  2013.5 

CMOSイメージセンサ用シングルスロープA/D変換器の高速化および低電力化

染谷 槙人, 内田 大輔, 池辺 将之, 本久 順一, 浅井 哲也, 本村 真人

LSIとシステムのワークショップ  2013.5 

Towards asynchronous digital circuit design based on stochastic resonance

Gonzalez-Carabarin L, Asai T, Motomura M

The 1st International Conference on Nanoenergy  2013.7 

ハードウェア指向ステレオマッチングアルゴリズムのアーキテクチャとそのFPGA実装

松山 健人, 真田 祐樹, 大畑 克樹, 大垣 哲郎, 大平 貴徳, 築田 聡史, 五十嵐 正樹, 池辺 将之, 浅井 哲也, 本村 真人, 黒田 忠広

VDECデザイナーズフォーラム2013  2013.8 

ゆらぎ利用しきい論理素子による非同期式論理回路の設計

Gonzalez-Carabarin L, 浅井 哲也, 本村 真人

2013年度第2回電子情報通信学会 NetSci/CCS研究会 合同ワークショップ  2013.8 

直交位相検出TDCを用いたイメージセンサ用12-bit Single-Slope ADC

Yokoyama S, Ikebe M, Na S, Takamaeda-Yamazaki S, Motomura M, Asai T

LSIとシステムのワークショップ2017  2017.5 

時分割多重機構を用いたイジングプロセッサの解精度向上手法の検討

Yamamoto K, Ikebe M, Asai T, Motomura M, Takamaeda-Yamazaki S

LSIとシステムのワークショップ2017  2017.5 

Exploring optimized accelerator design for binarized convolutional neural networks International conference

Ueyoshi K, Ando K, Orimo K, Ikebe M, Asai T, Motomura M

The 2017 International Joint Conference on Neural Networks  2017.5 

ソフトリセット機構を用いたイオン飛行時間計測用SOIイメージセンサ

Na S, Ikebe M, Yokoyama S, Takamaeda-Yamazaki S, Motomura M, Asai T, Hazama H, Fujita Y, Arai Y

LSIとシステムのワークショップ2017  2017.5 

二値化ニューラルネットワークアクセラレータのアーキテクチャ検討

Ando K, Ueyoshi K, Hirose K, Orimo K, Uematsu R, Takamaeda-Yamazaki S, Ikebe M, Asai T, Motomura M

電子情報通信学会リコンフィギャラブルシステム研究会 (RECONF)  2017.5 

FPGAを用いたCNNの最適ハードウェア構成とその二値化検討

Ueyoshi K, Ando K, Orimo K, Takamaeda-Yamazaki S, Ikebe M, Asai T, Motomura M

電子情報通信学会リコンフィギャラブルシステム研究会 (RECONF)  2017.5 

AI応用が導く情報処理ハードウェアの革新 Invited

Motomura M

JST革新コンピューティングセミナー  2017.4 

メモリアクセスパターンを考慮した遅延評価によるZDD構築の高速化

Kumazawa T, Takamaeda-Yamazaki S, Ikebe M, Asai T, Motomura M

第30回 回路とシステムワークショップ  2017.5 

AI応用が導く情報処理ハードウェアの革新 Invited

Motomura M

学振165委員会「人工知能システムのコア技術と周辺技術」  2017.4 

A scalable ising model implementation on an FPGA International conference

Yamamoto K, Takamaeda-Yamazaki S, Ikebe M, Asai T, Motomura M

COOL Chips 20  2017.4 

A novel iris-center detection algorithm towards gaze estimation targeting molecular cellular automata International conference

Iwamaru N, Takamaeda-Yamazaki S, Ikebe M, Motomura M, Asai T

International Workshop on Molecular Architectonics 2018  2018.3 

ZDDを用いた三角形分割パターンの列挙とその応用に向けて

Kumazawa T, Suzuki H, Ishihata M, Asai T, Ikebe M, Motomura M, Takamaeda-Yamazaki S

人工知能学会 第106回人工知能基本問題研究会  2018.3 

Quantization Error-based Regularization in Neural Networks International conference

Hirose K, Ando K, Ueyoshi K, Ikebe M, Asai T, Motomura M, Takamaeda-Yamazaki S

Thirty-seventh SGAI International Conference on Artificial Intelligence (SGAI 2017)  2017.12 

Trends toward Reconfigurable and in-Memory Processing Architectures for Deep Neural Networks Invited International conference

Motomura M

Future Chips 2017  2017.12 

Sign-invariant unsupervised learning facilitates weighted-sum computation in analog neural-network devices International conference

Hida I, Ueyoshi K, Takamaeda-Yamazaki S, Ikebe M, Motomura M, Asai T

2017 International Symposium on Nonlinear Theory and Its Applications  2017.12 

Accelerating Deep Learning by Binarized Hardware International conference

Takamaeda-Yamazaki S, Ueyoshi K, Ando K, Uematsu R, Hirose K, Ikebe M, Asai T, Motomura M

Asia-Pacific Signal and Information Processing Association Annual Summit and Conference 2017 (APSIPA ASC 2017)  2017.12 

QUEST: A 7.49-TOPS Multi-Purpose Log-Quantized DNN Inference Engine Stacked on 96MB 3D SRAM using Inductive-Coupling Technology in 40nm CMOS International conference

Ueyoshi K, Ando K, Hirose K, Takamaeda-Yamazaki S, Kadomoto J, Miyata T, Hamada M, Kuroda T, Motomura M

2018 International Solid-State Circuits Conference (ISSCC 2018)  2018.2 

QUEST: A 7.49TOPS Multi-Purpose Log- Quantized DNN Inference Engine Stacked on 96MB 3D SRAM Using Inductive-Coupling Technology in 40nm CMOS

Ueyoshi K, Ando K, Hirose K, Takamaeda-Yamazaki S, Kadomoto J, Miyata T, Hamada M, Kuroda T, Motomura M

ISSCC2018報告会  2018.2 

AIハードウェアの動向とニューロモル フィックHW分野の一考察 Invited

Motomura M

NEDO第3回ニューロモルフィックコンピューティング勉強会  2018.1 

Hardware-Algorithm Co-design for Efficient DNN Processing Invited

Motomura M

NEC基幹技術フォーラム  2018.2 

知的情報処理時代を支える情報処理アーキテクチャの革新 Invited

Motomura M

科学技術未来戦略ワークショップ「ドメインスペシフィックコンピューティング」  2017.11 

革新的コンピュータによるSociety5.0を支えるコア技術の創出 Invited

Motomura M

平成30年度戦略目標検討ワークショップ  2017.11 

Logarithmic Compression for Memory Footprint Reduction in Neural Network Training International conference

Hirose K, Uematsu R, Ando K, Orimo K, Ueyoshi K, Ikebe M, Asai T, Takamaeda-Yamazaki S, Motomura M

5th International Workshop on Computer Systems and Architectures (CSA 2017)  2017.11 

FPGA implementation of edge-guided pattern generation for motion-vector estimation of textureless objects (demo night) International conference

Tanibata A, Schmid A, Takamaeda-Yamazaki S, Ikebe M, Motomura M, Asai T

The 27th International Conference on Field-Programmable Logic and Applications  2017.9 

不揮発アナログシナプスデバイスの素子数を半減する重み符号固定事前学習法とその深層学習への適用

Hida I, Ueyoshi K, Takamaeda-Yamazaki S, Ikebe M, Motomura M, Asai T

日本神経回路学会第27回全国大会  2017.9 

A Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Invited International conference

Motomura M

CSAIL Seminor  2017.8 

Research Activity on Deep Neural Network Accelerators Invited International conference

Motomura M

Tsinghua University Workshop  2017.10 

機械学習向けチップの動向 Invited

Motomura M

ISSCC2018記者会見  2017.11 

A Regularization Approach for Quantized Neural Networks International conference

Hirose K, Uematsu R, Ando K, Ueyoshi K, Ikebe M, Asai T, Motomura M, Takamaeda-Yamazaki S

International Workshop on Highly Efficient Neural Networks Design (HENND 2017)  2017.10 

Trends toward Reconfigurable and in-Memory Processing Architectures for Deep Neural Networks Invited International conference

Motomura M

Chinese Academy of Science (CAS) Distinguished Lecture  2017.10 

量子化誤差を考慮したニューラルネットワークの学習手法

Hirose K, Ando K, Ueyoshi K, Ikebe M, Asai T, Motomura M, Takamaeda-Yamazaki S

人工知能学会人工知能基本問題研究会 (SIG-FPAI)  2017.8 

A Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Invited International conference

Motomura M

SEAS Seminor  2017.8 

熱雑音抑制型サンプルホールド回路を用いたイオン飛行時間計測用SOIイメージセンサ

Na S, Ikebe M, Yokoyama S, Takamaeda-Yamazaki S, Motomura M, Asai T, Hazama H, Fujita Y, Arai Y

映像情報メディア学会情報センシング研究会 (IST)  2017.7 

In-Memory Area-Efficient Signal Streaming Processor Design for Binary Neural Networks International conference

Ando K, Ueyoshi K, Hirose K, Orimo K, Yonekawa H, Sato S, Nakahara H, Ikebe M, Takamaeda-Yamazaki S, Asai T, Kuroda T, Motomura M

60th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2017)  2017.8 

A versatile and energy-efficient reconfigurable accelerator for embedded microprocessors International conference

Hida I, Takamaeda-Yamazaki S, Ikebe M, Motomura M, Asai T

GI-CoRE GSQ, GSB, & IGM Joint Symposium -Quantum, Informatics, Biology, & Medicine -  2017.7 

Hardware accelerator design for convolutional neural networks with low bit precision International conference

Ueyoshi K, Ikebe M, Asai T, Takamaeda-Yamazaki S, Motomura M

GI-CoRE GSQ, GSB, & IGM Joint Symposium -Quantum, Informatics, Biology, & Medicine -  2017.7 

[依頼講演] BRein Memory: バイナリ・インメモリ再構成型深層ニューラルネットワークアクセラレータ

Ando K, Ueyoshi K, Orimo K, Yonekawa H, Sato S, Nakahara H, Ikebe M, Asai T, Takamaeda-Yamazaki S, Kuroda T, Motomura M

電子情報通信学会集積回路研究会 (ICD)  2017.7 

貫通電流の時間変動を抑制したTDC+Single-Slope ADCの回路構成

Yokoyama S, Ikebe M, Na S, Takamaeda-Yamazaki S, Motomura M, Asai T

映像情報メディア学会情報センシング研究会 (IST)  2017.7 

AI応用が導く情報処理ハードウェアの革新 Invited

Motomura M

Impactセミナー  2017.7 

高次数イジングネットワークの時分割処理方式の検討

Yamamoto K, Kumazawa T, Ikebe M, Asai T, Motomura M, Takamaeda-Yamazaki S

電子情報通信学会コンピュータシステム研究会 (CPSY)  2017.7 

時分割多重機構を用いた高密度FPGAイジングマシン

Yamamoto K, Ikebe M, Asai T, Motomura M, Takamaeda-Yamazaki S

基盤（S）離散構造処理系プロジェクト「2017年度初夏のワークショップ」  2017.6 

AI応用が導く情報処理ハードウェアの革新 Invited

Motomura M

先進不揮発性半導体応用展開勉強会  2017.6 

A Time-Division Multiplexing Ising Machine on FPGAs International conference

Yamamoto K, Huang W, Takamaeda-Yamazaki S, Ikebe M, Asai T, Motomura M

International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART 2017)  2017.6 

メモリアクセスパターンを考慮した遅延評価によるZDD構築の高速化

Kumazawa T, Ikebe M, Asai T, Motomura M, Takamaeda-Yamazaki S

基盤（S）離散構造処理系プロジェクト「2017年度初夏のワークショップ」  2017.6 

Time-Division Multiplexing International conference

Yamamoto K, Ikebe M, Asai T, Motomura M, Takamaeda-Yamazaki S

GI-CoRE GSQ, GSB, & IGM Joint Symposium -Quantum, Informatics, Biology, & Medicine -  2017.7 

動的再構成ハードウェアアーキテクチャを活かしたCNNの実装と評価

Uematsu R, Hirose K, Ando K, Orimo K, Ueyoshi K, Takamaeda-Yamazaki S, Ikebe M, Asai T, Motomura M

電子情報通信学会リコンフィギャラブルシステム研究会 (RECONF)  2017.5 

Feature extraction system using restricted Boltzmann machines on FPGA International conference

Ueyoshi K, Marukame T, Asai T, Motomura M, Schmid A

2017 IEEE International Symposium on Circuits & Systems  2017.5 

BRein memory: a 13-layer 4.2 K neuron/0.8 M synapse binary/ternary reconfigurable in-memory deep neural network accelerator in 65 nm CMOS International conference

Ando K, Ueyoshi K, Orimo K, Yonekawa H, Sato S, Nakahara H, Ikebe M, Asai T, Takamaeda-Yamazaki S, Kuroda T, Motomura M

2017 Symposia on VLSI Technology and Circuits  2017.6 

時分割多重機構を用いた高密度FPGAイジングマシン

Yamamoto K, Takamaeda-Yamazaki S, Ikebe M, Asai T, Motomura M

電子情報通信学会コンピュータシステム研究会 (CPSY)  2017.5 

対数量子化による深層ニューラルネットワークのメモリ量削減

Hirose K, Uematsu R, Ando K, Orimo K, Ueyoshi K, Takamaeda-Yamazaki S, Ikebe M, Asai T, Motomura M

電子情報通信学会コンピュータシステム研究会 (CPSY)  2017.5 

Hardware-Oriented Approaches for Accelerating “AI” Workloads Invited International conference

Motomura M

2018 Symposium on VLSI Circuits, Short Course  2018.6 

FPGA実装に向けた大局・局所適応型輝度補正技術によるFull-HD60FPS動作実証

Shimada T, Ambalathankandy P, Takamaeda-Yamazaki S, Motomura M, Asai T, Ikebe M, Yoshida T

LSIとシステムのワークショップ  2018.5 

人工知能アクセラレータの技術動向 Invited

Motomura M

第31回 回路とシステムのワークショップ  2018.5 

Sparse disparity estimation using global phase only correlation for stereo matching acceleration International conference