Updated on 2026/03/10

写真a

 
ITO HIROYUKI
 
Organization
Institute of Integrated Research Nano Sensing Research Unit Professor
Title
Professor
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News & Media

Degree

  • Master of Engineering ( Tokyo Institute of Technology )

  • Doctor of Engineering ( Tokyo Institute of Technology )

Research Interests

  • 伝送線路

  • 電圧制御発振器

  • 伝送線路配線

  • 電力増幅器

  • 低雑音増幅器

  • power amplifier

  • transmission line interconnect

  • transmission line

  • low noise amplifier

  • voltage controlled oscillator

Research Areas

  • Manufacturing Technology (Mechanical Engineering, Electrical and Electronic Engineering, Chemical Engineering) / Electron device and electronic equipment

Education

  • Tokyo Institute of Technology   Interdisciplinary Science and Engineering   Advanced Applied Electronics

    - 2006

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    Country: Japan

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  • Tokyo Institute of Technology   Graduate School, Division of Integrated Science and Engineering   Department of Advanced Applied Electronics

    - 2006

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Research History

  • :Intel Corporation Communications Circuits Laboratory, Corporate Technology Group Visiting Professor

    2007

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  • -:東京工業大学 精密工学研究所 助教

    2007

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  • -:Tokyo Institute of Technology Precision and Intelligence Laboratory Assistant Professor

    2007

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  • :インテル株式会社

    2007

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  • :Tokyo Institute of Technology Precision and Intelligence Laboratory Tokyo Tech Postdoctoral Fellow

    2006 - 2007

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  • :日本学術振興会 特別研究員(PD)

    2006 - 2007

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  • :東京工業大学 精密工学研究所 東京工業大学特別研究員

    2006 - 2007

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  • :the Japan Society for the Promotion of Science Research Fellow

    2006 - 2007

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  • :Intel Corporation Communications Circuits Laboratory, Corporate Technology Group Temporary Visiting Researcher

    2006

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  • :インテル株式会社

    2006

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  • :the Japan Society for the Promotion of Science Research Fellow

    2004 - 2006

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  • :日本学術振興会 特別研究員(DC1)

    2004 - 2006

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Professional Memberships

Papers

  • Single-axis gold micro-electro-mechanical-systems capacitive accelerometer with circular proof-mass for suppressing warpage

    Masako Okumura, Tomoyuki Kurioka, Torauto Yamada, Tatsuhiko Mori, Katsuyuki Machida, Chun-Yi Chen, Tso-Fu Mark Chang, Hiroyuki Ito, Yoshihiro Miyake, Masato Sone

    Japanese Journal of Applied Physics   2026.2

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    Publishing type:Research paper (scientific journal)   Publisher:IOP Publishing  

    Abstract

    This paper describes the structural stability and device characteristics of a single-axis gold proof-mass MEMS (micro-electro-mechanical-systems) capacitive accelerometer fabricated using Ti/Au multilayer metal technology. We propose a circular proof-mass structure to suppress warping deformation of the proof-mass caused by the mismatch in thermal expansion coefficients between Ti and Au. The measured warpage of the fabricated device is less than 1% related to the proof-mass radius. The MEMS capacitive accelerometer shows a valid capacitance-voltage (C-V) response characteristic due to warpage suppression. The experimental measurements determine its sensitivity and Brownian noise at 2.3 pF g−1 and 0.17 μg Hz−1/2, respectively. These values satisfy the specification for the detection of μg-level acceleration. It is confirmed that the use of the circular proof-mass structure for the MEMS capacitive accelerometers realizes its structural stability with high sensitivity.

    DOI: 10.35848/1347-4065/ae4687

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    Other Link: https://iopscience.iop.org/article/10.35848/1347-4065/ae4687/pdf

  • Effect of Supercritical Carbon Dioxide Emulsification on Nickel Electroplating in Sulfamate Baths at Various CO 2 Volume Fractions

    Wending Hou, Chun-Yi Chen, Tomoyuki Kurioka, Katsuyuki Machida, Hiroyuki Ito, Yoshihiro Miyake, Tso-Fu Mark Chang, Masato Sone

    Journal of The Electrochemical Society   173 ( 3 )   032501 - 032501   2026.1

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    Publishing type:Research paper (scientific journal)   Publisher:The Electrochemical Society  

    This study examines nickel electroplating in supercritical carbon dioxide (scCO 2 )-emulsified nickel sulfamate baths, focusing on the effects of CO 2 volume fractions (10–80 vol.%) at a current density of 0.12 A cm −2 . The inclusion of scCO 2 significantly enhanced film quality, even at high CO 2 concentrations. However, Faradaic efficiency (FE) decreased from 95% to 75% as CO 2 volume fractions increased, attributed to intensified hydrogen evolution reactions (HER) caused by more negative deposition potentials and the insulating scCO 2 dispersed phase. Electrochemical analysis revealed pronounced potential fluctuations at higher CO 2 fractions due to intermittent electrode contact with the dispersed phase, which amplified HER and reduced the effective plating area. The conductivity of the scCO 2 -emulsified bath followed the Maxwell–Garnett model, indicating isolated scCO 2 dispersed phases in a conductive medium. Despite reductions in FE and Vickers hardness (from 750 to 580 Hv), the films maintained smooth surfaces and fine grain sizes (∼10 nm). These results demonstrate the potential of scCO 2 emulsification to produce high-quality nickel coatings and provide a framework for advancing electroplating in complex multiphase electrolytes.

    DOI: 10.1149/1945-7111/ae3b15

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    Other Link: https://iopscience.iop.org/article/10.1149/1945-7111/ae3b15/pdf

  • Evaluation of annealing effects on the deformation of Ti/Au multi-layered micro-cantilevers

    Ryosuke Miyai, Tomoyuki Kurioka, Chun-Yi Chen, Tso-Fu Mark Chang, Katsuyuki Machida, Hiroyuki Ito, Yoshihiro Miyake, Masato Sone

    Micro and Nano Engineering   100333 - 100333   2025.11

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    Publishing type:Research paper (scientific journal)   Publisher:Elsevier BV  

    DOI: 10.1016/j.mne.2025.100333

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  • Evaluation of the Annealing Induced Warpage of an Electrodeposited-Au Octagonal Proof Mass with a Ti/Au Multi-Layered Structure toward MEMS Capacitive Accelerometers

    Tatsuhiko Mori, Tomoyuki Kurioka, Chun-Yi Chen, Tso-Fu Mark Chang, Katsuyuki Machida, Hiroyuki Ito, Yoshihiro Miyake, Masato Sone

    Journal of The Electrochemical Society   2025.10

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    Publishing type:Research paper (scientific journal)   Publisher:The Electrochemical Society  

    Abstract

    Annealing effects of the fabrication process on the concave warpage deformation of an electrodeposited-Au octagonal proof mass with a Ti/Au multi-layered structure are reported. The octagonal proof mass is fabricated by using multi-layer metal technology, which consists of the gold electrodeposition and sacrificial film formation. The annealing at and below 150 °C hardly deforms the octagonal proof mass, whereas the annealing at 200 °C induces its concave warpage deformation, and the increase in the annealing temperature causes greater deformation. On the other hand, even after the annealing at 300 °C, the warpage of the octagonal proof mass remains 1% of the length from the center to the periphery of the octagonal proof mass. Also, the measured warpage is found to be approximately one-seventh that of the electrodeposited-Au square proof mass with the almost same size. These results reveal that the octagonal shape is advantageous in the suppression of the warpage deformation of the proof mass.

    DOI: 10.1149/1945-7111/ae11d5

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    Other Link: https://iopscience.iop.org/article/10.1149/1945-7111/ae11d5/pdf

  • Void-Free Smooth Nickel Electrodeposition with Supercritical Carbon Dioxide Emulsified Sulfamate Bath in High Current Density

    Wending Hou, Chun-Yi Chen, Tomoyuki Kurioka, Katsuyuki Machida, Hiroyuki Ito, Yoshihiro Miyake, Tso-Fu Mark Chang, Masato Sone

    Journal of The Electrochemical Society   2025.9

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    Publishing type:Research paper (scientific journal)   Publisher:The Electrochemical Society  

    Abstract

    Supercritical carbon dioxide (scCO₂) emulsions are used in the electrodeposition of nickel from a nickel sulfamate bath at current densities ranging from 0.03 to 0.36 A/cm². ScCO₂ emulsions are formed by mixing scCO₂, surfactants, and the aqueous nickel sulfamate bath. Nickel films obtained by electrodeposition with scCO₂ emulsions (ESCE) were compared to those produced by conventional electrodeposition (CONV). The use of scCO₂ emulsions improves the quality of the nickel film, even at high current densities up to 0.36 A/cm², as evidenced by reduced grain size and decreased surface roughness. The Faradaic efficiency (FE) of the deposition reaction by CONV gradually decreased from 95% to 90% as the current density increased from 0.03 to 0.36 A/cm², while the FE by ESCE decreased from 82% to 70%. The lowered FE is suggested to result from promoted hydrogen evolution due to the introduction of scCO₂ emulsions. Grain refinement and an increased Vickers hardness value of up to 780 HV are attributed to the periodic plating characteristic mechanism.

    DOI: 10.1149/1945-7111/ae05cf

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    Other Link: https://iopscience.iop.org/article/10.1149/1945-7111/ae05cf/pdf

  • Design and evaluation of a dual-detection range single-axis MEMS capacitive accelerometer with gold proof-mass structure for suppressed warpage

    Devi Srujana Tenneti, Chihaya Mukaide, Kisuke Miyado, Torauto Yamada, Katsuyuki Machida, Tomoyuki Kurioka, Tso-Fu Mark Chang, Masato Sone, Yoshihiro Miyake, Hiroyuki Ito

    Japanese Journal of Applied Physics   2025.3

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    Publishing type:Research paper (scientific journal)   Publisher:IOP Publishing  

    Abstract

    This paper presents a dual-detection range single-axis MEMS accelerometer and an octagonal gold proof-mass structure, which suppresses the proof-mass warpage caused during MEMS process. It comprises two devices; One device offers a detection range of 0.1g–10g (1g = 9.8m/s2), while the other, a large, hollow structure surrounding the central device, operates in µg level-0.1g. Simulation results clarify warpage suppression, even with a large hollow design. Based on the simulation, a MEMS accelerometer is designed and fabricated using multilayer-metal technology. The measurements confirm that the warpage in the fabricated device is suppressed from 27µm to 4µm. A Brownian noise and sensitivity of 0.13µg/√Hz and 1.8pF/g, respectively, are obtained for µg level-0.1g detection range. For the other device, the Brownian noise is 0.47µg/√Hz and the sensitivity is 5.3×10-2pF/g in the 0.1g-1g range and 6.9×10-2pF/g in the 1g–10g range. Therefore, the proposed proof-mass structure is effective for achieving the dual-detection range MEMS accelerometer.

    DOI: 10.35848/1347-4065/adc3a0

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    Other Link: https://iopscience.iop.org/article/10.35848/1347-4065/adc3a0/pdf

  • Simultaneous Necking and Barreling Deformation Behaviors in Bending of Single-Crystal Gold Micro-Cantilever

    Kazuya Fujita, Kosuke Suzuki, Keisuke Asano, Chun-Yi Chen, Tomoyuki Kurioka, Katsuyuki Machida, Hiroyuki Ito, Yoshihiro Miyake, Masato Sone, Tso-Fu Mark Chang

    Materials   17 ( 16 )   4054 - 4054   2024.8

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    Publishing type:Research paper (scientific journal)   Publisher:MDPI AG  

    Necking and barreling deformation behaviors occurred simultaneously during the bending test of a single-crystal gold micro-cantilever (sample A) with the loading direction parallel to the [1-10] orientation and the neutral plane parallel to the [110] orientation. In contrast, for another single-crystal gold micro-cantilever, sample B, with the loading direction aligned parallel to the [0.37 −0.92 0.05] orientation and the neutral plane parallel to the [0.54 0.28 0.78] orientation, predominant slip band deformation was noted. Sample A exhibited activation of four slip systems, whereas sample B demonstrated activity in only a single-slip system. This difference suggests that the presence of multiple slip systems contributes to the concurrent occurrence of necking and barreling deformations. Furthermore, variations in the thickness of the micro-cantilevers resulted in observable strengthening, indicating that the effect of sample size is intricately linked to the geometry of the cross-section, which we have termed the “sample geometry effect”.

    DOI: 10.3390/ma17164054

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  • Cross-sectional geometry effect on bending strength of gold micro-cantilever with trapezoidal cross-section

    Ryohei Hori, Kazuya Fujita, Chun Yi Chen, Tomoyuki Kurioka, Jhen-Yang Wu, Tso-Fu Mark Chang, Katsuyuki Machida, Hiroyuki Ito, Yoshihiro Miyake, Masato Sone

    Micro and Nano Engineering   23   100259 - 100259   2024.6

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    Publishing type:Research paper (scientific journal)   Publisher:Elsevier BV  

    DOI: 10.1016/j.mne.2024.100259

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  • Effects of the strain rate in compression of electrodeposited gold micro-pillars toward the design of MEMS components Reviewed

    Syota Kanno, Taro Omura, Tomoyuki Kurioka, Chun-Yi Chen, Parthojit Chakraborty, Katsuyuki Machida, Hiroyuki Ito, Yoshihiro Miyake, Masato Sone, Tso-Fu Mark Chang

    Micro and Nano Engineering   100254   2024.4

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    Language:English  

    DOI: 10.1016/j.mne.2024.100254

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  • Warpage Study of Electrodeposited-Au Micro-Components with Ti/Au Multi-Layered Structures toward MEMS Applications

    Taro Omura, Tomoyuki Kurioka, Chun Yi Chen, Tso Fu Mark Chang, Akira Onishi, Parthojit Chakraborty, Katsuyuki Machida, Hiroyuki Ito, Yoshihiro Miyake, Masato Sone

    Journal of the Electrochemical Society   171 ( 3 )   2024.3

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    Publishing type:Research paper (scientific journal)  

    DOI: 10.1149/1945-7111/ad2ba9

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  • Serpentine spring design technique for high sensitivity MEMS capacitive accelerometer fabricated by gold multi-layer metal technology

    Kisuke Miyado, Devi Srujana Tenneti, Akira Onishi, Katsuyuki Machida, Tomoyuki Kurioka, Tso-Fu Mark Chang, Masato Sone, Yoshihiro Miyake, Hiroyuki Ito

    Japanese Journal of Applied Physics   63 ( 4 )   04SP23 - 04SP23   2024.3

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    Publishing type:Research paper (scientific journal)   Publisher:IOP Publishing  

    Abstract

    This paper describes a design technique for serpentine spring with the edge span beam L/2. In order to improve design accuracy, we investigate the key structure parameters influenced by the fabrication process for MEMS device, comparing finite element analysis (FEA) and analytical models. It is found that the Fedder model as the analytical model is suitable for the spring constant characteristics of FEA with the edge span beam L/2. Further, the thickness and width are found to be the key structure parameters and the dominant factor of variation regarding the serpentine spring. Based on the analysis, we propose a spring design technique. The experimental results show that the variation between the measured data of 4.46 N m−1 and the design value of 4.15 N m−1 was 7.5%, satisfying the target of ±10%. It is confirmed that the proposed technique can establish the serpentine spring for high sensitivity gold proof-mass MEMS accelerometers.

    DOI: 10.35848/1347-4065/ad2913

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    Other Link: https://iopscience.iop.org/article/10.35848/1347-4065/ad2913/pdf

  • Dependence of structural design on effective Young's Modulus of Ti/Au multi-layered micro-cantilevers Reviewed

    Shunkai Watanabe, Tomoyuki Kurioka, Chun-Yi Chen, Tso-Fu Mark Chang, Akira Onishi, Parthojit Chakraborty, Katsuyuki Machida, Hiroyuki Ito, Yoshihiro Miyake, Masato Sone

    Micro and Nano Engineering   29   100249   2024.3

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    Language:English   Publishing type:Research paper (scientific journal)  

    DOI: 10.1016/j.mne.2024.100249

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  • Clarification of geometric effects on long-term structural stability of Ti/au multi-layered Micro-cantilevers

    Ryosuke Miyai, Tomoyuki Kurioka, Chun-Yi Chen, Tso-Fu Mark Chang, Akira Onishi, Parthojit Chakraborty, Katsuyuki Machida, Hiroyuki Ito, Yoshihiro Miyake, Masato Sone

    Micro and Nano Engineering   100244 - 100244   2024.3

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    Publishing type:Research paper (scientific journal)   Publisher:Elsevier BV  

    DOI: 10.1016/j.mne.2024.100244

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  • Impurity Analysis of Electroplated Gold Components with Multi-Layered Structures by Thermal Desorption Spectrometry toward Application in Gold Micro Electro Mechanical System Capacitive Accelerometers Reviewed

    Takumi Akiyama, Tomoyuki Kurioka, Chun-Yi Chen, Tso-Fu Mark Chang, Parthojit Chakraborty, Katsuyuki Machida, Hiroyuki Ito, Yoshihiro Miyake, Masato Sone

    Micro and Nano Engineering   21   100226 - 100226   2023.9

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    Language:English   Publishing type:Research paper (scientific journal)   Publisher:Elsevier BV  

    DOI: 10.1016/j.mne.2023.100226

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  • Correlation of Sample Geometry and Grain Size in Micro-Bending of Electrodeposited Polycrystalline Gold Invited Reviewed

    Kosuke Suzuki, Yiming Jiang, Ryohei Hori, Ken Hashigata, Tomoyuki Kurioka, Chun-Yi Chen, Tso-Fu Mark Chang, Parthojit Chakraborty, Katsuyuki Machida, Hiroyuki Ito, Yoshihiro Miyake, Masato Sone

    Materials Today Communications   35   106072 - 106072   2023.4

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    Language:English   Publishing type:Research paper (scientific journal)   Publisher:Elsevier BV  

    DOI: 10.1016/j.mtcomm.2023.106072

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  • Gold Single-Axis Differential Capacitive MEMS Accelerometer With Proof-Mass Position Control Electrode Fabricated by Post-CMOS Technology

    Akira Onishi, Kisuke Miyado, Devi Srujana Tenneti, Katsuyuki Machida, Parthojit Chakraborty, Masato Sone, Yoshihiro Miyake, Hiroyuki Ito

    IEEE 2023 INERTIAL   2023.3

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    Language:English   Publishing type:Research paper (scientific journal)  

    DOI: 10.1109/INERTIAL56358.2023.10103943

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  • Detection system for Legionella bacteria using photogate-type optical sensor Reviewed

    Yuto Honda, Ryosuke Ichikawa, Yong Joon Choi, Kensuke Murakami, Kazuhiro Takahashi, Toshihiko Noda, Kazuaki Sawada, Hiromu Ishii, Katsuyuki Machida, Hiroyuki Ito, Satoshi Miyahara, Yasuhiko Nikaido, Mitsumasa Saito

    Japanese Journal of Applied Physics   61 ( SD )   2022.6

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    Language:English   Publishing type:Research paper (scientific journal)  

    DOI: 10.35848/1347-4065/ac5a25

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  • Simplified Analytical Damping Constant Model for Design of MEMS Capacitive Accelerometer with Gold Perforated Proof-mass Structure Reviewed

    Kohei Shibata, Akihiro Uchiyama, Akira Onishi, Katsuyuki Machida, Shin-ichi Iida, Toshifumi Konishi, Masato Sone, Yoshihiro Miyake, Hiroyuki Ito

    IEEE Sensors Journal   2022.6

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    Language:English   Publishing type:Research paper (scientific journal)  

    DOI: 10.1109/JSEN.2022.3184340

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  • Suppressed drift and low-noise sensor module with a single-axis gold proof-mass MEMS accelerometer for micro muscle sound measurement

    Akira Onishi, Kohei Shibata, Akihiro Uchiyama, Katsuyuki Machida, Taiki Ogata, Noboru Ishihara, Hirotaka Uchitomi, Tso-Fu Mark Chang, Masato Sone, Yoshihiro Miyake, Hiroyuki Ito

    Japanese Journal of Applied Physics   61 ( SD )   2022.3

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    Language:English   Publishing type:Research paper (scientific journal)  

    DOI: 10.35848/1347-4065/ac5b25

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    Other Link: https://iopscience.iop.org/article/10.35848/1347-4065/ac5b25/pdf

  • Effect of current density on micro-mechanical property of electrodeposited gold film evaluated by micro-compression Reviewed

    Taro Omura, Chun-Yi Chen, Tso-Fu Mark Chang, Daisuke Yamane, Hiroyuki Ito, Katsuyuki Machida, Kazuya Masu, Masato Sone

    Surface and Coatings Technology   436   128315 - 128315   2022.3

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    Language:English   Publishing type:Research paper (scientific journal)  

    DOI: 10.1016/j.surfcoat.2022.128315

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  • A MEMS ACCELEROMETER with A SINGLE AXIS TWO PROOF MASSES for A WIDE DETECTION RANGE

    Akihiro Uchiyama, Takashi Ichikawa, Kohei Shibata, Shin-Ichi Iida, Sangyeop Lee, Noboru Ishihara, Katsuyuki MacHida, Kazuya Masu, Hiroyuki Ito

    21st International Conference on Solid-State Sensors, Actuators and Microsystems, TRANSDUCERS 2021   112 - 115   2021.6

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    Language:English   Publishing type:Research paper (international conference proceedings)   Publisher:Institute of Electrical and Electronics Engineers Inc.  

    DOI: 10.1109/Transducers50396.2021.9495507

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  • Effective Young’s Modulus of Complex Three Dimensional Multilayered Ti/Au Micro-Cantilevers Fabricated by Electrodeposition and the Temperature Dependency Invited Reviewed

    Hitomi Watanabe, Tso-Fu Mark Chang, Michael Schneider, Ulrich Schmid, Chun-Yi Chen, Shinichi Iida, Daisuke Yamane, Hiroyuki Ito, Katsuyuki Machida, Kazuya Masu, Masato Sone

    Electrochem   2021.4

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    Publishing type:Research paper (scientific journal)  

    DOI: 10.3390/electrochem2020015

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  • A 3-D Capacitive-Detection Electrode for a Single Gold Proof-Mass Three-Axis MEMS Accelerometer

    Takashi Ichikawa, Akihiro Uchiyama, Kohei Shibata, Shinichi Iida, Sangyeop Lee, Noboru Ishihara, Katsuyuki Machida, Kazuya Masu, Hiroyuki Ito

    INERTIAL 2021 - 8th IEEE International Symposium on Inertial Sensors and Systems, Proceedings   2021.3

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    Publishing type:Research paper (international conference proceedings)  

    DOI: 10.1109/INERTIAL51137.2021.9430475

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  • Special section on analog circuit techniques and related topics

    Hiroki Ishikuro, Hiroyuki Ito, Takashi Sato, Takahide Sato, Hao San, Hiroo Sekiya, Nicodimus Retdian, Akira Hyogo, Yoshitaka Hirai, Yasuyuki Matsuya, Cosy Muto, Akira Yasuda, Taizo Yamawaki, Takeshi Yoshida

    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E104A ( 2 )   476   2021.2

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    Publishing type:Research paper (scientific journal)  

    DOI: 10.1587/transfun.2020GCF0001

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  • A Highly Sensitive MEMS Accelerometer Module for Measuring Micro Muscular Sounds

    Hiroyuki Ito, Katsuyuki MacHida, Noboru Ishihara, Yoshihiro Miyake, Kazuya Masu

    ECS Transactions   104 ( 4 )   83 - 91   2021

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    Language:English   Publishing type:Research paper (international conference proceedings)   Publisher:IOP Publishing Ltd  

    DOI: 10.1149/10404.0083ecst

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  • Effects of Sample Geometry and Grain Size on Mechanical Property of Electrodeposited Gold Evaluated By Micro-Bending Test Reviewed

    Kosuke Suzuki, Yu-An Chien, Ken Hashigata, Keisuke Asano, Chun-Yi Chen, Tso-Fu Mark Chang, Daisuke Yamane, Hiroyuki Ito, Katsuyuki Machida, Kazuya Masu, Masato Sone

    ECS Meeting Abstracts   2020.11

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    Publishing type:Research paper (scientific journal)  

    DOI: 10.1149/MA2020-02653306mtgabs

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  • Effects of Sample Geometry on Micro-Mechanical Property of Single Crystal Gold for Applications in Microelectronics Reviewed

    Kazuya Fujita, Kosuke Suzuki, Chun-Yi Chen, Tso-Fu Mark Chang, Hiroyuki Ito, Katsuyuki Machida, Kazuya Masu, Masato Sone

    ECS Meeting Abstracts   2020.11

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    Publishing type:Research paper (scientific journal)  

    DOI: 10.1149/MA2020-02653307mtgabs

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  • Co-Electrodeposition of Au–TiO2 Nanocomposite and the Micro-Mechanical Properties Reviewed

    Yu-An Chien, Tso-Fu Mark Chang, Chun-Yi Chen, Daisuke Yamane, Hiroyuki Ito, Katsuyuki Machida, Kazuya Masu, Masato Sone

    Electrochem   1 ( 4 )   388 - 393   2020.11

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    Language:English   Publishing type:Research paper (scientific journal)   Publisher:MDPI AG  

    Strengthening of electrodeposited Au-based materials is achieved by co-electrodeposition with TiO2 nanoparticles dispersed in a sulfide-based gold electrolyte. TiO2 content in the composite film is adjusted by concentration of the TiO2 in the gold electrolyte. Effects of the TiO2 content on surface morphology, crystalline structure and microstructure of the composite film are investigated. Mechanical properties of the Au–TiO2 composite films are evaluated by micro-Vickers hardness and micro-compression tests. The hardness increases from 135 to 207 HV when the TiO2 content is increased from 0 to 2.72 wt%. Specimens used in the micro-compression test are micro-pillars fabricated from the composite film, and the yield strength reaches 0.84 GPa by incorporating 2.72 wt% TiO2 into the film.

    DOI: 10.3390/electrochem1040025

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  • Sample geometry effect on mechanical property of gold micro-cantilevers by micro-bending test

    Kosuke Suzuki, Tso-Fu Mark Chang, Ken Hashigata, Keisuke Asano, Chun-Yi Chen, Takashi Nagoshi, Daisuke Yamane, Hiroyuki Ito, Katsuyuki Machida, Kazuya Masu, Masato Sone

    MRS Communications   1 - 5   2020.6

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    Publishing type:Research paper (scientific journal)   Publisher:Cambridge University Press (CUP)  

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    DOI: 10.1557/mrc.2020.38

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  • A 100-nG/√ Hz-Level Single Au Proof-Mass 3-Axis MEMS Accelerometer with Pillar-Shaped electrodes

    Takashi Ichikawa, Ken Atsumi, Tatsuya Koga, Hiroyuki Ito, Shin Ichi Iida, Noboru Ishihara, Daisuke Yamane, Katsuyuki Machida, Kazuya Masu

    2020 Symposium on Design, Test, Integration and Packaging of MEMS and MOEMS, DTIP 2020   2020.6

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    Publishing type:Research paper (international conference proceedings)  

    DOI: 10.1109/DTIP51112.2020.9139134

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  • Electrodeposition of Au-Cu Alloys and the Micro-Mechanical Properties Reviewed

    Tso-Fu Mark Chang, Haochun Tang, Chun-Yi Chen, Daisuke Yamane, Hiroyuki Ito, Katsuyuki Machida, Kazuya Masu, Masato Sone

    ECS Meeting Abstracts   {MA}2020-01 ( 20 )   1233 - 1233   2020.5

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    Publishing type:Research paper (scientific journal)   Publisher:The Electrochemical Society  

    DOI: 10.1149/MA2020-01201233mtgabs

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  • CMOS-MEMS based microgravity sensor and its application

    Kazuya Masu, Katsuyuki Machida, Daisuke Yamane, Hiroyuki Ito, Noboru Ishihara, Tso Fu Mark Chang, Masato Sone, Ryo Shigeyama, Taiki Ogata, Yoshihiro Miyake

    ECS Transactions   97 ( 5 )   91 - 108   2020.4

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    Publishing type:Research paper (international conference proceedings)  

    DOI: 10.1149/09705.0091ecst

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  • A Gold Proof-Mass Differential MEMS Accelerometer for Micro-G Level Sensing

    Tatsuya Koga, Takashi Ichikawa, Daisuke Yamane, Shinichi Iida, Noboru Ishihara, Hiroyuki Ito, Katsuyuki Machida, Kazuya Masu

    INERTIAL 2020 - 7th IEEE International Symposium on Inertial Sensors and Systems, Proceedings   2020.3

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    Publishing type:Research paper (international conference proceedings)  

    DOI: 10.1109/INERTIAL48129.2020.9090069

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  • Alloy Electroplating and Young's Modulus Characterization of AuCu Alloy Microcantilevers

    Kyotaro Nitta, Tso Fu Mark Chang, Haochun Tang, Chun Yi Chen, Shinichi Iida, Daisuke Yamane, Katsuyuki MacHida, Hiroyuki Ito, Kazuya Masu, Masato Sone

    Journal of the Electrochemical Society   167 ( 8 )   2020.1

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    DOI: 10.1149/1945-7111/ab8805

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  • Distributed Sensing Via Inductively Coupled Single-Transistor Chaotic Oscillators: A New Approach and Its Experimental Proof-of-Concept.

    Ludovico Minati, Korkut Kaan Tokgoz, Mattia Frasca, Yasuharu Koike, Jacopo Iannacci, Natsue Yoshimura, Kazuya Masu, Hiroyuki Ito

    IEEE Access   8   36536 - 36555   2020

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    DOI: 10.1109/ACCESS.2020.2976139

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  • Distributed Sensing Via Inductively Coupled Single-Transistor Chaotic Oscillators: A New Approach and Its Experimental Proof-of-Concept

    Ludovico Minati, Korkut Kaan Tokgoz, Mattia Frasca, Yasuharu Koike, Jacopo Iannacci, Natsue Yoshimura, Kazuya Masu, Hiroyuki Ito

    IEEE Access   8   36536 - 36555   2020

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    DOI: 10.1109/ACCESS.2020.2976139

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  • High-Sensitivity Inertial Sensor Module to Measure Hidden Micro Muscular Sounds

    Tatsuya Koga, Katsuyuki Machida, Yoshihiro Miyake, Kazuya Masu, Takashi Ichikawa, Naoto Tanaka, Taiki Ogata, Hiroki Ora, Daisuke Yamane, Noboru Ishihara, Hiroyuki Ito, Masato Sone

    BioCAS 2019 - Biomedical Circuits and Systems Conference, Proceedings   2019.10

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    DOI: 10.1109/BIOCAS.2019.8919151

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  • Fabrication of Au-Cu Alloy/Ti Layered Micro-Cantilevers and the Long-Term Structure Stability

    Kyotaro Nitta, Masato Sone, Haochun Tang, Chun Yi Chen, Tso Fu Mark Chang, Daisuke Yamane, Shinichi Iida, Katsuyuki Machida, Hiroyuki Ito, Kazuya Masu

    Proceedings of IEEE Sensors   2019-October   2019.10

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    DOI: 10.1109/SENSORS43011.2019.8956496

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  • Nanoscale hierarchical structure of twins in nanograins embedded with twins and the strengthening effect

    Haochun Tang, Tso Fu Mark Chang, Yaw Wang Chai, Chun Yi Chen, Takashi Nagoshi, Daisuke Yamane, Hiroyuki Ito, Katsuyuki Machida, Kazuya Masu, Masato Sone

    Metals   9 ( 9 )   2019.9

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    DOI: 10.3390/met9090987

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  • Cu-alloying effect on structure stability of electrodeposited gold-based micro-cantilever evaluated by long-term vibration test

    Kyotaro Nitta, Tso Fu Mark Chang, Koichiro Tachibana, Haochun Tang, Chun Yi Chen, Shinichi Iida, Daisuke Yamane, Hiroyuki Ito, Katsuyuki Machida, Kazuya Masu, Masato Sone

    Microelectronic Engineering   215   2019.7

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    DOI: 10.1016/j.mee.2019.111001

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  • Strengthening of micro-cantilever by Au/Ti bi-layered structure evaluated by micro-bending test toward MEMS devices

    Ken Hashigata, Tso Fu Mark Chang, Haochun Tang, Chun Yi Chen, Daisuke Yamane, Toshifumi Konishi, Hiroyuki Ito, Katsuyuki Machida, Kazuya Masu, Masato Sone

    Microelectronic Engineering   213   13 - 17   2019.5

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    DOI: 10.1016/j.mee.2019.04.008

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  • Pillar-Shaped Electrodes for 3-axis Gold-Proof-Mass MEMS Capacitive Accelerometers

    Ken Atsumi, Shota Otobe, Tatsuya Koga, Takashi Ichikawa, Daisuke Yamane, Shinichi Iida, Hiroyuki Ito, Noboru Ishihara, Masato Sone, Katsuyuki Machida, Kazuya Masu

    2019 Symposium on Design, Test, Integration and Packaging of MEMS and MOEMS, DTIP 2019   2019.5

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    DOI: 10.1109/DTIP.2019.8752744

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  • Long-term structure stability of Ti/Au layered micro-cantilever evaluated by vibration test

    Koichiro Tachibana, Tso Fu Mark Chang, Chun Yi Chen, Daisuke Yamane, Toshifumi Konishi, Hiroyuki Ito, Katsuyuki Machida, Kazuya Masu, Masato Sone

    Microelectronic Engineering   207   33 - 36   2019.2

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    DOI: 10.1016/j.mee.2019.01.002

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  • Causal Characteristic Impedance Determination Using Calibration Comparison and Propagation Constant

    Shuhei Amakawa, Atsushi Takeshige, Shinsuke Hara, Ruibing Dong, Sangyeop Lee, Takeshi Yoshida, Minoru Fujishima, Kazuya Masu, Hiroyuki Ito

    2019 92nd ARFTG Microwave Measurement Conference: Next Generation Microwave and Millimeter-Wave Measurement Techniques and Systems, ARFTG 2019   2019.2

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    DOI: 10.1109/ARFTG.2019.8637225

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  • A 3-D Parallel-Plate MEMS Accelerometer with a Gold Proof Mass

    Daisuke Yamane, Shota Otobe, Ken Atsumi, Tatsuya Koga, Toshifumi Konishi, Teruaki Safu, Shinichi Iida, Hiroyuki Ito, Noboru Ishihara, Katsuyuki Machida, Kazuya Masu

    Proceedings of the IEEE International Conference on Micro Electro Mechanical Systems (MEMS)   2019-January   684 - 687   2019.1

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    DOI: 10.1109/MEMSYS.2019.8870627

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  • A MEMS accelerometer for sub-Mg sensing

    Daisuke Yamane, Toshifumi Konishi, Teruaki Safu, Hiroshi Toshiyoshi, Masato Sone, Katsuyuki Machida, Hiroyuki Ito, Kazuya Masu

    Sensors and Materials   31 ( 9 )   2883 - 2894   2019

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    Publishing type:Research paper (scientific journal)  

    DOI: 10.18494/SAM.2019.2122

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  • MEMS accelerometer fabricated by gold multi-layer metal technology

    K. Machida, D. Yamane, T. Konishi, S. Iida, N. Ishihara, T. M. Chang, M. Sone, H. Ito, K. Masu

    ECS Transactions   92 ( 4 )   169 - 184   2019

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    DOI: 10.1149/09204.0I69ecst

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  • High strength electrodeposited Au-Cu alloys evaluated by bending test toward movable micro-components

    Keisuke Asano, Tso Fu Mark Chang, Haochun Tang, Takashi Nagoshi, Chun Yi Chen, Daisuke Yamane, Hiroyuki Ito, Katsuyuki Machida, Kazuya Masu, Masato Sone

    ECS Journal of Solid State Science and Technology   8 ( 8 )   P412 - P415   2019

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    DOI: 10.1149/2.0151908jss

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  • Current-Starved Cross-Coupled CMOS Inverter Rings as Versatile Generators of Chaotic and Neural-Like Dynamics Over Multiple Frequency Decades.

    Ludovico Minati, Mattia Frasca, Natsue Yoshimura, Leonardo Ricci, Pawel Oswiecimka, Yasuharu Koike, Kazuya Masu, Hiroyuki Ito

    IEEE Access   7   54638 - 54657   2019

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    DOI: 10.1109/ACCESS.2019.2912903

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  • 口腔内荷重計測のための超低消費電力ワイヤレスセンサノードの検討

    伊藤 浩之, 石原 昇, 道正 志郎, 益 一哉, 依田 信裕, 佐々木 啓一

    生体医歯工学共同研究拠点成果報告書   平成29年度   163 - 163   2018.4

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  • Temperature Dependence on Package Sealing Ambient of MEMS Inertial Sensor Fabricated by Multi-layer Metal Technology

    Konishi Toshifumi, Yamane Daisuke, Safu Teruaki, Chen Chun-Yi, Chang Tso-Fu Mark, Ito Hiroyuki, Dosho Shiro, Ishihara Noboru, Sone Masato, Machida Katsuyuki, Masu Kazuya, Iida Shinichi

    JSAP Annual Meetings Extended Abstracts   2018.1   3125 - 3125   2018.3

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    DOI: 10.11470/jsapmeeting.2018.1.0_3125

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  • Microgravity generation using tilting board for resolution evaluation of MEMS accelerometer

    Motohiro Takayasu, Ippei Tsuji, Hiroyuki Ito, Daisuke Yamane, Shiro Dosho, Toshifumi Konishi, Noboru Ishihara, Katsuyuki Machida, Kazuya Masu

    Sensors and Materials   30 ( 12 )   2919 - 2926   2018

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    DOI: 10.18494/SAM.2018.1840

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  • A 0.5 V 5.96-GHz PLL With Amplitude-Regulated Current-Reuse VCO

    Sho Ikeda, Sang Yeop Lee, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu

    IEEE Microwave and Wireless Components Letters   27 ( 3 )   302 - 304   2017.3

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    DOI: 10.1109/LMWC.2017.2662001

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  • Design of high-frequency piezoelectric resonator-based cascaded fractional-N PLL with sub-ppb-order channel adjusting technique

    Yosuke Ishikawa, Sho Ikeda, Hiroyuki Ito, Akifumi Kasamatsu, Takayoshi Obara, Naoki Noguchi, Koji Kamisuki, Yao Jiyang, Shinsuke Hara, Dong Ruibing, Shiro Dosho, Noboru Ishihara, Kazuya Masu

    Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC   43 - 44   2017.2

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    Language:English   Publishing type:Research paper (international conference proceedings)   Publisher:Institute of Electrical and Electronics Engineers Inc.  

    DOI: 10.1109/ASPDAC.2017.7858293

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  • An 8.865-GHz -244dB-FOM high-frequency piezoelectric resonator-based cascaded fractional-N PLL with sub-ppb-order channel adjusting technique

    Sho Ikeda, Hiroyuki Ito, Akifumi Kasamatsu, Yosuke Ishikawa, Takayoshi Obara, Naoki Noguchi, Koji Kamisuki, Yao Jiyang, Shinsuke Hara, Dong Ruibing, Shiro Dosho, Noboru Ishihara, Kazuya Masu

    IEEE Symposium on VLSI Circuits, Digest of Technical Papers   2016-   2016.9

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    Language:English   Publishing type:Research paper (international conference proceedings)   Publisher:Institute of Electrical and Electronics Engineers Inc.  

    DOI: 10.1109/VLSIC.2016.7573548

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  • Environmental data recovery using polynomial regression for large-scale wireless sensor networks

    Kohei Ohba, Yoshihiro Yoneda, Koji Kurihara, Takashi Suganuma, Hiroyuki Ito, Noboru Ishihara, Kunihiko Gotoh, Koichiro Yamashita, Kazuya Masu

    SENSORNETS 2016 - Proceedings of the 5th International Confererence on Sensor Networks   161 - 168   2016

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    Language:English   Publishing type:Research paper (international conference proceedings)   Publisher:SciTePress  

    DOI: 10.5220/0005636901610168

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  • A sub-1G CMOS-MEMS accelerometer

    Daisuke Yamane, Toshifumi Konishi, Motohiro Takayasu, Hiroyuki Ito, Shiro Dosho, Noboru Ishihara, Hiroshi Toshiyoshi, Kazuya Masu, Katsuyuki Machida

    2015 IEEE SENSORS - Proceedings   2015.12

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    DOI: 10.1109/ICSENS.2015.7370303

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  • RF-Powered Transceiver With an Energy- and Spectral-Efficient IF-Based Quadrature Backscattering Transmitter Reviewed

    Atsushi Shirane, Yiming Fang, Haowei Tan, Taiki Ibe, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu

    IEEE JOURNAL OF SOLID-STATE CIRCUITS   50 ( 12 )   2975 - 2987   2015.12

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    DOI: 10.1109/JSSC.2015.2454235

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  • A 0.5-V 1.56-mW 5.5-GHz RF transceiver IC module with J-shaped folded monopole antenna

    Yosuke Ishikawa, Sang Yeop Lee, Shin Yonezawa, Sho Ikeda, Yiming Fang, Taisuke Hamada, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu

    Proceedings - IEEE International Symposium on Circuits and Systems   2015-July   1218 - 1221   2015.7

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    DOI: 10.1109/ISCAS.2015.7168859

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  • An RF energy harvesting power management circuit for appropriate duty-cycled operation

    Atsushi Shirane, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu

    Japanese Journal of Applied Physics   54 ( 4 )   2015.4

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    DOI: 10.7567/JJAP.54.04DE11

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  • 0.5V 5.8GHz highly linear current-reuse voltage-controlled oscillator with back-gate tuning technique Reviewed

    Sho Ikeda, Sang-Yeop Lee, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu

    JAPANESE JOURNAL OF APPLIED PHYSICS   54 ( 4 )   2015.4

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    DOI: 10.7567/JJAP.54.04DE06

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  • A 5.8GHz RF-powered transceiver with a 113μW 32-QAM transmitter employing the IF-based quadrature backscattering technique

    Atsushi Shirane, Haowei Tan, Yiming Fang, Taiki Ibe, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu

    Digest of Technical Papers - IEEE International Solid-State Circuits Conference   58   248 - 249   2015.3

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    DOI: 10.1109/ISSCC.2015.7063019

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  • A 0.5-V 5.8-GHz low-power asymmetrical QPSK/OOK transceiver for wireless sensor network

    Sho Ikeda, Sang Yeop Lee, Shin Yonezawa, Yiming Fang, Motohiro Takayasu, Taisuke Hamada, Yosuke Ishikawa, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu

    20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015   40 - 41   2015.3

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    DOI: 10.1109/ASPDAC.2015.7058976

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  • A 0.52-V 5.7-GHz low noise sub-sampling PLL with dynamic threshold MOSFET

    Sho Ikeda, Sang Yeop Lee, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu

    2014 IEEE Asian Solid-State Circuits Conference, A-SSCC - Proceedings of Technical Papers   365 - 368   2015.1

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    DOI: 10.1109/ASSCC.2014.7008936

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  • An Ultra-Low-Power 32QAM RF Transmitter Reviewed

    Hiroyuki Ito, Atsushi Shirane, Noboru Ishihara, Kazuya Masu

    2015 IEEE INTERNATIONAL SYMPOSIUM ON RADIO-FREQUENCY INTEGRATION TECHNOLOGY (RFIT)   16 - 18   2015

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  • E-band Filters Based on Substrate Integrated Waveguide Octagonal Cavities Loaded by Complementary Split-Ring Resonators Reviewed

    Hamid Kiumarsi, Kenji Wasa, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu

    2015 IEEE MTT-S INTERNATIONAL MICROWAVE SYMPOSIUM (IMS)   2015

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  • A 0.5-V 1.56-mW 5.5-GHz RF Transceiver IC Module with J-Shaped Folded Monopole Antenna Reviewed

    Yosuke Ishikawa, Sangyeop Lee, Shin Yonezawa, Sho Ikeda, Yiming Fang, Taisuke Hamada, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu

    2015 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)   1218 - 1221   2015

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  • A Sub-1 mW Class-C-VCO-Based Low Voltage PLL with Ultra-Low-Power Digitally-Calibrated ILFD in 65 nm CMOS Reviewed

    Sho Ikeda, Sang-yeop Lee, Tatsuya Kamimura, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu

    IEICE TRANSACTIONS ON ELECTRONICS   E97C ( 6 )   495 - 504   2014.6

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    DOI: 10.1587/transele.E97.C.495

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  • An 8 channel, 20V output CMOS switching driver with 3.3V power supply using triple-well biasing techniques for integrated MEMS device control

    Motohiro Takayasu, Atsushi Shirane, Sangyeop Lee, Daisuke Yamane, Hiroyuki Ito, Xiaoyu Mi, Hiroaki Inoue, Fumihiko Nakazawa, Satoshi Ueda, Noboru Ishihara, Kazuya Masu

    Japanese Journal of Applied Physics   53 ( 4 SPEC. ISSUE )   2014.4

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    Publishing type:Research paper (international conference proceedings)  

    DOI: 10.7567/JJAP.53.04EE13

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  • A novel direct injection-locked QPSK modulator based on ring VCO in 180 nm CMOS

    Sang Yeop Lee, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu

    IEEE Microwave and Wireless Components Letters   24 ( 4 )   269 - 271   2014.4

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    DOI: 10.1109/LMWC.2014.2299534

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  • An Ultra Low Power pH-Monitoring IC with a Duty-Cycling Wireless FM-Transmitter Reviewed

    Yusuke Shiino, Hiroyuki Ito, Taku Fujiwara, Noboru Ishihara, Hisashi Yamanouchi, Hiroki Tanabe, Satoshi Nomura, Toshifumi Konishi, Katsuyuki Machida, Kazuya Masu

    2014 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)   882 - 885   2014

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  • An ultra low power pH-monitoring IC with a duty-cycling wireless FM-transmitter

    Yusuke Shiino, Hiroyuki Ito, Taku Fujiwara, Noboru Ishihara, Hisashi Yamanouchi, Hiroki Tanabe, Satoshi Nomura, Toshifumi Konishi, Katsuyuki Machida, Kazuya Masu

    Proceedings - IEEE International Symposium on Circuits and Systems   882 - 885   2014

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    Publishing type:Research paper (international conference proceedings)  

    DOI: 10.1109/ISCAS.2014.6865277

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  • A 2.3 pJ/bit frequency-stable impulse OOK transmitter powered directly by an RF energy harvesting circuit with -19.5 dBm sensitivity

    Hiroyuki Ito, Shoichi Masui, Youichi Momiyama, Atsushi Shirane, Motohiro Takayasu, Yoshihiro Yoneda, Taiki Ibe, Taisuke Hamada, Sho Ikeda, Daisuke Yamane, Noboru Ishihara, Kazuya Masu

    Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium   13 - 16   2014

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    Publishing type:Research paper (international conference proceedings)  

    DOI: 10.1109/RFIC.2014.6851645

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  • A 0.5-V 2.5-GHz High-Gain Low-Power Regenerative Amplifier Based on Colpitts Oscillator Topology in 65-nm CMOS Reviewed

    Taisuke Hamada, Hao Jiang, Yiming Fang, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu

    2014 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS)   340 - 343   2014

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  • An Ultra-Low-Power RF Transceiver with a 1.5-pJ/bit Maximally-Digital Impulse-Transmitter and an 89.5-mu W Super-Regenerative RSSI Reviewed

    Hiroyuki Ito, Yoshihiro Yoneda, Taiki Ibe, Taisuke Hamada, Noboru Ishihara, Kazuya Masu, Shoichi Masui, Youichi Momiyama

    2014 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC)   265 - 268   2014

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  • A 0.5-V 5.8-GHz Ultra-Low-Power RF Transceiver for Wireless Sensor Network in 65 nm CMOS Reviewed

    Sho Ikeda, Sang-Yeop Lee, Shin Yonezawa, Yiming Fang, Motohiro Takayasu, Taisuke Hamada, Yosuke Ishikawa, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu

    2014 IEEE RADIO FREQUENCY INTEGRATED CIRCUITS SYMPOSIUM   29 - 32   2014

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  • A 950 mu W 5.5-GHz Low Voltage PLL with Digitally-Calibrated ILFD and Linearized Varactor Reviewed

    Sho Ikeda, Tatsuya Kamimura, Sangyeop Lee, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu

    2014 19TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC)   23 - 24   2014

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  • Novel sensor structure and its evaluation for integrated complementary metal oxide semiconductor microelectromechanical systems accelerometer

    Toshifumi Konishi, Daisuke Yamane, Takaaki Matsushima, Ghou Motohashi, Ken Kagaya, Hiroyuki Ito, Noboru Ishihara, Hiroshi Toshiyoshi, Katsuyuki Machida, Kazuya Masu

    Japanese Journal of Applied Physics   52 ( 6 PART 2 )   2013.6

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    DOI: 10.7567/JJAP.52.06GL04

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  • Fractionally Injection-Locked Frequency Multiplication Technique with Multi-Phase Ring Voltage-Controlled Oscillator Reviewed

    Sho Ikeda, Sang-yeop Lee, Tatsuya Kamimura, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu

    JAPANESE JOURNAL OF APPLIED PHYSICS   52 ( 4 )   2013.4

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    DOI: 10.7567/JJAP.52.04CE15

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  • A Transformer-Based Current-Reuse QVCO with a Capacitor Coupling Technique in 180 nm CMOS Reviewed

    Sho Ikeda, Tatsuya Kamimura, Sang-yeop Lee, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu

    2013 8TH EUROPEAN MICROWAVE INTEGRATED CIRCUITS CONFERENCE (EUMIC)   93 - 96   2013

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  • A sub-1mw 5.5-GHz PLL with digitally-calibrated ILFD and linearized varactor for low supply voltage operation

    Sho Ikeda, Tatsuya Kamimura, Sangyeop Lee, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu

    Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium   439 - 442   2013

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    DOI: 10.1109/RFIC.2013.6569625

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  • An inductorless cascaded phase-locked loop with pulse injection locking technique in 90 nm CMOS

    Sang Yeop Lee, Hiroyuki Ito, Shuhei Amakawa, Noboru Ishihara, Kazuya Masu

    International Journal of Microwave Science and Technology   2013

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    Publishing type:Research paper (scientific journal)  

    DOI: 10.1155/2013/584341

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  • A 60GHz 3-dB tandem coupler using offset broadside-coupled lines on a silicon substrate

    Kiumarsi Hamid, Ito Hiroyuki, Okada Kenichi, Uemichi Yusuke, Chiba Yasuto, Ishihara Noboru, Masu Kazuya

    IEICE Electron. Express   10 ( 2 )   20120901 - 20120901   2013

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    In this letter, a 60GHz tandem coupler using offset broadside-coupled lines is proposed on a silicon-based integrated passive device technology. Over the frequency band of 57-66GHz, the measured insertion loss, amplitude imbalance, input return loss, isolation and phase error of the designed tandem coupler are better than 0.67dB, 0.31dB, 27.9dB, 29.7dB and 3.7° respectively. To the best of our knowledge the proposed coupler achieves the lowest reported insertion loss and amplitude imbalance for a 3-dB coupler on a silicon substrate at 60GHz band. Furthermore using the even- and odd-mode analysis, the reason for a high directivity of edge-coupled lines and a low coupling level of broadside-coupled lines on the adopted technology is investigated and a solution for increasing the coupling level of broadside-coupled lines is proposed.

    DOI: 10.1587/elex.10.20120901

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  • An arrayed MEMS accelerometer with a wide range of detection

    D. Yamane, T. Konishi, T. Matsushima, G. Motohashi, K. Kagaya, H. Ito, N. Ishihara, H. Toshiyoshi, K. Machida, K. Masu

    2013 Transducers and Eurosensors XXVII: The 17th International Conference on Solid-State Sensors, Actuators and Microsystems, TRANSDUCERS and EUROSENSORS 2013   22 - 25   2013

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    DOI: 10.1109/Transducers.2013.6626691

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  • Sub-1G MEMS accelerometer

    Daisuke Yamane, Toshifumi Konishi, Takaaki Matsushima, Gou Motohashi, Ken Kagaya, Hiroyuki Ito, Nobru Ishihara, Hiroshi Toshiyoshi, Katsuyuki Machida, Kazuya Masu

    Proceedings of IEEE Sensors   2013

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    DOI: 10.1109/ICSENS.2013.6688166

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  • A process-scalable RF transmitter using 90nm and 65nm Si CMOS

    Atsushi Shirane, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu

    2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013   2013

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    DOI: 10.1109/VLDI-DAT.2013.6533878

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  • A multi-band quadrature clock generator with high-pass-filtered pulse injection technique

    Sang Yeop Lee, Tatsuya Kamimura, Shin Yonezawa, Atsushi Shirane, Sho Ikeda, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu

    IEEE Microwave and Wireless Components Letters   23 ( 2 )   96 - 98   2013

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    DOI: 10.1109/LMWC.2013.2239634

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  • A ring-VCO-based injection-locked frequency multiplier with novel pulse generation technique in 65nm CMOS

    Sang Yeop Lee, Norifumi Kanemaru, Sho Ikeda, Tatsuya Kamimura, Satoru Tanoi, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu

    IEICE Transactions on Electronics   E95-C ( 10 )   1589 - 1597   2012.10

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    DOI: 10.1587/transele.E95.C.1589

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  • Planar Solenoidal Inductor in Radio Frequency Micro-Electro-Mechanical Systems Technology for Variable Inductor with Wide Tunable Range and High Quality Factor Reviewed

    Atsushi Shirane, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu

    JAPANESE JOURNAL OF APPLIED PHYSICS   51 ( 5 )   2012.5

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    DOI: 10.1143/JJAP.51.05EE02

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  • An Inverter-Based Wideband Low-Noise Amplifier in 40 nm Complementary Metal Oxide Semiconductor

    Dharmiza Dayang Nur Salmi, Oturu Mototada, Tanoi Satoru, Ito Hiroyuki, Ishihara Noboru, Masu Kazuya

    Jpn J Appl Phys   51 ( 4 )   04DE07 - 04DE07-5   2012.4

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    Multistandard RF chips have been highly demanded for multipurpose wireless applications. However, in RF circuits, a low-noise amplifier (LNA) plays an important role in determining the receiver's performance. In this paper, we present a scalable wideband LNA based on complementary metal oxide semiconductor (CMOS) inverters, employing two bandwidth expansion techniques to achieve a large bandwidth without using inductors. Fabricated by the 40 nm CMOS process, the LNA attains 0.1--8.0 GHz of flat bandwidth with S_{21}=17.5 dB and S_{11}\leq -10 dB. The minimum NF measured is 5.1 dB and the power consumption is 14.3 mW at 1.3 V. The LNA core circuit is as small as 0.001 mm2 since no large passive device is used. A study of LNA scalability has been conducted by comparing the performances of circuits with the same topology fabricated by the 65, 90, and 180 nm CMOS processes.

    DOI: 10.1143/JJAP.51.04DE07

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  • 0.1 v 13 GHz transformer-based quadrature voltage-controlled oscillator with a capacitor coupling technique in 90nm complementary metal oxide semiconductor

    Tatsuya Kamimura, Sang Yeop Lee, Satoru Tanoi, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu

    Japanese Journal of Applied Physics   51 ( 4 PART 2 )   2012.4

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    DOI: 10.1143/JJAP.51.04DE04

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  • A Three-Stage Inverter-Based Stacked Power Amplifier in 65 nm Complementary Metal Oxide Semiconductor Process

    Kiumarsi Hamid, Mizuochi Yutaka, Ito Hiroyuki, Ishihara Noboru, Masu Kazuya

    Jpn J Appl Phys   51 ( 2 )   02BC01 - 02BC01-5   2012.2

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    A three-stage inverter-based stacked power amplifier (PA) in complementary metal oxide semiconductor (CMOS) process is proposed to overcome low breakdown voltage problem of scaled CMOS technologies. Unlike previous reported stacked PAs which radio frequency choke (RFC) was inevitable, we proposed stacked nMOS and pMOS transistors which effectively eliminates use of RFC. By properly setting self-biased circuits' and transistors' parameters, output impedance could reach up to 50 \Omega which together with not employing the RFC makes this topology very appealing for the scalable PA realization. As a proof of concept, a three-stage PA using 65 nm CMOS technology is implemented. With a 6 V power supply for the third stage, the fabricated PA shows a small-signal gain of 36 dB, a saturated output power of 16 dBm and a maximum power added efficiency of 10% at 1 GHz. Using a 7.5 V of power supply, saturated output power reaches 18 dBm. To the best of our knowledge, this is the first reported inverter-based stacked PA.

    DOI: 10.1143/JJAP.51.02BC01

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  • 1.2-17.6 GHz ring-oscillator-based phase-locked loop with injection locking in 65nm complementary metal oxide semiconductor

    Sang Yeop Lee, Hiroyuki Ito, Shuhei Amakawa, Satoru Tanoi, Noboru Ishihara, Kazuya Masu

    Japanese Journal of Applied Physics   51 ( 2 PART 2 )   2012.2

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    DOI: 10.1143/JJAP.51.02BE03

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  • A process-scalable RF transceiver for short range communication in 90 nm Si CMOS

    Atsushi Shirane, Mototada Otsuru, Sang Yeop Lee, Shin Yonezawa, Satoru Tanoi, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu

    Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium   455 - 458   2012

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    DOI: 10.1109/RFIC.2012.6242320

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  • Injection-locked fractional frequency multiplier with automatic reference pulse-selection technique

    Sang Yeop Lee, Hiroyuki Ito, Satoru Tanoi, Noboru Ishihara, Kazuya Masu

    IEICE Electronics Express   9 ( 21 )   1624 - 1629   2012

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    DOI: 10.1587/elex.9.1624

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  • Optimal Design Method for Chip-Area-Efficient CMOS Low-Dropout Regulator Reviewed

    Sho Ikeda, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu

    2012 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS)   332 - 335   2012

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  • A 0.5-V 5.5-GHz Class-C-VCO-Based PLL with Ultra-Low-Power ILFD in 65 nm CMOS Reviewed

    Sho Ikeda, Tatsuya Kamimura, Sangyeop Lee, Norifumi Kanemaru, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu

    2012 IEEE ASIAN SOLID STATE CIRCUITS CONFERENCE (A-SSCC)   357 - 360   2012

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  • A 3-dB quadrature WLP coupler for 60 GHz applications

    Hamid Kiumarsi, Hiroyuki Ito, Noboru Ishihara, Kenichi Okada, Yusuke Uemichi, Yasuto Chiba, Kazuya Masu

    Materials Research Society Symposium Proceedings   1427   8 - 13   2012

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    DOI: 10.1557/opl.2012.1119

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  • An inductorless injection-locked PLL with 1/2- and 1/4-integral subharmonic locking in 90 nm CMOS

    Sang Yeop Lee, Sho Ikeda, Hiroyuki Ito, Satoru Tanoi, Noboru Ishihara, Kazuya Masu

    Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium   189 - 192   2012

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    DOI: 10.1109/RFIC.2012.6242261

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  • Challenges and Opportunities of RF CMOS in Wireless Communication

    MASU Kazuya, AMAKAWA Shuhei, ITO Hiroyuki, ISHIHARA Noboru

    The Journal of the Institute of Electronics, Information, and Communication Engineers   94 ( 5 )   427 - 432   2011.5

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  • RF MEMS planar solenoidal inductor with wide tunability

    Atsushi Shirane, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu

    Advanced Metallization Conference (AMC)   102 - 103   2011

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  • A 21 V output charge pump circuit with appropriate well-bias supply technique in 0.18 μm Si CMOS

    Atsushi Shirane, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu

    2011 International SoC Design Conference, ISOCC 2011   28 - 31   2011

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  • A ring-VCO-based injection-locked frequency multiplier using a new pulse generation technique in 65 nm CMOS

    Norifumi Kanemaru, Sho Ikeda, Tatsuya Kamimura, Sang Yeop Lee, Satoru Tanoi, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu

    2011 International SoC Design Conference, ISOCC 2011   32 - 35   2011

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    DOI: 10.1109/isocc.2011.6138639

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  • Interconnect Design Challenges in Nano CMOS Circuit Reviewed

    Kazuya Masu, Shuhei Amakawa, Hiroyuki Ito, Noboru Ishihara

    TECHNOLOGY EVOLUTION FOR SILICON NANO-ELECTRONICS   470   224 - +   2011

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    DOI: 10.4028/www.scientific.net/KEM.470.224

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  • C-12-60 Investigation of Scalable Wideband RF CMOS Low Noise Amplifier Using Inveter Construction

    Nakajima Tomoya, Ito Hiroyuki, Amakawa Shuhei, Ishihara Noboru, Masu Kazuya

    Proceedings of the IEICE General Conference   2009 ( 2 )   148 - 148   2009.3

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  • A 20 Gb/s 1:4 DEMUX with Near-Rail-to-Rail Logic Swing in 90 nm CMOS process Reviewed

    A. Mineyama, T. Suzuki, H. Ito, S. Amakawa, N. Ishihara, K. Masu

    2009 INTERNATIONAL MICROWAVE WORKSHOP SERIES ON SIGNAL INTEGRITY AND HIGH-SPEED INTERCONNECTS   97 - +   2009

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  • A simple de-embedding method for characterization of on-chip four-port networks

    Shuhei Amakawa, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu

    Advanced Metallization Conference (AMC)   99 - 103   2009

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  • C-12-45 RF CMOS Low Noise Amplifier Dependencies on Process Generation

    Nakajima Tomoya, Ito Hiroyuki, Amakawa Shuhei, Ishihara Noboru, Masu Kazuya

    Proceedings of the Society Conference of IEICE   2008 ( 2 )   114 - 114   2008.9

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  • C-2-14 A CMOS-Inverter-Based Wideband Variable Gain Amplifier

    Sadoshima Susumu, Ito Hiroyuki, Amakawa Shuhei, Ishihara Noboru, Masu Kazuya

    Proceedings of the Society Conference of IEICE   2008 ( 1 )   39 - 39   2008.9

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  • C-2-57 Dependence on Process Generation of CMOS RF Power Amplifier

    Mizuochi Yutaka, Sadoshima Susumu, Ito Hiroyuki, Amakawa Shuhei, Ishibara Noboru, Masu Kazuya

    Proceedings of the Society Conference of IEICE   2008 ( 2 )   126 - 126   2008.9

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  • A-1-12 Wide Band CMOS Differential Type Ring VCO

    Oshita Takao, Ito Hiroyuki, Amakawa Shuhei, Ishihara Noboru, Masu Kazuya

    Proceedings of the Society Conference of IEICE   2008   12 - 12   2008.9

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  • An Over-12-Gbps On-Chip Transmission Line Interconnect with a Pre-Emphasis Technique in 90 nm CMOS Reviewed

    Kazuya Miyashita, Takahiro Ishii, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu

    2008 IEEE-EPEP ELECTRICAL PERFORMANCE OF ELECTRONIC PACKAGING   285 - +   2008

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  • High-frequency characteristics of on-chip wirings up to 110 GHz

    Kazuya Miyashita, Hiroyuki Ito, Kenichi Okada, Kazuya Masu

    Advanced Metallization Conference (AMC)   309 - 313   2008

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  • A Low Phase Noise LC-VCO with a High-Q Inductor Fabricated by Wafer Level Package Technology Reviewed

    Kazuma Ohashi, Yuka Kobayashi, Hiroyuki Ito, Kenichi Okada, Hideki Hatakeyama, Takuya Aizawa, Tatsuya Ito, Ryozo Yamauchi, Kazuya Masu

    2008 IEEE RADIO FREQUENCY INTEGRATED CIRCUITS SYMPOSIUM, VOLS 1 AND 2   107 - +   2008

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  • Small-area CMOS RF distributed mixer using multi-port inductors Reviewed

    Susumu Sadoshima, Satoshi Fukuda, Tackya Yammtouch, Hiroyuki Ito, Kenichi Okada, Kazuya Masu

    2008 ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2   5 - +   2008

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  • A 1.7-GHz 1.5-mW Digitally-Controlled FBAR Oscillator with 0.03-ppb Resolution Reviewed

    H. Ito, H. Lakdawala, A. Ravi, S. Pellerano, R. Ruby, K. Soumyanath, K. Masu

    ESSCIRC 2008: PROCEEDINGS OF THE 34TH EUROPEAN SOLID-STATE CIRCUITS CONFERENCE   98 - +   2008

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  • Signal transmission through interconnects with repetitive loads Reviewed

    Shuhei Amakawa, Hiroyuki Ito, Kazuya Masu

    ADVANCED METALLIZATION CONFERENCE 2007 (AMC 2007)   23   321 - 325   2008

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  • LVDS-type on-chip transmision line interconnect with passive equalizers in 90nm CMOS process Reviewed

    Akiko Mineyama, Hiroyuki Ito, Takahiro Ishii, Kenichi Okada, Kazuya Masu

    2008 ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2   809 - +   2008

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  • An 8Gbps 2.5mW On-Chip Pulsed-Current-Mode Transmission Line Interconnect with a Stacked-Switch Tx Reviewed

    Tomoaki Maekawa, Hiroyuki Ito, Kazuya Masu

    ESSCIRC 2008: PROCEEDINGS OF THE 34TH EUROPEAN SOLID-STATE CIRCUITS CONFERENCE   474 - +   2008

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  • A low-power differential transmission line interconnect using wafer level package technology Reviewed

    Tomoaki Maekawa, Takahiro Ishii, Junki Seita, Hiroyuki Ito, Kenichi Okada, Hideki Hatakeyama, Yusuke Uemichi, Takuya Aizawa, Tatsuya Ito, Ryozo Yamauchi, Kazuya Masu

    2008 IEEE WORKSHOP ON SIGNAL PROPAGATION ON INTERCONNECTS   99 - +   2008

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  • High-frequency characteristics of on-chip wirings up to 110 GHz Reviewed

    Kazuya Miyashita, Hiroyuki Ito, Kenichi Okada, Kazuya Masu

    ADVANCED METALLIZATION CONFERENCE 2007 (AMC 2007)   23   309 - 313   2008

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  • C-2-86 An Effective Attenuation that Includes Crosstalk from Wirings with Various Attenuation Characteristics

    Fu Wanlin, Ito Hiroyuki, Amakawa Shuhei, Sakai Jun, Masu Kazuya

    Proceedings of the Society Conference of IEICE   2007 ( 1 )   108 - 108   2007.8

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  • Transmission line interconnect on Si CMOS LSI Reviewed

    Kazuya Masu, Kenichi Okada, Hiroyuki Ito

    ICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology, Proceedings   306 - 309   2007

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    DOI: 10.1109/ICSICT.2006.306214

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  • A Low-Power Low-Phase-Noise CMOS VCO using RF SiP Technology Reviewed

    Kazuma Ohashi, Yusaku Ito, Hiroyuki Ito, Kenichi Okada, Hideki Hatakeyama, Naoyuki Ozawa, Masakazu Sato, Takuya Aizawa, Tatsuya Ito, Ryozo Yamauchi, Kazuya Masu

    2007 ASIA PACIFIC MICROWAVE CONFERENCE, VOLS 1-5   1963 - +   2007

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  • A low-latency and high-power-efficient on-chip LVDS transmission line interconnect for an RC interconnect alternative Reviewed

    Hiroyuki Ito, Junki Seita, Takahiro Ishii, Hideyuki Sugita, Kenichi Okada, Kazuya Masu

    PROCEEDINGS OF THE IEEE 2007 INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE   193 - +   2007

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  • A 8-gbps low-latency multi-drop on-chip transmission line interconnect with 1.2-mW two-way transceivers Reviewed

    Hiroyuki Ito, Makoto Kimura, Kenichi Okada, Kazuya Masu

    2007 Symposium on VLSI Circuits, Digest of Technical Papers   136 - 137   2007

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  • A 5.2 GHz CMOS low noise amplifier with high-Q inductors embedded in wafer-level chip-scale package Reviewed

    Satoshi Fukuda, Hiroyuki Ito, Kazuhisa Itoi, Masakazu Sato, Tatsuya Ito, Ryozo Yamauchi, Kenichi Okada, Kazuya Masu

    2007 IEEE INTERNATIONAL WORKSHOP ON RADIO-FREQUENCY INTEGRATION TECHNOLOGY, PROCEEDINGS   34 - +   2007

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  • On-chip Differential-Transmission-Line(DTL) interconnect for 22nm technology Reviewed

    Kenichi Okada, Hiroyuki Ito, Kazuya Masu

    Advanced Metallization Conference 2006 (AMC 2006)   29 - 33   2007

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  • A 6.5-mW 5-gbps on-chip differential transmission line interconnect with a low-latency asymmetric Tx in a 180nm CMOS technology

    Takahiro Ishii, Hiroyuki Ito, Makoto Kimura, Kenichi Okada, Kazuya Masu

    2006 IEEE Asian Solid-State Circuits Conference, ASSCC 2006   131 - 134   2006

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    DOI: 10.1109/ASSCC.2006.357869

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  • Distributed constant passive devices using wafer-level chip scale package technology for one-chip wireless communication circuits Reviewed

    J Seita, H Ito, H Sugita, K Okada, T Ito, K Itoi, M Sato, K Masu

    2006 TOPICAL MEETING ON SILICON MONOLITHIC INTEGRATED CIRCUITS IN RF SYSTEMS, DIGEST OF PAPERS   338 - +   2006

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  • High-crosstalk robustness transmission line interconnect in si LSI using zero-crosstalk structurea Reviewed

    Makoto Kimura, Hiroyuki Ito, Hideyuki Sugita, Kenichi Okada, Kazuya Masu

    10TH IEEE WORKSHOP ON SIGNAL PROPAGATION ON INTERCONNECTS, PROCEEDINGS   153 - +   2006

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  • High-density differential transmission line bus structure for future subnanometer technologies Reviewed

    M Kimura, H Ito, H Sugita, K Okada, K Masu

    ADVANCED METALLIZATION CONFERENCE 2005 (AMC 2005)   143 - 149   2006

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  • On-chip transmission line interconnect for SiCMOS LSI Reviewed

    K Masu, K Okada, H Ito

    2006 TOPICAL MEETING ON SILICON MONOLITHIC INTEGRATED CIRCUITS IN RF SYSTEMS, DIGEST OF PAPERS   353 - +   2006

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  • Twisted Differential Transmission Line Structure for Global Interconnect in Si LSI

    Ito Hiroyuki, Gomi Shinichiro, Sugita Hideyuki, Okada Kenichi, Masu Kazuya

    Jpn J Appl Phys   44 ( 4 )   2774 - 2779   2005.4

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    This paper investigates the twisted differential transmission line structure to achieve high-speed signal transmission and electromagnetic interference (EMI) noise reduction of global interconnects in Si LSIs. The differential transmission line in Si LSIs can transmit a 12 Gbps pulse signal and has the capability of reducing EMI noise. The proposed twisted-diagonal-pair line provides high-speed, low-EMI-noise, high-crosstalk-robustness and high-density global interconnects in Si LSIs.

    DOI: 10.1143/JJAP.44.2774

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  • 4 Gbps on-chip interconnection using differential transmission line Reviewed

    Hiroyuki Ito, Hideyuki Sugita, Kenichi Okada, Kazuya Masu

    2005 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE, PROCEEDINGS OF TECHNICAL PAPERS   417 - 420   2005

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  • Evaluation of on-chip transmission line interconnect using wire length distribution Reviewed

    Junpei Inoue, Hiroyuki Ito, Shinichiro Gomi, Takanori Kyogoku, Takumi Uezono, Kenichi Okada, Kazuya Masu

    ASP-DAC 2005: PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2   133 - 138   2005

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  • Design and fabrication of a MEMS 1-D optical scanner using self-assembled vertical combs and scan-angle magnifying mechanism Reviewed

    M Yoda, K Isamoto, C Chong, H Ito, A Murata, H Toshiyoshi

    IEEE/LEOS Optical MEMs 2005: International Conference on Optical MEMs and Their Applications   19 - 20   2005

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  • Variable RF Inductor on Si CMOS Chip

    Sugawara Hirotaka, Yokoyama Yoshisato, Gomi Shinichiro, Ito Hiroyuki, Okada Kenichi, Hoshino Hiroaki, Onodera Hidetoshi, Masu Kazuya

    Jpn J Appl Phys   43 ( 4 )   2293 - 2296   2004.4

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    We propose a novel variable inductor on a Si complementary metal oxide semiconductor (CMOS) chip, whose inductance is of nH-order, for GHz applications. The inductance value can be varied by moving a metal plate above the inductor. The magnetic flux penetrating the spiral inductor continuously varies depending on the position of the metal plate. The metal plate is slid horizontally using a micro electro mechanical system (MEMS) actuator. We present the measured and simulated results. At 2.45 GHz, the inductance is varied from 6.6 nH to 5.7 nH, i.e., the variable range is 13%. These results show that the effect of parasitic capacitance between the spiral inductor and the metal plate can be ignored. The proposed variable inductor can be applied to RF circuits.

    DOI: 10.1143/JJAP.43.2293

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  • On-chip transmission line for long global interconnects

    Hiroyuki Ito, Junpei Inoue, Shinichiro Gomi, Hideyuki Sugita, Kenichi Okada, Kazuya Masu

    Technical Digest - International Electron Devices Meeting, IEDM   677 - 680   2004

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  • Millimeter-wave photonic integrated circuit technologies for high-speed wireless communications applications

    T. Nagatsuma, A. Hirata, M. Harada, H. Ishii, K. Machida, T. Minotani, H. Ito, T. Kosugi, T. Shibata

    Digest of Technical Papers - IEEE International Solid-State Circuits Conference   47   2004

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  • On-chip high-Q Cu inductors embedded in wafer-level chip-scale package for silicon RF application

    Kazuhisa Itoi, Masakazu Sato, Hiroshi Abe, Hirotaka Sugawara, Hiroyuki Ito, Kenichi Okada, Kazuya Masu, Tatsuya Ito

    IEEE MTT-S International Microwave Symposium Digest   1   197 - 200   2004

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  • Inductance-Tuned LC-VCO for Reconfigurable RF Circuit Design

    Yoshihara Yoshiaki, Sugawara Hirotaka, Ito Hiroyuki, Okada Kenichi, Masu Kazuya

    IEICE Electron. Express   1 ( 7 )   156 - 159   2004

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    This paper presents a wide tuning range LC-VCO using an on-chip variable inductor to extend tuning range. The VCO was fabricated using 0.35µm CMOS process. The tuning range was found to be 37.8% without degradation of phase noise by inductance tuning. Wide tunable VCO with an on-chip variable inductor is one of the key circuits of reconfigurable RF circuit.

    DOI: 10.1587/elex.1.156

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MISC

  • Evaluation of Device for High-Sensitivity MEMS Sensor Module

    内山晃宏, 柴田滉平, 大西哲, 町田克之, 緒方大樹, 石原昇, 内富寛隆, CHANG Tso-Fu Mark, 曽根正人, 三宅美博, 伊藤浩之

    応用物理学会春季学術講演会講演予稿集(CD-ROM)   69th   2022

  • Noise floor estimation of Au proof-mass single-axis MEMS sensor module

    大西哲, 御宿希祐, TENNETI Devi Srujana, CHAKRABORTY Parthojit, 町田克之, 緒方大樹, 内富寛隆, CHANG Tso-Fu Mark, 曽根正人, 三宅美博, 伊藤浩之

    応用物理学会秋季学術講演会講演予稿集(CD-ROM)   83rd   2022

  • A Study on High-Sensitivity MEMS Sensor Module for Micro Muscle Sound Measurement

    大西哲, 柴田滉平, 内山晃宏, 町田克之, 緒方大樹, 石原昇, 内富寛隆, CHANG Tso-Fu Mark, 曽根正人, 三宅美博, 伊藤浩之

    応用物理学会春季学術講演会講演予稿集(CD-ROM)   69th   2022

  • フォトゲート型蛍光センサによるレジオネラ属菌検知システムの検討—Detection system of bacteria, Legionella by photogate type optical sensor—第13回集積化MEMSシンポジウム

    本田 優斗, 崔 容俊, 村上 健介, 野田 俊彦, 高橋 一浩, 澤田 和明, 石井 仁, 町田 克之, 伊藤 浩之, 宮原 敏, 二階堂 靖彦, 齋藤 光正

    「センサ・マイクロマシンと応用システム」シンポジウム論文集 電気学会センサ・マイクロマシン部門 [編]   38   5p   2021.11

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    Language:Japanese   Publisher:[東京] : Institute of Electrical Engineers of Japan  

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  • Measurement system by photogate type fluorescent sensor for identification of Legionella Reviewed

    本田優斗, CHOI Y. J., 村上健介, 野田俊彦, 高橋一浩, 澤田和明, 石井仁, 町田克之, 伊藤浩之, 二階堂靖彦, 齋藤光正

    応用物理学会春季学術講演会講演予稿集(CD-ROM)   68th   2306 - 2306   2021.7

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    Language:Japanese   Publishing type:Article, review, commentary, editorial, etc. (scientific journal)   Publisher:The Japan Society of Applied Physics  

    DOI: 10.11470/jsapmeeting.2021.1.0_2306

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  • 細菌-材料インターフェイスにおけるフッ素徐放性材料のpH低下抑制効果の評価および将来への展望

    真柳 弦, 鷲尾 純平, 高橋 信博, 柳田 保子, 伊藤 浩之, 石原 昇, 益 一哉

    生体医歯工学共同研究拠点成果報告書   平成29年度   98 - 98   2018.4

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    Language:Japanese   Publisher:東京医科歯科大学生体材料工学研究所  

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  • A 0.18-µm CMOS time-domain capacitive-sensor interface for sub-1mG MEMS accelerometers

    Motohiro Takayasu, Shiro Dosho, Hiroyuki Ito, Daisuke Yamane, Toshifumi Konishi, Katsuyuki Machida, Noboru Ishihara, Kazuya Masu

    IEICE Electronics Express   15 ( 2 )   2018

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    Publishing type:Book review, literature introduction, etc.  

    DOI: 10.1587/elex.15.20171227

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  • Inclining Angle Sensitivity Characteristics of MEMS Accelerometer Fabricated by Multi-Layer Metal Technology

    34   3p   2017.10

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  • A Multi-layer Metal MEMS Accelerometer with Differential Sensing Structure

    33   1 - 4   2016.10

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  • A Noise Analysis Method with Multi-physics Simulation for CMOS-MEMS Inertial Sensor

    33   1 - 4   2016.10

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  • A High-Resolution Capacitive Sensor Circuit using RC Oscillator

    33   1 - 4   2016.10

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  • A Study of Inertial Sensor Module with MEMS Accelerometers by Multi-layer Metal Technology

    33   1 - 4   2016.10

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  • C-12-2 A 0.5-V 1.56-mW OOK RF Transceiver Module with J-Shaped Folded Monopole Antenna

    Ishikawa Yosuke, Lee Sang_yeop, Yonezawa Shin, Ikeda Sho, Fang Yiming, Hamada Taisuke, Ito Hiroyuki, Ishihara Noboru, Masu Kazuya

    Proceedings of the IEICE General Conference   2016 ( 2 )   75 - 75   2016.3

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  • B-1-45 Bezier Curves Geometry for Shape Optimization of Patch Antenna

    Ohashi Ryotaro, Dosho Shiro, Ito Hiroyuki, Ishihara Noboru, Kai Manabu, Abe Tomoyuki, Nakamoto Hiroyuki, Masui Shoichi, Masu Kazuya

    Proceedings of the IEICE General Conference   2016 ( 1 )   45 - 45   2016.3

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  • B-18-28 Evaluation of sampling frequency using environmental data recovery in wireless sensor networks

    Ohba Kohei, Yoneda Yoshihiro, Suganuma Takashi, Ito Hiroyuki, Ishihara Noboru, Gotoh Kunihiko, Masu Kazuya

    Proceedings of the IEICE General Conference   2016 ( 2 )   526 - 526   2016.3

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  • C-2-99 An RF Universal Board for SSOP-Surface-Mounted Components

    Takayasu Motohiro, Gonda Toshiaki, Ishikawa Yosuke, Ito Hiroyuki, Dosho Shiro, Ishihara Noboru, Masu Kazuya

    Proceedings of the IEICE General Conference   2016 ( 1 )   128 - 128   2016.3

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  • C-12-13 A study of CMOS low-noise amplifier design method

    Liu Anky, Konishi Toshifumi, Yamane Daisuke, Ito Hiroyuki, Dosho Shiro, Ishihara Noboru, Machida Katsuyuki, Masu Kazuya

    Proceedings of the IEICE General Conference   2016 ( 2 )   86 - 86   2016.3

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  • A Study on Gain-Controlled Sensor Circuits with Multi-physics Simulation for CMOS-MEMS Accelerometer

    32   1 - 4   2015.10

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  • A study on applicability of inertial sensor for mobile vehicle control

    32   1 - 4   2015.10

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  • A study on phase noise cancellation for group synchronous frequency generation

    114 ( 498 )   127 - 132   2015.3

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  • C-12-7 Start-up Energy Reduction of a Crystal Oscillator with a Negative Resistance Booster

    Park Jeehoon, Ito Hiroyuki, Ishihara Noboru, Masu Kazuya

    Proceedings of the IEICE General Conference   2015 ( 2 )   68 - 68   2015.2

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  • C-2-102 Impedance matching circuit design and board level packaging technology for a low power RF CMOS transceiver

    Ishikawa Yosuke, Lee Sang_yeop, Yonezawa Shin, Ikeda Sho, Fang Yiming, Takayasu Motohiro, Hamada Taisuke, Ito Hiroyuki, Ishihara Noboru, Masu Kazuya

    Proceedings of the IEICE General Conference   2015 ( 1 )   122 - 122   2015.2

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  • C-2-99 A Study of a Transmission Line Probe for One-Dimensional Soil-Moisture-Content Measurement

    Togashi Yuta, Ito Hiroyuki, Ishihara Noboru, Masu Kazuya

    Proceedings of the IEICE General Conference   2015 ( 1 )   119 - 119   2015.2

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  • B-18-78 Frequency analysis of reproduced environmental information using polynomial regression

    Ohba Kouhei, Yoneda Yoshihiro, Kurihara Koji, Suganuma Takashi, Ito Hiroyuki, Gotoh Kunihiko, Masu Kazuya

    Proceedings of the IEICE General Conference   2015 ( 2 )   625 - 625   2015.2

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  • C-12-24 A 0.5-V 5.8-GHz Low Power Inverter-based RF CMOS Transceiver with Forward Body Bias

    Ishikawa Yosuke, Lee Sang-yeop, Yonezawa Shin, Ikeda Sho, Fang Yiming, Takayasu Motohiro, Hamada Taisuke, Ito Hiroyuki, Ishihara Noboru, Masu Kazuya

    Proceedings of the Society Conference of IEICE   2014 ( 2 )   76 - 76   2014.9

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  • C-12-23 A 0.5-V 5.8-GHz Phase-Locked Loop with Amplitude-Balanced Current-Reuse VCO

    Ikeda Sho, Lee Sang-yeop, Ito Hiroyuki, Ishihara Noboru, Masu Kazuya

    Proceedings of the Society Conference of IEICE   2014 ( 2 )   75 - 75   2014.9

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  • B-18-37 Data Reliability of Sensor Network for Environmental Monitoring

    Yoneda Yoshihiro, Kurihara Koji, Suganuma Takashi, Ito Hiroyuki, Gotoh Kunihiko, Masu Kazuya

    Proceedings of the Society Conference of IEICE   2014 ( 2 )   395 - 395   2014.9

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  • C-12-7 A 0.5V CMOS Inverter-based ΔΣ Analog-to-Digital Converter

    Maruyama Tatsuya, Tomimatsu Kazuki, Shiino Yusuke, Ito Hiroyuki, Gotoh Kunihiko, Ishihara Noboru, Masu Kazuya

    Proceedings of the IEICE General Conference   2014 ( 2 )   71 - 71   2014.3

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  • MEMS Resonant Mixers for a Mixer-First RF Receiver

    30   1 - 4   2013.11

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  • A Low Voltage Phase-Locked Loop with Digitally Calibrated Injection Locked Frequency Divider and Linearized Varactor

    Ikeda Sho, Kamimura Tatsuya, Lee Sangyeop, Ito Hiroyuki, Ishihara Noboru, Masu Kazuya

    Proceedings of the Society Conference of IEICE   2013 ( 2 )   94 - 94   2013.9

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  • Low-power wireless pH monitoring FM Transmitter IC with Ion Sensitive Field Effect Transistor

    Shiino Yusuke, Fujiwara Taku, Nomura Satoshi, Ito Hiroyuki, Ishihara Noboru, Yamanouchi Hisashi, Tanabe Hiroki, Konishi Toshifumi, Machida Katsuyuki, Masu Kazuya

    Proceedings of the Society Conference of IEICE   2013 ( 2 )   84 - 84   2013.9

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  • A Study on an Arrayed MEMS Accelerometer

    TSUKUDA Masafumi, YAMANE Daisuke, KAGAYA Ken, ITO Hiroyuki, ISHIHARA Nobiru, MASU Kazuya, KONISHI Toshifumi, MATSUSHIMA Takaaki, MACHIDA Katsuyuki, TOSHIYOSHI Hiroshi

    電気学会研究会資料. MSS, マイクロマシン・センサシステム研究会   2013 ( 1 )   1 - 4   2013.8

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  • Invited Talk : A Study of Ultra-Low-Power RF CMOS Transceiver Circuit Technologies

    ITO Hiroyuki, LEE Sang-yeop, IKEDA Sho, HAO Jiang, ISHIHARA Noboru, MASU Kazuya

    IEICE technical report. Microwaves   112 ( 459 )   153 - 156   2013.3

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    The purpose of this work is development of an ultra-low-power RF CMOS tranceiver circuit technology for a short range wireless sensor network (WSN). Wireless macro-trends of bit-rate, power and power efficiency in ISSCC are shown, and challenges of RF circuits for WSN are briefly explained. This paper introduces circuit techniques for saving power of local-signal generators that consume larger power than other circuits in a short-range RF CMOS tranceiver.

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  • C-12-23 A1.8 GHz, 2.2 Watt Fully Integrated CMOS Power Amplifier

    Kiumarsi Hamid, Zheng Fenghuai, Ito Hiroyuki, Ishihara Noboru, Masu Kazuya

    Proceedings of the IEICE General Conference   2013 ( 2 )   94 - 94   2013.3

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  • C-12-62 A0.5 V Phase-Locked Loop with lnjection Locked Frequency Divider and Class-C VCO

    Ikebe Sho, Uemura Tatsuya, Lee Sangyeop, Kanemaru Norifumi, Ito Hiroyuki, Ishihara Noboru, Masu Kazuya

    Proceedings of the IEICE General Conference   2013 ( 2 )   133 - 133   2013.3

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  • C-12-26 A Study of Ultra-low Power RF CMOS Wake-up Receiver

    Jiang Hao, Ito Hiroyuki, lshihara Noboru, Masu Kazuya

    Proceedings of the IEICE General Conference   2013 ( 2 )   97 - 97   2013.3

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  • C-12-57 A Study of Low-power pH monitoring FM Transmitter IC with lon Sensitive Field Effect Transistor

    Shiino Yusuke, Fujiwara Taku, Ito Hiroyuki, Ishihara Noboru, Yamauchi Hisashi, Tanabe Hiroki, Nomura Satoshi, Konishi Toshifumi, Machida Katsuyuki, Masu Kazuya

    Proceedings of the IEICE General Conference   2013 ( 2 )   128 - 128   2013.3

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  • C-12-27 A Study of RF CMOS Low-Power and Miliaturized Receiver Module

    Yonezawa Shin, Fang Yiming, Ito Hiroyuki, Ishihara Noboru, Masu Kazuya

    Proceedings of the IEICE General Conference   2013 ( 2 )   98 - 98   2013.3

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  • C-12-26 Design of CMOS Inverter-based ΔΣ Analog-to-Digital Converter

    Tomimatsu Kazuki, Ito Hiroyuki, Ishihara Noboru, Gotoh Kunihiko, Masu Kazuya

    Proceedings of the Society Conference of IEICE   2012 ( 2 )   99 - 99   2012.8

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  • C-12-11 Indutors and Transformers on 65 nm CMOS Technology for 60 GHz Applications

    Kiumarsi Hamid, Ito Hiroyuki, Okada Kenichi, Ishihara Noboru, Masu Kazuya

    Proceedings of the Society Conference of IEICE   2012 ( 2 )   84 - 84   2012.8

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  • RF MEMS回路とCMOS集積回路のフリップチップ実装

    白根篤史, 伊藤浩之, 石原昇, 益一哉

    応用物理学関係連合講演会講演予稿集(CD-ROM)   59th   2012

  • 近距離通信用90nm Si CMOSプロセススケーラブルRFトランシーバ

    米澤慎, 白根篤史, 大鶴基格, LEE Sang-yeop, 田野井聡, 伊藤浩之, 石原昇, 益一哉

    電子情報通信学会大会講演論文集   2012   2012

  • An Inductorless Phase-Locked Loop with Pulse Injection Locking Technique in 90 nm CMOS

    Lee Sang_yeop, Ito Hiroyuki, Ishihara Noboru, Masu Kazuya

    Technical report of IEICE. ICD   111 ( 352 )   1 - 6   2011.12

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    An inductorless phase-locked loop with subharmonic pulse injection locking was realized (PLL area: 0.08 mm^2) by adopting 90 nm Si CMOS technology. In the proposed PLL, a phase-locked loop is implemented to ensure correct frequency locking. Final phase locking is done by injection locking to reduce phase noise. For a 300-MHz input reference signal, without injection locking, the 1-MHz-offset phase noise was -91.4 dBc/Hz (PLL output frequency: 7.2 GHz = 24×300 MHz); with injection locking, the noise was -107 dBc/Hz (spurious level: -32 dBc; power consumption from a 1.0 V power supply: 13.6 mW).

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  • C-2-82 Broadside 3-dB Tandem Coupler Using WLP Technology for 60 GHz Applications

    Kiumarsi Hamid, Tanoi Satoru, Uemichi Yusuke, Hatakeyama Hideki, Aizawa Takuya, Ito Hiroyuki, Okada Kenichi, Ishihara Noboru, Masu Kazuya

    Proceedings of the IEICE General Conference   2011 ( 1 )   120 - 120   2011.2

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  • C-12-23 A Study of Inverter-based RF CMOS Low Noise Amplifier Scalability in CMOS Process

    Dharmiza Dayang Nur Salmi, Oturu Mototada, Nakajima Tomoya, Tanoi Satoru, Amakawa Shuhei, Ito Hiroyuki, Ishihara Noboru, Masu Kazuya

    Proceedings of the IEICE General Conference   2011 ( 2 )   95 - 95   2011.2

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  • C-12-11 An Inductorless Phase-Locked Loop with an Injection Locking Technique

    Lee Sangyeop, Amakawa Shuhei, Ito Hiroyuki, Ishihara Noboru, Masu Kazuya

    Proceedings of the IEICE General Conference   2011 ( 2 )   83 - 83   2011.2

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  • RF MEMS高可変率インダクタの形状に関する検討

    白根篤史, 伊藤浩之, 石原昇, 益一哉

    応用物理学会学術講演会講演予稿集(CD-ROM)   72nd   2011

  • 集積化CMOS-MEMSのための統合設計技術の検討(2)

    小西敏文, 丸山智史, 松島隆明, 三田信, 町田克之, 町田克之, 伊藤浩之, 石原昇, 益一哉, 藤田博之, 年吉洋

    応用物理学会学術講演会講演予稿集(CD-ROM)   72nd   2011

  • 集積化CMOS-MEMSのためのSPICE系統合設計手法

    小西敏文, 丸山智史, 松島隆明, 三田信, 町田克之, 町田克之, 伊藤浩之, 石原昇, 益一哉, 藤田博之, 年吉洋

    センサ・マイクロマシンと応用システムシンポジウム(CD-ROM)   28th   2011

  • S-parameter-based Modal Decomposition of Multiconductor Transmission Lines and Its Application to De-embedding Reviewed

    S. Amakawa, K. Yamanaga, H. Ito, T. Sato, N. Ishihara, K. Masu

    IEEE International Conference on Microelectronic Test Structures (ICMTS)   177 - 180   2009.3

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    DOI: 10.1109/ICMTS.2009.4814635

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  • C-12-4 Low-Power On-Chip High-Speed Transmission Line Interconnect using Signal Data Edge Pulses

    Maekawa Tomoaki, Ito Hiroyuki, Ishihara Noboru, Masu Kazuya

    Proceedings of the Society Conference of IEICE   2008 ( 2 )   73 - 73   2008.9

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  • C-12-5 Measurements of On-Chip Transmission Line Interconnect with Pre-Emphasis Techniques

    Miyashita Kazuya, Ishii Takahiro, Ito Hiroyuki, Ishihara Noboru, Masu Kazuya

    Proceedings of the Society Conference of IEICE   2008 ( 2 )   74 - 74   2008.9

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  • C-12-8 A Low-Power and Small-Area CMOS Pseudo-Random-Bit-Sequence Data-Generator

    Mineyama Akiko, Ito Hiroyuki, Ishihara Noboru, Masu Kazuya

    Proceedings of the Society Conference of IEICE   2008 ( 2 )   77 - 77   2008.9

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  • A bidirectional- and multi-drop-transmission-line interconnect for multipoint-to-multipoint on-chip communications

    Hiroyuki Ito, Makoto Kimura, Kazuya Miyashita, Takahiro Ishii, Kenichi Okada, Kazuya Masu

    IEEE JOURNAL OF SOLID-STATE CIRCUITS   43 ( 4 )   1020 - 1029   2008.4

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  • C-12-58 A De-embedding Method for W-band On-Wafer S-parameter Measurements

    Ito Hiroyuki, Masu Kazuya

    Proceedings of the IEICE General Conference   2008 ( 2 )   148 - 148   2008.3

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  • C-12-54 A Low-Power On-Chip Pulse Transmission Line Interconnect

    Maekawa Tomoaki, Ishii Takahiro, Ito Hiroyuki, Okada Kenichi, Masu Kazuya

    Proceedings of the IEICE General Conference   2008 ( 2 )   144 - 144   2008.3

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  • C-12-18 A Low Phase Noise CMOS Voltage Controlled Oscillator using a Wafer Level Package Technology

    Kobayashi Yuka, Ohashi Kazuma, Ito Hiroyuki, Okada Kenichi, Hatakeyama Hideki, Aizawa Takuya, Ito Tatsuya, Yamauchi Ryozo, Masu Kazuya

    Proceedings of the IEICE General Conference   2008 ( 2 )   108 - 108   2008.3

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  • C-12-64 A Low Noise Amplifier using Wafer Level Package Technology

    Sadoshima Susumu, Ito Hiroyuki, Okada Kenichi, Hatakeyama Hideki, Aizawa Takuya, Ito Tatsuya, Yamauchi Ryozo, Masu Kazuya

    Proceedings of the IEICE General Conference   2008 ( 2 )   154 - 154   2008.3

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  • C-12-53 A Low Power 1:4 Demultiplexer for On-Chip Networks using Transmission Line Interconnects

    Mineyama Akiko, Ito Hiroyuki, Masu Kazuya

    Proceedings of the IEICE General Conference   2008 ( 2 )   143 - 143   2008.3

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  • A simple through-only de-embedding method for on-wafer S-parameter measurements up to 110GHz

    ITO H.

    IEEE MTT-S International Microwave Symposium Digest, June 2008   383 - 386   2008

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  • A 0.49-6.50GHz Wideband LC-VCO with High-IRR in a 180nm CMOS Technology

    KOBAYASHI Yuka, OHASHI Kazuma, ITO Yusaku, ITO Hiroyuki, OKADA Kenichi, MASU Kazuya

    2007   268 - 269   2007.9

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  • C-12-35 Investigation of High FoM Voltage Controlled Oscillator using Wafer Level Chip Scale Package Technology

    Ohashi Kazuma, Ito Hiroyuki, Okada Kenichi, Hatakeyama Hideki, Aizawa Takuya, Ito Tatsuya, Yamauchi Ryozo, Masu Kazuya

    Proceedings of the Society Conference of IEICE   2007 ( 2 )   90 - 90   2007.8

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  • C-12-45 Investigation of On-Chip Transmission Line Interconnect in Wafer Level Chip Scale Package Technology

    Mineyama Akiko, Ishii Takahiro, Kimira Makoto, Ito Hiroyuki, Okada Kenichi, Hatakeyama Hideki, Aizawa Takuya, Ito Tatsuya, Yamauchi Ryozo, Masu Kazuya

    Proceedings of the Society Conference of IEICE   2007 ( 2 )   100 - 100   2007.8

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  • C-12-27 Investigation of Wide-band Low Noise Amplifier Using Wafer Level Chip Size Package Process

    Fukuda Satoshi, Ito Hiroyuki, Okada Kenichi, Masu Kazuya, Hatakeyama Hideki, Aizawa Takuya, Ito Tatsuya, Yamauchi Ryozo

    Proceedings of the Society Conference of IEICE   2007 ( 2 )   82 - 82   2007.8

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  • C-12-42 Investigation of On-Chip Differential Transmission Line Interconnect with Pre-emphasis Technique

    Ishii Takahiro, Ito Hiroyuki, Masu Kazuya

    Proceedings of the Society Conference of IEICE   2007 ( 2 )   97 - 97   2007.8

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  • C-12-43 Transmitters for Low-Power Pulsed Signaling on On-Chip Differential Transmission Line Interconnects

    Maekawa Tomoaki, Ishii Takahiro, Ito Hiroyuki, Okada Kenichi, Masu Kazuya

    Proceedings of the Society Conference of IEICE   2007 ( 2 )   98 - 98   2007.8

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  • C-12-28 A Tunable Power Amplifier using Wafer Level Chip Scale Package Technology

    Sadoshima Susumu, Yammouch Tackya, Ito Hiroyuki, Okada Kenichi, Masu Kazuya, Hatakeyama Hideki, Aizawa Takuya, Ito Tatsuya, Yamauchi Ryozo

    Proceedings of the Society Conference of IEICE   2007 ( 2 )   83 - 83   2007.8

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  • C-12-41 Measurements of a Multi-Drop On-Chip Interconnect using Transmission Lines

    Miyashita Kazuya, Kimura Makoto, Ito Hiroyuki, Okada Kenichi, Masu Kazuya

    Proceedings of the Society Conference of IEICE   2007 ( 2 )   96 - 96   2007.8

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  • C-12-31 A Wideband CMOS Voltage Controlled Oscillator with High-IRR Frequency-Tuning-Range-Extention Circuit

    Kobayashi Yuka, Ohashi Kazuma, Ito Yusaku, Ito Hiroyuki, Okada Kenichi, Masu Kazuya

    Proceedings of the Society Conference of IEICE   2007 ( 2 )   86 - 86   2007.8

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  • On-chip Yagi-Uda antenna for horizontal wireless signal transmission in stacked multi chip packaging

    Kazuma Ohashi, Tackya Yammouch, Makoto Kimura, Hiroyuki Ito, Kenichi Okada, Kazuhisa Itoi, Masakazu Sato, Tatsuya Ito, Ryozo Yamauchi, Kazuya Masu

    JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS   46 ( 4B )   2283 - 2286   2007.4

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  • C-2-98 A Composite Right/Left Handed Transmission Line with Si CMOS Process

    Kim Jang-Gu, Ito Hiroyuki, Okada Kenichi, Masu Kazuya

    Proceedings of the IEICE General Conference   2007 ( 1 )   131 - 131   2007.3

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  • C-2-62 Study of High-Density and High-Speed Printed-Wiring Board using Diagonal-Pair Line Structure

    Fu Wanlin, Kimura Makoto, Ito Hiroyuki, Okada Kenichi, Sakai Jun, Masu Kazuya

    Proceedings of the IEICE General Conference   2007 ( 1 )   95 - 95   2007.3

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  • C-12-27 A 2.7mW/10Gbps On-Chip LVDS-type Transmission Line Interconnect in 90nm CMOS Technology

    Ito Hiroyuki, Seita Junki, Ishii Takahiro, Sugita Hideyuki, Okada Kenichi, Masu Kazuya

    Proceedings of the IEICE General Conference   2007 ( 2 )   106 - 106   2007.3

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  • A-3-10 Investigation of Scaling Effects on On-Chip Differential Transmission Line Using an Asymmetric Tx

    Ishii Takahiro, Ito Hiroyuki, Okada Kenichi, Masu Kazuya

    Proceedings of the IEICE General Conference   2007   100 - 100   2007.3

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  • Low-loss distributed constant passive devices using wafer-level chip scale package technology

    Hiroyuki Ito, Hideyuki Sugita, Kenichi Okada, Tatsuya Ito, Kazuhisa Itoi, Masakazu Sato, Ryozo Yamauchi, Kazuya Masu

    IEICE TRANSACTIONS ON ELECTRONICS   E90C ( 3 )   641 - 643   2007.3

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  • A Multi-drop Transmission-line Interconnect in Si LSI Reviewed

    J. Seita, H. Ito, K. Okada, T. Sato, K. Masu

    ACM/IEEE Asia and South Pacific Design Automation Conference (ASPDAC)   118 - 119   2007.1

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    DOI: 10.1109/ASPDAC.2007.357969

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  • On-Chip Yagi Antenna for Wireless Signal Transmission in Stacked MCP

    OHASHI Kazuma, YAMMOUCH Tackya, KIMURA Makoto, ITO Hiroyuki, OKADA Kenichi, ISHIDA Koichi, ITOI Kazuhisa, SATO Masakazu, ITO Tatsuya, MASU Kazuya

    2006   68 - 69   2006.9

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  • C-12-37 Investigation of On-Chip Differential Transmission Line Using CML for High-Speed Global Interconnect

    Ishii Takahiro, Ito Hiroyuki, Okada Kenichi, Masu Kazuya

    Proceedings of the Society Conference of IEICE   2006 ( 2 )   98 - 98   2006.9

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  • A-3-15 On-Chip Differential-Transmission-Line(DTL) Interconnect for 22nm Technology

    Okada Kenichi, Ito Hiroyuki, Masu Kazuya

    Proceedings of the Society Conference of IEICE   2006   59 - 59   2006.9

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  • A-3-17 Loss Investigation Using WD Product for On-Chip Differential Transimission Lines

    Fu Wanlin, Ito Hiroyuki, Kimura Makoto, Okada Kenichi, Masu Kazuya

    Proceedings of the Society Conference of IEICE   2006   61 - 61   2006.9

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  • A-3-18 Wireless Interconnection using On-chip Directional Antenna in Package

    Ohashi Kazuma, Yammouch Tackya, Kimura Makoto, Ito Hiroyuki, Okada Kenichi, Itoi Kazuhisa, Sato Masakazu, Ito Tatsuya, Yamauchi Ryozo, Masu Kazuya

    Proceedings of the Society Conference of IEICE   2006   62 - 62   2006.9

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  • 伝送線路を用いたオンチップ高速伝送回路の研究

    清田 淳紀, 伊藤 浩之, 岡田 健一, 佐藤 高史, 益 一哉

    電子情報通信学会 ソサイエティ大会   ( A-3-16 )   60 - 60   2006.9

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  • RF Passive Components Using Metal Line on Si CMOS

    MASU Kazuya, OKADA Kenichi, ITO Hiroyuki

    IEICE Trans. Electron., C   89 ( 6 )   681 - 691   2006.6

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    This paper discusses the design and performance of on-chip passive components of transmission lines (TR) and inductors. First, the measurement technique of on chip passives is discussed. A transmission line that can be used for Gbps signal propagation on Si CMOS is examined. As a high density transmission line structure of diagonal-pair differential TR line is described. Also, a circuit and TR line is introduced for above 10Gbps signal propagation. The on-chip inductor which is a key passive component in RF application of Si CMOS technology is discussed. We examine some on-chip inductors that have been developed in our group: small area inductor, high performance inductor using WL-CSP (Wafer-Level Chip-Size-Packaging) technology. Finally, a wide tuning range LC-VCO using a variable inductor for RF reconfigurable circuit is introduced.

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  • C-2-48 Study of Directional Coupler for One-Chip Wireless Communication Circuits with WL-CSP

    Seita Junki, Ito Hiroyuki, Sugita Hideyuki, Okada Kenichi, Ito Tatsuya, Itoi Kazuhisa, Sato Masakazu, Masu Kazuya

    Proceedings of the IEICE General Conference   2006 ( 1 )   79 - 79   2006.3

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  • On-Chip High-Q Variable Inductor Using Wafer-Level Chip-Scale Package Technology

    OKADA K.

    IEEE Trans. Electron Devices   53 ( 9 )   2401 - 2406   2006

  • Zero-Crosstalk Bus Line Structure for Global Interconnects in Si Ultra Large Scale Integration

    Kimura Makoto, Ito Hiroyuki, Sugita Hideyuki, Okada Kenichi, Masu Kazuya

    Jpn J Appl Phys   45 ( 6A )   4977 - 4981   2006

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    In this paper, we propose a novel technique for achieving high-density, high-speed and low-power on-chip bus lines using differential transmission lines. The feasibility of this technique is discussed with a two-dimensional electromagnetic simulator (Ansoft 2D Extractor) and time-domain measurements. Results show that the proposed bus line can transmit at over 12 Gbps. The proposed bus line can reduce wiring area by 30% compared with a conventional co-planar line.

    DOI: 10.1143/JJAP.45.4977

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  • A loss optimization method using WD product for on-chip differential transmission line design

    ITO H.

    Proc. IEEE SPI, 2006   217 - 220   2006

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  • A-3-15 Crosstalk Evaluation of Twisted Differential Transmission Line in Si LSI

    Kimura Makoto, Ito Hiroyuki, Sugita Hideyuki, Okada Kenichi, Masu Kazuya

    Proceedings of the IEICE General Conference   79 - 79   2006

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  • Si CMOSオンチップ伝送線路配線技術

    益 一哉, 岡田 健一, 伊藤 浩之

    エレクトロニクス実装学会誌   9 ( 5 )   342 - 346   2006

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    DOI: 10.5104/jiep.9.342

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  • Zero-Crosstalk Bus Line Structure for Global Interconnects in Si ULSI

    KIMURA Makoto, ITO Hiroyuki, SUGITA Hideyuki, OKADA Kenichi, MASU Kazuya

    2005   936 - 937   2005.9

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  • On Chip Transmission Line Interconnect

    MASU Kazuya, OKADA Kenichi, ITO Hiroyuki

    Technical report of IEICE. ICD   105 ( 268 )   47 - 52   2005.9

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    Recent Si CMOS performance becomes to be limited by the long global interconnect characteristics. In this paper, we discuss the performance of transmission line interconnect on Si CMOS chip. Interconnect line structure, design and evaluation of signal transmission of Tx/TR-Line/Rx circuit, and estimation and prediction of signal delay and power consumption of global interconnect in 180nm, 90nm and 45nm technology node are presented. In sub 100nm node, signal delay and power consumption of transmission line interconnect are both superior to those using the conventional RC global interconnect with repeaters.

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  • A-3-7 High-Frequency Characteristics of On-Chip Transmission Line with Bending and Vias

    Ito Hiroyuki, Sugita Hideyuki, Okada Kenichi, Masu Kazuya

    Proceedings of the Society Conference of IEICE   2005   66 - 66   2005.9

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  • A-3-8 On-Chip Multi-Drop Bus Using Transmission Line

    Seita Junki, Ito Hiroyuki, Okada Kenichi, Masu Kazuya

    Proceedings of the Society Conference of IEICE   2005   67 - 67   2005.9

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  • A-3-10 On-chip High-density Transmission Line Using Pseudo Differential Transmission Line

    Sugita Hideyuki, Ito Hiroyuki, Kimura Makoto, Okada Kenichi, Masu Kazuya

    Proceedings of the Society Conference of IEICE   2005   69 - 69   2005.9

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  • A-3-9 High-Speed and High-Density On Chip Bus Line using Transmission Line

    Kimura Makoto, Ito Hiroyuki, Sugita Hideyuki, Okada Kenichi, Masu Kazuya

    Proceedings of the Society Conference of IEICE   2005   68 - 68   2005.9

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  • A-3-11 Measurement and evaluation for Pseudo Differential Transmission Line on Si ULSI

    Sugita Hideyuki, Ito Hiroyuki, Gomi Shinichiro, Okada Kenichi, Masu Kazuya

    Proceedings of the IEICE General Conference   2005   76 - 76   2005.3

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  • C-2-61 Directional Coupler in Wafer-Level Chip Scale Package

    Ito Hiroyuki, Okada Kenichi, Ito Tatsuya, Sato Masakazu, Masu Kazuya

    Proceedings of the IEICE General Conference   2005 ( 1 )   94 - 94   2005.3

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  • Wide Tuning Range LC-VCO Using Variable Inductor for Reconfigurable RF Circuit

    YOSHIHARA Yoshiaki, SUGAWARA Hirotaka, ITO Hiroyuki, OKADA Kenichi, MASU Kazuya

    IEICE Trans. Fundamentals, A   88 ( 2 )   507 - 512   2005.2

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    This paper presents a novel wide tuning range CMOS Voltage Controlled Oscillator (VCO). VCO uses an on-chip variable inductor as an additional variable element to extend the tuning range of VCO. The fabricated variable inductor achieves the variable range of 35%. The VCO was fabricated using 0.35μm standard CMOS process, and can be tuned continuously from 2.13 GHz to 3.28 GHz (tuning range of 38%) without degradation of phase noise. Wide tunable LC-VCO using a variable inductor is one of the key circuits for reconfigurable RF circuit.

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  • On-Chip Transmission Line for Long Global Interconnects

    ITO Hiroyuki, INOUE Junpei, GOMI Shinichiro, SUGITA Hideyuki, OKADA Kenichi, MASU Kazuya

    Technical report of IEICE. SDM   104 ( 645 )   1 - 6   2005.1

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    This paper investigates the feasibility of differential transmission line interconnects at the future process technology. Delay time of differential transmission line interconnect is a tenth part of RC interconnect delay, and differential transmission line interconnect can save the power of 80% at 5-mm-long line in 45nm technology. It is expected that the circuit with transmission line interconnects can save 10% power at 45nm process. Additional global layers for transmission line interconnect give the power saving of 30%.

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  • On-chip Spiral Inductors Integrated with Wafer-Level Package

    SATO Masakazu, ITOI Kazuhisa, ABE Hiroshi, SUGAWARA Hirotaka, ITO Hiroyuki, OKADA Kenichi, MASU Kazuya, ITO Tatsuya

    2004   286 - 287   2004.9

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  • Twisted Differential Transmission Line Structure for EMI Noise Reduction at Global Interconnect in Si LSI

    ITO Hiroyuki, GOMI Shinichiro, SUGITA Hideyuki, OKADA Kenichi, MASU Kazuya

    2004   290 - 291   2004.9

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  • High-Speed Transmission Circuit for Micro Network on Si ULSI

    GOMI Shinichiro, NAKAMURA Kohichi, ITO Hiroyuki, SUGITA Hideyuki, OKADA Kenichi, MASU Kazuya

    2004   308 - 309   2004.9

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  • High Density Differential Transmission Line Structure on Si ULSI

    ITO Hiroyuki, OKADA Kenichi, MASU Kazuya

    IEICE Trans. on Electronics, C   87 ( 6 )   942 - 948   2004.6

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    The present paper proposes differential transmission line structures on Si ULSI. Interconnect structures are examined using numerical results from a two-dimensional electromagnetic simulation (Ansoft, 2D Extractor). The co-planar and diagonal-pair lines are found to have superior characteristics for gigahertz signal propagation through long interconnects. The proposed diagonal-pair line can reduce the crosstalk noise and interconnect resource concurrently.

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  • 樹脂基板内RFスパイラルインダクタの評価

    伊藤浩之, 菅原弘雄, 岡田健一, 島田靖, 大島俊之, 益一哉

    エレクトロニクス実装学術講演大会   123 - 124   2004

  • A wide tuning range CMOS VCO using variable inductor

    Y Yoshihara, H Sugawara, H Ito, K Okada, K Masu

    2004 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, Digest of Papers   278 - 281   2004

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  • ウェハレベルパッケージ内蔵高性能オンチップインダクタ

    佐藤正和, 糸井和久, 阿部博史, 伊藤浩之, 菅原弘雄, 岡田健一, 益一哉, 伊藤達也

    電子情報通信学会 総合大会   C-12-48   2004

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  • MEMSを用いたRF可変インダクタのモデル化手法

    菅原弘雄, 伊藤浩之, 岡田健一, 益一哉

    電子情報通信学会 総合大会   C-12-31   2004

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  • 可変インダクタを用いた広帯域CMOS VCOの設計

    吉原義昭, 菅原弘雄, 伊藤浩之, 岡田健一, 益一哉

    電子情報通信学会 総合大会   C-12-28   2004

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  • Si ULSIにおけるGHz帯差動伝送線路駆動受端回路の設計

    五味振一郎, 中村恒一, 伊藤浩之, 岡田健一, 益一哉

    電子情報通信学会 総合大会   A-3-24   2004

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  • リコンフィギュラブルRF回路設計技術に関する研究

    岡田健一, 吉原義昭, 菅原弘雄, 伊藤浩之, 益一哉

    電子情報通信学会シリコンアナログRF研究会   RF2004-1   1   2004

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  • 高周波インダクタ内蔵ウェハレベルパッケージ

    伊藤達也, 佐藤正和, 糸井和久, 阿部博史, 菅原弘雄, 伊藤浩之, 岡田健一, 益一哉

    エレクトロニクス実装学会 超高速高周波エレクトロニクス実装研究会   4 ( 1 )   7 - 8   2004

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  • Si ULSI内における擬差動伝送線路構造の検討

    杉田英之, 伊藤浩之, 五味振一郎, 岡田健一, 益一哉

    2004年秋季 第65回 応用物理学会 学術講演会   3a-L-9   2004

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  • Si CMOS チップにおけるEMI 低減のための縒り合わせ差動伝送線路構造

    伊藤浩之, 五味振一郎, 杉田英之, 岡田健一, 益一哉

    2004年秋季 第65回 応用物理学会 学術講演会   3a-L-8   2004

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  • Si ULSI内差動伝送線路の時間領域測定による評価

    伊藤浩之, 岡田健一, 益一哉

    電子情報通信学会 総合大会   A-3-23   2004

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  • Si CMOSチップ内差動伝送線路の時間領域測定による評価

    伊藤浩之, 岡田健一, 益一哉

    2004年春季 第50回 応用物理学会 関係連合講演会   28a-ZH-3   2004

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  • Si CMOSチップ上に作成した差動伝送線路のアイパターン測定

    伊藤浩之, 岡田健一, 益一哉

    電子情報通信学会シリコンアナログRF研究会   RF2004-1   1   2004

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  • オンチップマイクロネットワーク通信の実現に向けた高速信号伝送線路配線駆動回路の設計

    五味振一郎, 中村恒一, 伊藤浩之, 杉田英之, 岡田健一, 益一哉

    電子情報通信学会 ソサイエティ大会   C-12-25   2004

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  • GHz帯広帯域PLL向け発振器及び分周器についての検討

    吉原義昭, 菅原弘雄, 伊藤浩之, 岡田健一, 益一哉

    電子情報通信学会 ソサイエティ大会   C-12-23   2004

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  • Si LSIにおける縒り合わせ差動伝送線路を用いたEMI低減手法

    伊藤浩之, 五味振一郎, 杉田英之, 岡田健一, 益一哉

    電子情報通信学会 ソサイエティ大会   A-3-4   2004

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  • Si ULSI内の高速信号伝送に適した差動伝送線路構造に関する検討

    伊藤浩之, 岡田健一, 益一哉

    情報処理学会 DA シンポジウム論文集   2004 ( 8 )   271 - 276   2004

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  • High speed and low power on-chip micro network circuit with differential transmission line

    S Gomi, K Nakamura, H Ito, H Sugita, K Okada, K Masu

    2004 INTERNATIONAL SYMPOSIUM ON SYSTEM-ON-CHIP, PROCEEDINGS   173 - 176   2004

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  • High speed and low power globel interconnect IP with differential transmission line and driver-receiver circuits

    S Gomi, K Nakamura, H Ito, K Okada, K Masu

    PROCEEDINGS OF 2004 IEEE ASIA-PACIFIC CONFERENCE ON ADVANCED SYSTEM INTEGRATED CIRCUITS   384 - 387   2004

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  • Wide-range RF variable inductor on Si CMOS chip with MEMS actuator

    H Sugawara, Y Yoshihara, H Ito, K Okada, K Masu

    34TH EUROPEAN MICROWAVE CONFERENCE, VOLS 1-3, CONFERENCE PROCEEDINGS   701 - 704   2004

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  • Si ULSIにおける擬差動伝送線路構造

    杉田英之, 伊藤浩之, 五味振一郎, 岡田健一, 益一哉

    電子情報通信学会 ソサイエティ大会   A-3-3   2004

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  • 配線長分布を用いたオンチップ伝送線路の性能評価

    井上淳平, 伊藤浩之, 京極貴規, 上薗巧, 岡田健一, 益一哉

    電子情報通信学会 ソサイエティ大会   A-3-2   2004

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  • オンチップ差動伝送線路を用いた高速信号伝送回路

    五味振一郎, 伊藤浩之, 杉田英之, 岡田健一, 益一哉

    STARCシンポジウム   2004

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  • 高速信号伝送に適したオンチップ差動伝送線路構造

    伊藤浩之, 五味振一郎, 杉田英之, 岡田健一, 益一哉

    STARCシンポジウム   2004

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  • High-Q variable inductor using redistributed layers for Si RF circuits

    H Sugawara, H Ito, K Okada, K Itoi, M Sato, H Abe, T Ito, K Masu

    2004 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, Digest of Papers   187 - 190   2004

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    Web of Science

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  • On-chip high-Q solenoid inductors embedded in WL-CSP

    K Itoi, M Sato, H Abe, H Ito, H Sugawara, K Okada, K Masu, T Ito

    PROCEEDINGS OF THE SIXTH IEEE CPMT CONFERENCE ON HIGH DENSITY MICROSYSTEM DESIGN AND PACKAGING AND COMPONENT FAILURE ANALYSIS (HDP'04)   105 - 108   2004

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  • Pseudo differential transmission line structure on SiULSI

    H Sugita, H Ito, S Gomi, K Okada, K Masu

    ADVANCED METALLIZATION CONFERENCE 2004 (AMC 2004)   165 - 170   2004

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  • Reconfigurable RF circuit design for multi-band wireless chip

    Y Yoshihara, H Sugawara, H Ito, K Okada, K Masu

    PROCEEDINGS OF 2004 IEEE ASIA-PACIFIC CONFERENCE ON ADVANCED SYSTEM INTEGRATED CIRCUITS   418 - 419   2004

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  • Differential transmission line interconnect for high speed and low power global wiring

    S Gomi, K Nakamura, H Ito, K Okada, K Masu

    PROCEEDINGS OF THE IEEE 2004 CUSTOM INTEGRATED CIRCUITS CONFERENCE   325 - 328   2004

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  • Differential Transmission Line Structure for Over 10 Gbps Signal Transmission at Global Interconnect in Si ULSI

    ITO H.

    IEEE Asia-Pacific Conference on Advanced System Integrated Circuits, Aug., 2004   2004

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  • Wideband LC-VCO with Dynamic Reconfiguration

    YOSHIHARA Yoshiaki, SUGAWARA Hirotaka, ITO Hiroyuki, OKADA Kenichi, MASU Kazuya

    Technical report of IEICE. VLD   103 ( 476 )   247 - 251   2003.11

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    Language:Japanese   Publisher:The Institute of Electronics, Information and Communication Engineers  

    We propose reconfigurable RF circuit design. Dynamic reconfiguration provides Multi-function circuits and improves design productivity. As the elemental technology, wideband LC-VCO is designed. LC-VCO can be tuned from 2.4GHz to 5.1GHz using on-chip variable inductor.

    CiNii Books

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  • Wideband LC - VCO with Dynamic Reconfiguration

    YOSHIHARA Yoshiaki, SUGAWARA Hirotaka, ITO Hiroyuki, OKADA Kenichi, MASU Kazuya

    2003 ( 120 )   277 - 281   2003.11

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    Language:Japanese   Publisher:Information Processing Society of Japan (IPSJ)  

    We propose reconfigurable RF circuit design. Dynamic reconfiguration provides Multi-function circuits and improves design productivity. As the elemental technology, wideband LC-VCO is designed. LC-VCO can be tuned from 2.4GHz to 5.1GHz using on-chip variable inductor.

    CiNii Books

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    Other Link: http://id.nii.ac.jp/1001/00027391/

  • Wideband Bus Structure Using Differential Transmission Line on Si ULSI

    Ito Hiroyuki, Okada Kenichi, Masu Kazuya

    Proceedings of the Society Conference of IEICE   2003   55 - 55   2003.9

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  • Low Crosstalk Differential Transmission Line Interconnect on Si ULSI

    H. Ito, S. Gomi, H. Sugawara, K, Okada, K. Masu

    Advanced Metallization Conference   9 - 10   2003

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  • 26a-ZA-4 A Simple Model of Excitable Media with Dispenson and Curvature I

    Ito Hiroyuki

    1992 ( 3 )   451 - 451   1992.9

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    Language:Japanese   Publisher:The Physical Society of Japan (JPS)  

    CiNii Books

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▼display all

Presentations

  • On-chip high-Q spiral Cu inductors embedded in wafer-level chip-scale package for silicon RF application

    IEEE MTT-S International Microwave Symposium  2004 

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  • 高速プリント基板配線のばらつき特性に関する評価

    電子情報通信学会シリコンアナログRF研究会  2008 

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  • W帯オンウエハS行列測定のためのディエンベディング手法

    電子情報通信学会 総合大会  2008 

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  • WLP技術を用いた低位相雑音なCMOS電圧制御発振器

    電子情報通信学会 総合大会  2008 

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  • Small-Area CMOS RF Distributed Mixer Using Multi-Port Inductors

    IEEE/ACM Asia and South Pacific Design Automation Conference (Design Contest)  2008 

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  • LVDS-type On-Chip Transmision Line Interconnect with Passive Equalizers in 90 nm CMOS Process

    IEEE/ACM Asia and South Pacific Design Automation Conference (Design Contest)  2008 

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  • RF CMOS Circuits with Wafer-Level Packaging Inductors

    International Wafer-Level Packaging Conference  2008 

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  • 低消費電力オンチップパルス伝送線路配線

    電子情報通信学会 総合大会  2008 

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  • WLP技術を用いた低雑音増幅器の検討

    電子情報通信学会 総合大会  2008 

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  • 高速プリント基板配線の特性ばらつきに関する検討

    春季第55回応用物理学会  2008 

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  • 低消費電力オンチップパルス伝送線路配線

    電子情報通信学会シリコンアナログRF研究会  2008 

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  • An Over-12-Gbps On-Chip Transmission Line Interconnect with a Pre-Emphasis Technique in 90 nm CMOS

    17th Conference on Electrical Performance of Electronic Packaging (EPEP)  2008 

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  • A 2-GHz-band CMOS Low Noise Amplifier with High-Q Inductors Embedded in Wafer-Level Package

    International Conference on Solid State Devices and Materials (SSDM)  2008 

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  • An 8Gbps 2.5mW On-Chip Pulsed-Current-Mode Transmission Line Interconnect with a Stacked-Switch Tx

    The 34th European Solid-State Circuits Conference  2008 

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  • A 1.7-GHz 1.5-mW Digitally-Controlled FBAR Oscillator with 0.03-ppb Resolution

    The 34th European Solid-State Circuits Conference  2008 

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  • プリエンファシスを用いたオンチップ伝送線路配線の実測評価

    電子情報通信学会ソサイエティ大会  2008 

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  • RF CMOS 低雑音増幅回路特性のプロセス世代依存性

    2008 

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  • A Multi-Drop Transmission-Line Interconnect in Si LSI

    Asia and South Pacific Design Automation Conference  2007 

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  • RF CMOS Circuits with Wafer-Level Packaging Inductors

    International Wafer-Level Packaging Conference  2008 

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  • An Over-12-Gbps On-Chip Transmission Line Interconnect with a Pre-Emphasis Technique in 90 nm CMOS

    17th Conference on Electrical Performance of Electronic Packaging (EPEP)  2008 

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  • エッジパルス信号による低電力オンチップ高速伝送線路配線技術

    電子情報通信学会ソサイエティ大会  2008 

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  • Signal transmission through interconnects with repetitive loads

    Advanced Metallization Conference (AMC)  2007 

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  • A 0.49-6.50GHz Wideband LC-VCO with High-IRR in a 180 nm CMOS Technology

    International Conference on Solid State Devices and Materials (SSDM)  2007 

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  • A 8-Gbps Low-Latency Multi-Drop On-Chip Transmission Line Interconnect with 1.2-mW Two-Way Transceivers

    IEEE Symposium on VLSI Circuits  2007 

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  • A Low-Latency and High-Power-Efficient On-Chip LVDS Transmission Line Interconnect for an RC Interconnect Alternative

    IEEE International Interconnect Technology Conference (IITC)  2007 

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  • A Low-Power Differential Transmission Line Interconnect using Wafer Level Package Technology

    IEEE Workshop on Signal Propagation on Interconnects (SPI)  2008 

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  • A 1.7-GHz 1.5-mW Digitally-Controlled FBAR Oscillator with 0.03-ppb Resolution

    The 34th European Solid-State Circuits Conference  2008 

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  • A simple de-embedding method for characterization of on-chip four-port networks

    Advanced Metallization Conference (AMC)  2008 

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  • A Low Phase Noise LC-VCO with a High-Q Inductor Fabricated by Wafer Level Package Technology

    Radio Frequency Integrated Circuits Symposium 2008 (RFIC 2008)  2008 

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  • A Simple Through-Only De-Embedding Method for On-Wafer S-Parameter Measurements up to 110 GHz

    EEE MTT-S International Microwave Symposium2008 (IMS 2008)  2008 

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  • CMOSインバータ型広帯域可変利得増幅器の検討

    2008 

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  • 広帯域CMOS 差動型リングVCO

    電子情報通信学会ソサイエティ大会  2008 

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  • A 2-GHz-band CMOS Low Noise Amplifier with High-Q Inductors Embedded in Wafer-Level Package

    International Conference on Solid State Devices and Materials (SSDM)  2008 

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  • An 8Gbps 2.5mW On-Chip Pulsed-Current-Mode Transmission Line Interconnect with a Stacked-Switch Tx

    The 34th European Solid-State Circuits Conference  2008 

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  • CMOS RF パワーアンプにおけるプロセス世代依存性

    電子情報通信学会ソサイエティ大会  2008 

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  • On-chip high-Q spiral Cu inductors embedded in wafer-level chip-scale package for silicon RF application

    IEEE MTT-S International Microwave Symposium  2004 

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  • 性能指数に基づくオンチップ伝送線路配線の有効性評価

    電子情報通信学会 ソサイエティ大会  2006 

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  • オンチップRF受動素子のオンウエハ測定技術に関する検討

    電子情報通信学会シリコンアナログRF研究会  2006 

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  • A Low-Power Low-Phase-Noise CMOS VCO using RF SiP Technology

    Asia-Pacific Microwave Conference (APMC)  2007 

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  • Signal transmission through interconnects with repetitive loads

    Advanced Metallization Conference, Asian Session (ADMETA)  2007 

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  • High Frequency Characteristics of On-Chip Wirings up to 110 GHz

    Advanced Metallization Conference, Asian Session (ADMETA)  2007 

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  • High Frequency Characteristics of On-Chip Wirings up to 110 GHz

    Advanced Metallization Conference (AMC)  2007 

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  • ワンチップ無線通信回路に向けたWL-CSP方向性結合器の検討

    電子情報通信学会 総合大会  2006 

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  • A Design Guideline of On-Chip Differential Transmission Line Structure for High-Frequency Signal Transmission

    IEEE Workshop on Signal Propagation on Interconnects (SPI)  2006 

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  • A Design Guideline of On-Chip Differential Transmission Line Structure for High-Frequency Signal Transmission

    IEEE Workshop on Signal Propagation on Interconnects (SPI)  2006 

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  • A 5.2GHz CMOS Low Noise Amplifier with High-Q Inductors Embedded in Wafer-Level Chip-Scale Package

    International Workshop on RF Integration Technology (RFIT)  2007 

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  • Signal transmission through interconnects with repetitive loads

    Advanced Metallization Conference (AMC)  2007 

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  • ウエハ・レベル・パッケージ再配線の高周波特性

    電子情報通信学会シリコンアナログRF研究会  2007 

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  • WLCSP技術を利用したオンチップ伝送線路配線の検討

    電子情報通信学会ソサイエティ大会  2007 

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  • オンチップ伝送線路配線における低電力パルス伝送用駆動回路

    電子情報通信学会ソサイエティ大会  2007 

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  • プリエンファシス技術を用いたオンチップ差動伝送線路配線の検討

    電子情報通信学会ソサイエティ大会  2007 

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  • 伝送線路を用いた多対多オンチップ高速配線の実測による評価

    電子情報通信学会ソサイエティ大会  2007 

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  • 益研での高周波CMOS回路設計事例

    2007 

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  • 双方向・多対多伝送可能なオンチップ伝送線路配線の評価

    VDECデザイナーフォーラム  2007 

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  • WLCSP技術を用いた低消費電力オンチップ伝送線路配線の設計

    VDECデザイナーフォーラム  2007 

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  • 異なる減衰特性を有する配線からの漏話を考慮した実効減衰量

    電子情報通信学会 総合大会  2007 

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  • 「グローバル配線」オンチップ伝送線路配線技術

    2007 

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  • WLCSP技術を用いた高FoM 電圧制御発振器の検討

    電子情報通信学会ソサイエティ大会  2007 

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  • 90nm CMOSオンチップLVDS型伝送線路配線に関する検討

    電子情報通信学会シリコンアナログRF研究会  2007 

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  • A 8-Gbps Low-Latency Multi-Drop On-Chip Transmission Line Interconnect with 1.2-mW Two-Way Transceivers

    IEEE Symposium on VLSI Circuits  2007 

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  • A Low-Latency and High-Power-Efficient On-Chip LVDS Transmission Line Interconnect for an RC Interconnect Alternative

    IEEE International Interconnect Technology Conference (IITC)  2007 

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  • 90nm CMOSテクノロジーを利用した2.7mW/10GbpsオンチップLVDS型伝送線路配線

    2007 

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  • WLCSP技術を用いた広帯域低雑音増幅器の検討

    電子情報通信学会ソサイエティ大会  2007 

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  • マルチバンドRFフロントエンドに向けた低雑音増幅器の研究

    STARCシンポジウム  2007 

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  • 0.4~6GHzマルチスタンダード無線通信回路実現に向けた広帯域電圧制御発振器の研究

    STARCシンポジウム  2007 

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  • A 0.49-6.50GHz Wideband LC-VCO with High-IRR in a 180 nm CMOS Technology

    International Conference on Solid State Devices and Materials (SSDM)  2007 

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  • 高イメージ抑圧比・周波数可変域拡張回路を用いたCMOS電圧制御発振器

    電子情報通信学会ソサイエティ大会  2007 

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  • WLCSP技術を用いた可変電力増幅器の検討

    電子情報通信学会ソサイエティ大会  2007 

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  • Signal transmission through interconnects with repetitive loads

    Advanced Metallization Conference, Asian Session (ADMETA)  2007 

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    Presentation type:Poster presentation  

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  • High Frequency Characteristics of On-Chip Wirings up to 110 GHz

    Advanced Metallization Conference, Asian Session (ADMETA)  2007 

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  • High Frequency Characteristics of On-Chip Wirings up to 110 GHz

    Advanced Metallization Conference (AMC)  2007 

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  • 性能指数に基づくオンチップ配線技術評価 ― 長距離配線における伝送線路配線の有効性 ―

    応用物理学会シリコンテクノロジー分科会  2007 

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  • A Multi-Drop Transmission-Line Interconnect in Si LSI

    Asia and South Pacific Design Automation Conference  2007 

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  • A 5.2GHz CMOS Low Noise Amplifier with High-Q Inductors Embedded in Wafer-Level Chip-Scale Package

    International Workshop on RF Integration Technology (RFIT)  2007 

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  • A Low-Power Low-Phase-Noise CMOS VCO using RF SiP Technology

    Asia-Pacific Microwave Conference (APMC)  2007 

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  • Si CMOSプロセスによる右手・左手系伝送線路

    電子情報通信学会 総合大会  2007 

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  • 非対称Txを用いたオンチップ差動伝送線路配線におけるスケーリングの影響の検討

    電子情報通信学会 総合大会  2007 

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  • ダイアゴナル構造を用いた高密度高速プリント基板配線の研究

    電子情報通信学会 総合大会  2007 

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  • Small-Area CMOS RF Distributed Mixer Using Multi-Port Inductors

    IEEE/ACM Asia and South Pacific Design Automation Conference (Design Contest)  2008 

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  • LVDS-type On-Chip Transmision Line Interconnect with Passive Equalizers in 90 nm CMOS Process

    IEEE/ACM Asia and South Pacific Design Automation Conference (Design Contest)  2008 

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  • A simple de-embedding method for characterization of on-chip four-port networks

    Advanced Metallization Conference (AMC)  2008 

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  • A Low Phase Noise LC-VCO with a High-Q Inductor Fabricated by Wafer Level Package Technology

    Radio Frequency Integrated Circuits Symposium 2008 (RFIC 2008)  2008 

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  • A Simple Through-Only De-Embedding Method for On-Wafer S-Parameter Measurements up to 110 GHz

    EEE MTT-S International Microwave Symposium2008 (IMS 2008)  2008 

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  • A Low-Power Differential Transmission Line Interconnect using Wafer Level Package Technology

    IEEE Workshop on Signal Propagation on Interconnects (SPI)  2008 

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  • オンチップネットワークへの利用を目指した低電力パルス伝送線路回路

    LSIとシステムのワークショップ2009  2009 

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  • インダクタレスRF CMOS低雑音増幅回路の検討

    LSIとシステムのワークショップ2009  2009 

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  • S-parameter-based modal decomposition of multiconductor transmission lines and its application to de-embedding

    International Conference on Microelectronic Test Structures (ICMTS)  2009 

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  • インバータ構成を用いたスケーラブル広帯域RF CMOS低雑音増幅器の検討

    2009 年 電子情報通信学会総合大会  2009 

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  • 90nmプロセスによる20Gb/sNear-Rail-to-Rail ロジック動作1:4 DEMUX

    電子情報通信学会 シリコンアナログRF研究会  2009 

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  • A 20 Gb/s 1:4 DEMUX with Near-Rail-to-Rail Logic Swing in 90 nm CMOS process

    2009 IEEE MTT-S International Microwave Workshop Series on Signal Integrity and High-Speed Interconnects (IMWS2009-R9)  2009 

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  • S-parameter-based modal decomposition of multiconductor transmission lines and its application to de-embedding

    International Conference on Microelectronic Test Structures (ICMTS)  2009 

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  • Investigation of Scalable Wideband RF CMOS Low Noise Amplifier Using Inveter Construction

    2009 

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  • A 20 Gb/s 1:4 DEMUX with Near-Rail-to-Rail Logic Swing in 90 nm CMOS process

    2009 IEEE MTT-S International Microwave Workshop Series on Signal Integrity and High-Speed Interconnects (IMWS2009-R9)  2009 

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Research Projects

  • セルフパワードウェアラブル口腔内情報モニタリングシステムの開発

    Grant number:25K02817  2025.4 - 2028.3

    日本学術振興会  科学研究費助成事業  基盤研究(B)

    依田 信裕, 土方 亘, 伊藤 浩之, 柳田 保子, 鷲尾 純平, 佐々木 啓一, 日原 大貴

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    Grant amount:\18720000 ( Direct Cost: \14400000 、 Indirect Cost:\4320000 )

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  • Creation of ultra-low-power wireless technology using interference waves.

    Grant number:24K00939  2024.4 - 2027.3

    Japan Society for the Promotion of Science  Grants-in-Aid for Scientific Research  Grant-in-Aid for Scientific Research (B)

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    Grant amount:\18330000 ( Direct Cost: \14100000 、 Indirect Cost:\4230000 )

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  • 静電誘導型発電シートを用いたウェアラブル型リアルタイム咬合力測定方法の開発

    Grant number:21K09969  2021.4 - 2024.3

    日本学術振興会  科学研究費助成事業  基盤研究(C)

    依田 信裕, 佐々木 啓一, 土方 亘, 伊藤 浩之

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    Grant amount:\4160000 ( Direct Cost: \3200000 、 Indirect Cost:\960000 )

    本研究は,ヒト口腔内における噛みしめや咀嚼などの機能時における歯列上の咬合接触状態,ならびに同部位にて発揮される咬合力を調査可能なセンシングデバイスとして,加わる圧縮力に応じて発電量が変化する特性を有する「静電誘導型発電シート」の活用方法を探索した.これまで研究分担者の東工大の土方らが開発した「静電誘導型口腔内発電シート」を改良し,このシートを歯科一般臨床においてマウスガードや,オクルーザルスプリント等にて用いられている樹脂製シートに埋め込み、上下の歯の接触の有無,その咬合接触部位,ならびに同部における咬合力を発電量変化から解析するシステムの構築を試みた.
    現時点では,発電シートを埋め込んだオクルーザルスプリントへ,既知の荷重を負荷するベンチテストを実施し,荷重時の出力電圧を測定し,その出力値の妥当性を検証した.この結果,発電シートを用いた測定装置からの出力値の高い精度が示され,口腔内荷重測定装置としての妥当性が検証されている.
    また,今回の装置におけるセンサノードにおいては,咬合負荷により発生する電流をデジタル信号に変換して無線通信で外部に送信する方式とし,口腔内における安全性を考慮した無線電力供給方式の導入を計画している.このバッテリーレス動作を実現するため,無線通信部の低消費電力化として低電力インパルス無線送信機の利用可能性について検討し,プリント基板に右図のチップとインピーダンスマッチング用素子,コネクタを実装し測定を行い,3kbpsの場合の消費電力は0.34μWと無線による十分な給電の可能性を示した.

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  • ヘテロジニアス微小ノード群による無線通信機能の創発

    Grant number:19H02191  2019.4 - 2023.3

    日本学術振興会  科学研究費助成事業  基盤研究(B)

    伊藤 浩之

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    Grant amount:\17030000 ( Direct Cost: \13100000 、 Indirect Cost:\3930000 )

    昨年度までに得られた知見をベースに,アドホック化技術とセンサデータ伝送の実証に関して研究を進めた.また,昨年度開発した弛張発振器型センサ回路についてドリフトの原因特定と改善方法検討のためにプリント基板を作成した.発振周期と温度特性の関係を実測した結果から,温度依存性を補正することでドリフトを改善できることを示した.発振器型センサ回路技術を活用した極低消費電力無線センサチップを180nm Si CMOSプロセスで設計・製造した.さらに,本研究で扱う分散型センシングの実際のアプリケーションを考えた場合に,超小型無線センサ同士が相互作用できないケースも考えうることから,昨年実施した研究を発展させて,カオスダイナミクスも利用する方法を発明した.この方法では,まず,各センサをカオス発振器に接続し,測定値に依存する周波数を含む送信信号を生成する.小さなニューラルネットワークを介して,信号のスペクトルの重ね合わせを考慮することにより,センサの母集団における平均値など測定値の統計的分布の側面をニューラルネットワークで推定する.この手法を理論的かつ実験的に検証し,成果を学術論文誌 (Chaos, Solitons & Fractals, インパクトファクター5.944) で公開した.

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  • Study for optimal denture design based on the load beneath the denture base measured using an in-vivo wearable device

    Grant number:18K09651  2018.4 - 2021.3

    Japan Society for the Promotion of Science  Grants-in-Aid for Scientific Research  Grant-in-Aid for Scientific Research (C)

    Yoda Nobuhiro

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    Grant amount:\4420000 ( Direct Cost: \3400000 、 Indirect Cost:\1020000 )

    Bone tissue exhibits metabolic activity in response to the mechanical stress to the bone, resulting in bone resorption, bone addition, or alteration of trabecular structure. Therefore, inappropriate mechanical stress on the oral tissue may be a factor regarding the resorption of peri-implant bone and/or the mandibular bone beneath the denture base. In order to maintain the healthy mandible for a long time, it is necessary to understand the occlusal force applied to the dentition and the force beneath the denture base during daily function.
    This study attempted to develop some sensor system for measuring the load on the oral tissues during the daily function. For this purpose, the method for fixing the sensors to the oral devices, the method for output analysis, and basic technology for making the sensor systems wearable, which were essential for developing a new device for measuring the daily functional force in human mouth.

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  • Study on soil water content measurement technique based on transmission line theory

    Grant number:15K18046  2015.4 - 2018.3

    Japan Society for the Promotion of Science  Grants-in-Aid for Scientific Research  Grant-in-Aid for Young Scientists (B)

    Ito Hiroyuki

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    Grant amount:\4160000 ( Direct Cost: \3200000 、 Indirect Cost:\960000 )

    This work has studied sensor technology to measure water content of soil, improvement method of resolution and accuracy, and ion-concentration measurement technique for soil by exploiting frequency dependence of complex permittivity. We have proposed the new thin probe technique which uses interference between transmitted waves and reflected waves with soil influence. In our measurement, variation was 2.3% in the range of 20% to 35% water content. Measurements to improve accuracy and to consider influence of soil ions were conducted. The complex permittivity is hardly affected by fertilizer from 10GHz to 25GHz in our measurement.

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  • A Study on Highly Efficient Energy Harvesting Circuits and Systems

    Grant number:24656181  2012.4 - 2015.3

    Japan Society for the Promotion of Science  Grants-in-Aid for Scientific Research  Grant-in-Aid for Challenging Exploratory Research

    ISHIHARA Noboru, MASU Kazuya, ITO Hiroyuki

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    Grant amount:\3900000 ( Direct Cost: \3000000 、 Indirect Cost:\900000 )

    To utilize the environmental energy (EE) extremely, an energy harvesting (EH) circuit techniques were pursued and following results were obtained. (i) An EH CMOS circuit that can convert a weak radio frequency energy to electric power was clarified and its validity was confirmed by fabricating the circuit with a 0.18-um CMOS technology. (ii) In order to charge energy harvested to a storage battery, a high-voltage output dc-dc up-converter is required. A dc-dc up-converter with the COMS technology was studied and the circuit that can output a high voltage exceeding transistor’s breakdown voltage was invented. (iii) An energy generation tree system (EGTS) that is integrated with different kinds of the energy harvesters was suggested to utilize the EE extremely. (iv) Autonomous distributed system controlling technique was clarified for the generic tree energy management. (v) And to implement the EGTS, the circuit and system design environment was built with the circuit simulator, SPICE.

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  • A Study on Cell-Size RF CMOS Transceiver Circuit Technology

    Grant number:24656225  2012.4 - 2014.3

    Japan Society for the Promotion of Science  Grants-in-Aid for Scientific Research  Grant-in-Aid for Challenging Exploratory Research

    ITO Hiroyuki

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    Grant amount:\3900000 ( Direct Cost: \3000000 、 Indirect Cost:\900000 )

    If wireless communication circuits could be equivalent to the size of a cell, they are not only distributed in environment for sensing information but can be injected into human body to cure illness such as cancer. The research purpose is to pursue utmost of small size and scalability of wireless communication circuit technology.
    We have studied wireless communication circuit architecture suitable for size reduction. Our technology was evaluated through simulation and measurement of integrated circuits, and we could show feasibility of wireless communication by the proposed circuit technology with much smaller size than the conventional one. Thus, the purpose of this work was achieved.

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  • 義脳チップを目指したinter-brain通信回路の研究

    Grant number:20760219  2008

    日本学術振興会  科学研究費助成事業  若手研究(B)

    伊藤 浩之

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    Grant amount:\1040000 ( Direct Cost: \800000 、 Indirect Cost:\240000 )

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  • Signal Integrity of Nano-Scale interconnect and Circuit

    Grant number:18063008  2006 - 2009

    Japan Society for the Promotion of Science  Grants-in-Aid for Scientific Research  Grant-in-Aid for Scientific Research on Priority Areas

    MASU Kazuya, ISHIHARA Noboru, SATO Takashi, AMAKAWA Shuhei, ITO Hiroyuki, OKADA Kenichi

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    Grant amount:\106000000 ( Direct Cost: \106000000 )

    Nano-scale MOSFET has enabled a great number of circuit elements can be integrated into a single chip. So far, MOSFET has been miniaturized according to a scaling scheme, however, the chip size has not been reduced because more functions is required to be implemented on one chip; interconnect delays of long wires limit digital circuit performance. Interconnect design is a never-ending issue with CMOS LSI. For long wiring, we have developed transmission line interconnect (TLI).
    In this project, we have developed (1) estimation of interconnect resource of nano-CMOS based on interconnect wire length distribution, (2) modeling of novel interconnect structure such as periodic scheme, multi-port analysis for cross-talk modeling, etc., (3) de-embedding method up to 100GHz which is essential in ultra high speed nano-CMOS circuit, (4) high-speed, low-latency, low-power, energy-efficient transmission line interconnect, which has been designed, fabricated and evaluated on 180nm, 90nm, and 65nm CMOS, and small area, low power, high-speed on-chip SER/DES circuits, (5) comparison of interconnect performance of transmission line, optical and wireless interconnects.

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  • Development of On-chip Nano-Scale Network Based on Communication Theory

    Grant number:16206034  2004 - 2007

    Japan Society for the Promotion of Science  Grants-in-Aid for Scientific Research  Grant-in-Aid for Scientific Research (A)

    MASU Kazuya, ITO Hiroyuki, SATO Takashi, AMAKAWA Shuhei, ISHIDA Koichi

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    Grant amount:\49790000 ( Direct Cost: \38300000 、 Indirect Cost:\11490000 )

    Si CMOS has been scaled according to the "Scaling Concept" and have achieved high performance, low power consumption, and high functionality. The Si CMOS has become the most important hardware in ubiquitous network. In 2013, hundred million transistors will be integrated on a one chip of 20mm square using 35nm technology and the operating frequency is expected to be over 20GHz. The Si CMOS is progressing toward Nano Scale era.
    In this work, the signal propagation is recognized to be just communication, and we have developed global wiring technology. The novel analytic expression has been derived for wire length distribution ; the wire length distribution and cumulative number of interconnects of real 130nm and 90nm CMOS chip are well expressed by our new model. We have developed global wiring technology based on differential transmission line ; 0.27pJ/bit transmission has been successfully achieved on 1cm long interconnect, and mutli drop transmission line interconnect has been also developed for future network on-chip technology. Furthermore, novel FoM (Figure of Merit) has been proposed to compare the performance of various interconnects ; the conventional RC line, the RC line using CNT (Carbon Nano Tube), transmission line interconnect which has been developed in this work, optical interconnect, and wireless interconnect. As a results, the FoM of the transmission line interconnect has most superior in the range of several hundred micron to several mm. This means the transmission line has been the best solution for global wiring.

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  • シリコン集積回路多層配線における伝送線路配線を用いた高速信号伝送の研究

    Grant number:04J04594  2004 - 2006

    日本学術振興会  科学研究費助成事業  特別研究員奨励費

    伊藤 浩之

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    Grant amount:\2800000 ( Direct Cost: \2800000 )

    近年、シリコン集積回路(Si LSI)の性能は、トランジスタ単体よりもむしろ長距離配線によって律速されている。本研究は、長距離配線の遅延と消費電力を低減させるために、差動伝送線路配線を用いたオンチップ超高速信号伝送技術を確立することを目的としている。
    高密度かつ高いクロストーク耐性を有するゼロクロストーク構造を提案した。提案する配線構造は従来のコプレナー構造と比較して55%高い実効的配線密度を有していた。また、実測によりゼロクロストーク構造が高いクロストーク耐性を有していることを示した。
    前年度90nm Si CMOSプロセスにより設計したLVDS型伝送線路配線を実測により評価した。5mmの伝送線路配線に10Gbpsの信号を2.7mWの消費電力で伝送させることができた。Energy per Bitは0.27pJ/bitであり、Energy per Bitに関してオンチップ伝送線路配線における世界最高性能を実現した。5mmの長さの従来のオンチップ配線と比較して遅延ばらつきが89%小さいことを示した。
    マルチドロップバスやクロック分配回路へ向けたオンチップ伝送線路の分岐方法を検討した。分岐部分において伝送線路に直接トランジスタを接続することによって信号品質の劣化なく信号を分岐できることがわかった。その知見をもとにマルチドロップバスを開発した。TxとRxの面積削減のために、TxとRxの両方の機能を有するTwo-way transceiverを開発した。また、Rx動作時にゲート接地型の増幅回路として動作させることでRxでの遅延を低減した。90nm Si CMOSプロセスを用いて6つの分岐を有するマルチドロップバスを試作し、測定結果から8Gbpsの信号を合計7.1mWの消費電力で伝送させることができた。Two-way transceiver一つあたりの消費電力は1.2mWであった。
    以上により、差動伝送線路を応用した低クロストーク高密度バス技術、差動伝送線路を応用したH-tree Mesh Hybrid型クロック分配回路を構築するための高速信号伝送技術と分岐技術を確立した。

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  • 集積回路における高速信号配線技術の研究

    2002

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    Grant type:Competitive

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  • Investigation of High-Speed Signal Transmission on Si CMOS LSI

    2002

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    Grant type:Competitive

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  • マルチバンドRF CMOS回路の研究

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    Grant type:Competitive

    マルチバンドかつスケーラブルなディジタルRFフロントエンドの実現を目指す.超低位相雑音発振器, 広帯域PLL/LNA/PA,WLPプロセスを利用した高Q受動素子なども研究する.

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  • Multi-band RF CMOS circuit

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    Grant type:Competitive

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