Updated on 2025/04/22

写真a

 
LI DONGJU
 
Organization
School of Engineering Assistant Professor
Title
Assistant Professor
External link

Degree

  • Doctor of Philosophy ( Tokyo Institute of Technology )

Research Interests

  • SOC Architecture Design, Biometric Authentication

  • Architecture

  • Embedded system

  • Biometrics Authentication

  • SOC Design

  • 画像処理

  • 生体認証

  • Algorithm

  • Fingerprint authentication

  • SOC 設計

  • 指紋認証組込アルゴリズム

Research Areas

  • Manufacturing Technology (Mechanical Engineering, Electrical and Electronic Engineering, Chemical Engineering) / Control and system engineering

Education

  • Tokyo Institute of Technology   Science of Engineering

    - 1998

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    Country： Japan

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  • Tokyo Institute of Technology   Graduate School, Division of Science and Engineering   Electrical and Electronics Engineering

    - 1998

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  • Liaoning University   Physics   Semiconductor device

    - 1984

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    Country： China

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  • 遼寧大学   物理   半導体デバイス物理

    - 1984

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    Country： China

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Research History

  • -:

    2000

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  • -:東京工業大学 理工学研究科、集積システム専攻 助手

    2000

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  • -:東京工業大学 工学部、理工学研究科、電気電子専攻 教務職員

    1998

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  • -:

    1998

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  • -:中国電子工業部東北微電子研究所VLSI設計部 Design Engineer

    1987

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  • -:

    1987

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Professional Memberships

MISC

  • Orientation Field Estimation for Embedded Fingerprint Authentication System

    Wei Tang, Dongju Li, Tsuyoshi Isshiki, Hiroaki Kunieda

    IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS   E93D ( 7 )   1918 - 1926   2010.7

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    Language：English   Publisher：IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG  

    Orientation field (OF) estimation is a fundamental process in fingerprint authentication systems. In this paper, a novel binary pattern based low-cost OF estimation algorithm is proposed. The new method consists of two modules. The first is block-level orientation estimation and averaging in vector space by pixel level orientation statistics. The second is orientation quantization and smoothing. In the second module, the continuous orientation is quantized into fixed orientations with sufficient resolution (interval between fixed orientations). An effective smoothing scheme on the quantized orientation space is also proposed. The proposed algorithm is capable of stably processing poor-quality fingerprint images and is validated by tests conducted on an adaptive OF matching scheme. The proposed algorithm is also implemented into a fingerprint System on Chip (SoC) to comfirm that it satisfies the strict requirements of embedded system.

    DOI： 10.1587/transinf.E93.D.1918

    Web of Science

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  • A unified performance estimation method for hardware and software components in multiprocessor system-on-chips

    Arif Ullah Khan, Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda

    IPSJ Transactions on System LSI Design Methodology   3   194 - 206   2010

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    Language：English  

    With the growing complexity of consumer embedded products and the improvements in process technology, multiprocessor system-on-chip (MPSoC) architectures have become widespread. These MPSoCs include not only multiple processors but also multiple dedicated hardware accelerators that can be designed from software programs, written in high-level languages like 'C', using high-level synthesis tools (HLS). Traditional techniques of HW/SW cosimulation are very slow and time consuming when used for exploring HW/SW partitioning strategies. There is a strong need for methodologies that quickly and accurately estimate the performance of such complex systems. In this paper, we present a system level performance estimation method for exploring the trade-off between hardware and software implementations in such "hybrid" MPSoC architectures. The key feature of our performance estimation is the unified timing model, in the form of a program trace graph (PTG) for both software executions on processors as well as the hardware blocks (finite state machines) synthesized by a HLS tool. The RTL code from the HLS tool is analyzed and its state transition graph is transformed into the PTG, which was originally developed for software timing annotations. These PTGs represent the workload of the computation that is driven by program execution traces in the form of 'Branch Bitstreams'. Our methodology allows highly accurate performance estimation under the existence of data dependent behavior of software and hardware components. © 2010 Information Processing Society of Japan.

    DOI： 10.2197/ipsjtsldm.3.194

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  • A Unified Performance Estimation Method for Hardware and Software Components in Multiprocessor System-On-Chips

    ARIF ULLAH KHAN, TSUYOSHI ISSHIKI, DONGJU LI, hiroaki kunieda

    IPSJ Transactions on System LSI Design Methodology   3   194 - 206   2010

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  • Orientation Field Extimation for Embedded Fingerprint Authentication System

    Wei Tang, Dongju Li, Tsuyoshi Isshiki, Hiroaki Kunieda

    IEICE transaction on Information and System   E93-D ( 7 )   1918 - 1926   2010

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  • Decomposition of task-level concurrency on C programs applied to the design of multiprocessor SoC

    Mohammad Zalfany Urfianto, Tsuyoshi Isshiki, Arif Ullah Khan, Dongju Li, Hiroaki Kunieda

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E91A ( 7 )   1748 - 1756   2008.7

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    Language：English   Publisher：IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG  

    A simple extension used to assist the decomposition of task-level concurrency within C programs is presented in this paper. The concurrency decomposition is meant to be used as the point of entry for Multiprocessor System-on-Chips (MPSoC) architectures' design-flow. Our methodology allows the (re)use of readily available reference C programs and enables easy and rapid exploration for various alternatives of task partitioning strategies; a crucial task that greatly influences the overall quality of the designed MPSoC. A test case using a JPEG encoder application has been performed and the results are presented in this paper.

    DOI： 10.1093/ietfec/e91-a.7.1748

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  • Low cost SoC design of H.264/AVC decoder for handheld video player

    Sumek Wisayataksin, Dongju Li, Tsuyoshi Isshiki, Hiroaki Kunieda

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E91A ( 4 )   1197 - 1205   2008.4

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    Language：English   Publisher：IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG  

    We propose a low cost and stand-alone platform-based SoC for H.264/AVC decoder, whose target is practical mobile applications such as a handheld video player. Both low cost and stand-alone solutions are particularly emphasized. The SoC, consisting of RISC core and decoder core, has advantages in terms of flexibility, testability and various I/O interfaces. For decoder core design, the proposed H.264/AVC coprocessor in the SoC employs a new block pipelining scheme instead of a conventional macroblock or a hybrid one, which greatly contribute to reducing drastically the size of the core and its pipelining buffer. In addition, the decoder schedule is optimized to block level which is easy to be programmed. Actually, the core size is reduced to 138 KGate with 3.5 kbyte memory. In our practical development, a single external SDRAM is sufficient for both reference frame buffer and display buffer. Various peripheral interfaces such as a compact flash, a digital broadcast receiver and a LCD driver are also provided on a chip.

    DOI： 10.1093/ietfec/e91-a.4.1197

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  • A Multiprocessor SoC architecture with efficient communication infrastructure and advanced compiler support for easy application development

    Mohammad Zalfany Urfianto, Tsuyoshi Isshiki, Arif Ullah Khan, Dongju Li, Hiroaki Kunieda

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E91A ( 4 )   1185 - 1196   2008.4

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    Language：English   Publisher：IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG  

    This paper presents a Multiprocessor System-on-Chips (MPSoC) architecture used as an execution platform for the new C-language based MPSoC design framework we are currently developing. The MPSoC architecture is based on an existing SoC platform with a commercial RISC core acting as the host CPU. We extend the existing SoC with a multiprocessor-array block that is used as the main engine to run parallel applications modeled in our design framework. Utilizing several optimizations provided by our compiler, an efficient inter-communication between processing elements with minimum overhead is implemented. A host-interface is designed to integrate the existing RISC core to the multiprocessor-array. The experimental results show that an efficacious integration is achieved, proving that the designed communication module can be used to efficiently incorporate off-the-shelf processors as a processing element for MPSoC architectures designed using our framework.

    DOI： 10.1093/ietfec/e91-a.4.1185

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  • Minutia Shape Indexing for Embedded Fingerprint Identification

    Wei Tang, Dongju Li, Tsuyoshi Isshiki, Hiroaki Kunieda

    IEICE transaction on Information and System   submitted   2008

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  • Low cost SoC design of H.264/AVC decoder for handheld video player

    Sumek Wisayataksin, Dongju Li, Tsuyoshi Isshiki, Hiroaki Kunieda

    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E91-A ( 4 )   1197 - 1205   2008

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    Language：English   Publisher：Institute of Electronics, Information and Communication, Engineers, IEICE  

    We propose a low cost and stand-alone platform-based SoC for H.264/AVC decoder, whose target is practical mobile applications such as a handheld video player. Both low cost and stand-alone solutions are particularly emphasized. The SoC, consisting of RISC core and decoder core, has advantages in terms of flexibility, testability and various I/O interfaces. For decoder core design, the proposed H.264/AVC coprocessor in the SoC employs a new block pipelining scheme instead of a conventional macroblock or a hybrid one, which greatly contribute to reducing drastically the size of the core and its pipelining buffer. In addition, the decoder schedule is optimized to block level which is easy to be programmed. Actually, the core size is reduced to 138 KGate with 3.5 kbyte memory. In our practical development, a single external SDRAM is sufficient for both reference frame buffer and display buffer. Various peripheral interfaces such as a compact flash, a digital broadcast receiver and a LCD driver are also provided on a chip. © 2008 The Institute of Electronics, Information and Communication Engineers.

    DOI： 10.1093/ietfec/e91-a.4.1197

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  • Fast and Accurate Singular Point Detection and Classfication on Quantized Orientation Field of Fingerprints

    Wei Tang, Dongju Li, Tsuyoshi Isshiki, Hiroaki Kunieda

    IEICE transaction on Information and System   accepted   2008

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  • Minutia Shape Indexing for Embedded Fingerprint Identification

    Wei Tang, Dongju Li, Tsuyoshi Isshiki, Hiroaki Kunieda

    IEICE transaction on Information and System   submitted   2008

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  • Decomposition of Task-Level Concurrency on C Programs Applied to the Design of Multiprocessor SoC

    TSUYOSHI ISSHIKI

    IEICE Trans. Fundamentals   E91-A ( 7 )   1748 - 1756   2008

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  • Fast and Accurate Singular Point Detection and Classfication on Quantized Orientation Field of Fingerprints

    Wei Tang, Dongju Li, Tsuyoshi Isshiki, Hiroaki Kunieda

    IEICE transaction on Information and System   accepted   2008

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  • A fingerprint matching using minutia ridge shape for low cost match-on-card systems

    AS Rikin, DJ Li, T Isshiki, H Kunieda

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E88A ( 5 )   1305 - 1312   2005.5

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    Language：English   Publisher：IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG  

    In recent years, there is an increasing trend of using bio-metric identifiers for personal authentication. Encouraged by advances in smart card technologies, the fingerprint matching gets increasingly embedded into smart cards for an effective personal authentication method. However, current generation of low cost smart cards are usually equipped with limited hardware resources such as an 8-bit or 16-bit microcontroller. The fingerprint matching typically is a time consuming, computationally intensive and costly process. Therefore, it is still a challenge to integrate the fingerprint matching into a smart card. In this paper, we present a fast memory-efficient fingerprint matching using minutia ridge shape feature. This feature offers advantages of smaller template size, smaller memory requirement, faster matching time and robust matching against image distortion over conventional minutiae-based feature. The implementation result shows that the proposed method can be embedded in smart cards for a real-time Match-on-Card system.

    DOI： 10.1093/uetfec/e88-a.5.1305

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  • A NOVEL FINGERPRINT SOC WITH BIT SERIAL FPGA ENGINE

    Yiwen Wang, Dongju Li, Tsuyoshi, Isshiki Hiroaki Kunieda

    Special on System LSI Design Technology and Design Automation   46 ( 6 )   1366 - 1373   2005

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  • A NOVEL FINGERPRINT SOC WITH BIT SERIAL FPGA ENGINE

    Yiwen Wang, Dongju Li, Tsuyoshi, Isshiki Hiroaki Kunieda

    Special on System LSI Design Technology and Design Automation   46 ( 6 )   1366 - 1373   2005

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  • Binary line-pattern algorithm for embedded fingerprint authentication system

    JQ Qi, DJ Li, T Isshiki, H Kunieda

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E87A ( 8 )   1879 - 1886   2004.8

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    Language：English   Publisher：IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG  

    A novel binary line-pattern algorithm for embedded fingerprint authentication system is introduced in this paper. In this algorithm, each line-pattern is a one-dimension binary matrix that describes the alternation pattern of ridge and valley in fingerprint image. Two parallel lines or two cross lines in a certain scope make up related line-pattern pair. Several such line-pattern pairs at different parts of a fingerprint image can describe another intrinsic feature besides traditional minutiae feature. Experimental results showed this algorithm was not only efficient but also effective. Furthermore, a hybrid fingerprint match scheme is also introduced in this paper. It has the following features: (i) minutiae matching is firstly carried out to calculate the similarity score between the query fingerprint and the template fingerprint, and moreover, the translation and rotation parameters are obtained at the same time; (ii) line-pattern algorithm is immediately performed based on the parameters obtained after minutiae matching to get another similarity score; (iii) the final matching score is the combination of the minutiae matching score and the line-pattern matching score. Experiments were conducted on the FVC2002 database and our private database respectively. Both of the results were inspiring. In detail, at the same FAR value, the FRR of this hybrid match algorithm is to be 2-8% lower than only minutiae-based matching algorithm.

    Web of Science

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  • A Novel SoC Architecture Embedded Bit Serial FPGA

    Yiwen Wang, Dongju Li, Tsuyosi Isshiki Hiroaki Kunieda

    IEEE Asia Pacific Conference on Circuit and System (APCCAS)   1 ( 1 )   111   2004

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  • A Novel SoC Architecture Embedded Bit Serial FPGA

    Yiwen Wang, Dongju Li, Tsuyosi Isshiki Hiroaki Kunieda

    IEEE Asia Pacific Conference on Circuit and System (APCCAS)   1 ( 1 )   111   2004

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  • Fast Fingerprint Classification based on Direction Pattern

    Jinqing Qi, Dongju Li, Tsuyoshi, Isshiki Hiroaki Kunieda

    IEICE Transaction on Fundamentals of Electronics, Communications and Computer Sciences, special section on Digital Signal Processing   E 87-A ( 8 )   2004

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  • Fast Fingerprint Classification based on Direction Pattern

    Jinqing Qi, Dongju Li, Tsuyoshi, Isshiki Hiroaki Kunieda

    IEICE Transaction on Fundamentals of Electronics, Communications and Computer Sciences, special section on Digital Signal Processing   E 87-A ( 8 )   2004

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  • New rate control method with minimum skipped frames for very low delay in H.263+codec

    T Adiono, T Isshiki, C Honsawek, K Ito, DJ Li, H Kunieda

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E85A ( 6 )   1396 - 1407   2002.6

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    Language：English   Publisher：IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG  

    A new H.263+ rate control method that has very low encoder-decoder delay, small buffer and low computational complexity for hardware realization is proposed in this paper. This method focuses on producing low encoder-decoder delay in order to solve the lip synchronization problem. Low encoder-decoder delay is achieved by improving target bit rate achievement and reducing processing delay. The target bit rate achievement is improved by allocating an optimum frame encoding bits, and employing a new adaptive threshold of zero vector motion estimation. The processing delay is reduced by simplifying quantization parameter computation, applying a new non-zero coefficient distortion measure and utilizing previous frame information in current frame encoding. The simulation results indicate very large number skipped frames reduction in comparison with the test model TMN8. There were 80 skipped frames less than that of TMN8 within a 380 frame sequence during encoding of a very high movement video sequence. The 27kbps target bit rate is achieved with insignificant difference for various types of video sequences. The simulation results also show that our method successfully allocates encoding bits, maintains small data at the encoder buffer and avoids buffer from overflow and underflow.

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  • New Rate Control Method with Minimum Skipped Frames for Very Low Delay in H.263+ Codec

    Trio Adiono Tsuyoshi, Isshiki Kazuhito Ito Dongju Li Chawalit Honsawek, Hiroaki Kunieda

    IEICE Trans. on Fundamentals of Electronics, Communications and Computer Science   E 85-A ( 06 )   1396 - 1407   2002

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  • System-MSPA Design of H.263+ Video Encoder/Decoder LSI for Videotelephony Applications

    Chawalit Honsawek Kazuhito Ito Tomohiko Ohtsuka Trio Adiono, Dongju Li, Tsuyoshi Isshiki Hiroaki KunieDa

    Transactions fundamentals, Special Section on VLSI Design and CAD Algorithms   E84-A ( 11 )   2614 - 2622   2001

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  • System-MSPA Design of H.263+ Video Encoder/Decoder LSI for Videotelephony Applications

    Chawalit Honsawek Kazuhito Ito Tomohiko Ohtsuka Trio Adiono, Dongju Li, Tsuyoshi Isshiki Hiroaki KunieDa

    Transactions fundamentals, Special Section on VLSI Design and CAD Algorithms   E84-A ( 11 )   2614 - 2622   2001

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  • Design optimization of VLSI array processor architecture for window image processing

    DJ Li, L Jiang, H Kunieda

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E82A ( 8 )   1475 - 1484   1999.8

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    Language：English   Publisher：IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG  

    In this paper; we present a novel architecture named as Window-MSPA architecture which targets to window operations in image processing. We have previously developed a Memory Sharing Processor Array (MSPA) for fast array processing with regular iterative algorithms. Window-MSPA tries to optimize the data I/O ports and the number of processing elements so as to reduce hardware cost. The input scheme of image data is restricted to row by row input which simplifies the I/O architecture. Under this practical I/O restriction, the fastest processings are achieved. In this paper, we present the general Window-MSPA design methodology for wide variety of applications.,its an practical application, we have already reported the design of MP@HL MPEG2 Motion Estimator LS1[13]. Design formulas for Window-MSPA architecture are given for various size of window: operations in image processing. Thus, the derived architecture is flexible enough to satisfy user's requirement for either area or speed.

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  • New VLSI array processor design for image window operations

    DJ Li, L Jiang, T Isshiki, H Kunieda

    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING   46 ( 5 )   635 - 640   1999.5

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    Language：English   Publisher：IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC  

    A novel architecture named Window-Memory Sharing Processor Array is proposed, which targets window operations in image processing. The architecture can be used not only for conventional image filtering, but also in practical window operations such as motion vector search in MPEG2. The derived architecture is flexible enough to satisfy user's requirement for either area or speed.

    DOI： 10.1109/82.769813

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  • Design Optimization of VLSI Array Processor Architecture for Window Image Processing

    Dongju Li Li Jiang, Hiroaki Kunieda

    The Institute of Electronics, Information and Communication Engineers Transactions(IEICE TRANS) on Fundamentals of Electronics, Communications and Computer Sciences, Special Section on Digital Signal Processing   E82-A ( 8 )   1475 - 1484   1999

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  • New VLSI array processor design for image window operations

    D. J. Li, L. Jiang, T. Isshiki, H. Kunieda

    IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing   46 ( 5 )   635 - 640   1999

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    Language：English   Publisher：IEEE  

    A novel architecture named Window-Memory Sharing Processor Array is proposed, which targets window operations in image processing. The architecture can be used not only for conventional image filtering, but also in practical window operations such as motion vector search in MPEG2. The derived architecture is flexible enough to satisfy user's requirement for either area or speed.

    DOI： 10.1109/82.769813

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  • Dedicated design of motion estimator with Bits Truncation fast algorithm

    L Jiang, DJ Li, S Haba, C Honsawek, H Kunieda

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E81A ( 8 )   1667 - 1675   1998.8

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    Language：English   Publisher：IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG  

    In this paper, a dedicated hardware design for motion estimation LSI of MPEG2 is presented. Combining our bits truncation adaptive pyramid (BTAP) algorithm with Window-MSPA architecture, the hardware cost is tremendously reduced without PSNR performance degradation For mean pyramid algorithm. The core of the test chip working at 83 MHz, performs a search range of +/-67 for image size of 1920 x 1152 and achieves video rate of 60 field/s. It can be used for HDTV purpose. The chip size is 4.8 mm x 4.8 mm with 0.5u 2-level metal CMOS technology. The result in this paper shows our promising future to realize one chip HDTV MPEG2 encoder.

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  • Programmble Design for Memory Sharing Processor Array

    Dongju Li, Hiroaki Kunieda

    1 ( 1 )   1997

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  • Programmble Design for Memory Sharing Processor Array

    Dongju Li, Hiroaki Kunieda

    1 ( 1 )   1997

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  • Memory Sharing Processor Array (MSPA) architecture

    DJ Li, H Kunieda

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E79A ( 12 )   2086 - 2096   1996.12

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    Language：English   Publisher：IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG  

    In this paper, a design of a new processor array architecture with effective data storage schemes which meets the practical requirement of a reduced number of processor elements is proposed. Its design method is shown to be drastically simpler than the popular systolic arrays. This processor array which we call Memory Sharing Processor Array (MSPA) consists of a processor array, several memory units, and some address generation hardware units used to minimize the number of I/O parts. MSPA architecture with its design methodology tries to overcome overlapping data storages, idle processing time and I/O bottleneck problems, which mostly degrade the performance of systolic architecture. It has practical advantages over the systolic array in the clew of area-efficiency, high throughput and practical input schemes.

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  • Automatic synthesis of a serial input multiprocessor array

    DJ Li, H Kunieda

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E79A ( 12 )   2097 - 2105   1996.12

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    Language：English   Publisher：IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG  

    Memory Sharing Processor Array (MSPA) architecture has been developed as an effective array processing architecture for both reduced data storages and increased processor cell utilization efficiency[ll. In this paper, the MSPA design methodology is extended to the VLSI synthesis of a serial input processor array (PA). Then, a new bit-serial input multiplier and a new data serial input matrix multiplier are derived from the new PA. These multipliers are superior to the conventional multipliers by their smaller number of logic-gate count.

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  • Automatic Synthesis of a Serial Input Multiprocessor Array

    Dongju Li, Hiroaki Kunieda

    The Institute of Electronics, Information and Communication Engineers Transactions(IEICE TRANS) on Fundamentals of Electronics, Communications and Computer Sciences, Special Section on VLSI Design and CAD Algorithms   E79-A ( 12 )   2097 - 2105   1996

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  • Memory Sharing Processor Array(MSPA) Architecture

    Dongju Li, Hiroaki Kunieda

    The Institute of Electronics, Information and Communication Engineers Transactions(IEICE TRANS) on Foundamentals of Electronics, Communications and Computer Sciences, Special Section on VLSI Design and CAD Algorithms   E79-A ( 12 )   2086 - 2096   1996

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Presentations

  • ASIC Design Methodology for MSPA Architecture and its application to Data-serial Matrix Multiplier

    1996 

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  • Memory Sharing Processor Array(MSPA) and its Design Methodology

    1996 

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  • Programmable Design for Memory Sharing Processor Array (MSPA)

    1996 

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  • Programmable Design for Memory Sharing Processor Array (MSPA)

    1997 

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  • ASIC Design Methodology for MSPA Architecture and its application to Data-serial Matrix Multiplier

    1996 

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  • Memory Sharing Processor Array(MSPA) and its Design Methodology

    1996 

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  • ASIC Array Processor Design for Regular Algorithm

    1996 

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  • Programmable Design for Memory Sharing Processor Array (MSPA)

    1996 

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  • Automatic design for Bit-serials MSPA architecture

    Proceedings of ASP-DAC'95 /CHDL'95 /VLSI'95  1995 

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  • Automatic design for Bit-serials MSPA architecture

    Proceedings of ASP-DAC'95 /CHDL'95 /VLSI'95  1995 

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  • Kunieda Unique Fingerprint Image Generation Algorithm for One Line Swipe Sensors

    Proceedings of International Conference on Information and Communication Technology for Embedded System(ICICTES 2010)  2010 

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  • Fast Search for Fingerprint Matching in Embedded System

    International Conference on Information and Communication Technology for Embedded System(ICICTES 2010)  2010 

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  • High-Speed Video Processing System-On-Chip Architecture Exploration

    International Conference on Information and Communication Technology for Embedded Systems  2010 

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  • Fast Search for Fingerprint Matching in Embedded System

    International Conference on Information and Communication Technology for Embedded Systems  2010 

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  • Unique Fingerprint Image Generation Algorithm for One Line Swipe Sensors

    International Conference on Information and Communication Technology for Embedded Systems  2010 

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  • Multiprocessor System-On-Chip Design Methodology Using Model-Based Tightly-Compled Thread Model

    International Conference on Information and Communication Technology for Embedded Systems  2010 

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  • A Novel Fingerprint Orientation Field Estimation Method

    International Conference on Information and Communication Technology for Embedded Systems  2010 

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  • Fingerprint Reference Point Extraction in Small Size Sensor Images

    International Conference on Information and Communication Technology for Embedded Systems  2010 

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  • Architecture of Dynamic Reconfigurable Neural Networks Based ib Network-on-Chip

    International Conference on Information and Communication Technology for Embedded Systems  2010 

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  • Fast Search for Fingerprint Matching in Embedded System

    International Conference on Information and Communication Technology for Embedded System(ICICTES 2010)  2010 

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  • Unique Fingerprint Image Generation Algorithm for One Line Swipe Sensors

    International Conference on Information and Communication Technology for Embedded Systems  2010 

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  • Multiprocessor System-On-Chip Design Methodology Using Model-Based Tightly-Coupled Thread Model

    International Conference on Information and Communication Technology for Embedded System(ICICTES 2010)  2010 

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  • Kunieda Unique Fingerprint Image Generation Algorithm for One Line Swipe Sensors

    Proceedings of International Conference on Information and Communication Technology for Embedded System(ICICTES 2010)  2010 

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  • Fast Search for Fingerprint Matching in Embedded System

    International Conference on Information and Communication Technology for Embedded Systems  2010 

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  • A Novel Fingerprint Orientation Field Estimation Method

    International Conference on Information and Communication Technology for Embedded Systems  2010 

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  • Multiprocessor System-On-Chip Design Methodology Using Model-Based Tightly-Compled Thread Model

    International Conference on Information and Communication Technology for Embedded Systems  2010 

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  • High-Speed Video Processing System-On-Chip Architecture Exploration

    International Conference on Information and Communication Technology for Embedded Systems  2010 

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  • Architecture of Dynamic Reconfigurable Neural Networks Based ib Network-on-Chip

    International Conference on Information and Communication Technology for Embedded Systems  2010 

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  • Multiprocessor System-On-Chip Design Methodology Using Model-Based Tightly-Coupled Thread Model

    International Conference on Information and Communication Technology for Embedded System(ICICTES 2010)  2010 

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  • Fingerprint Reference Point Extraction in Small Size Sensor Images

    International Conference on Information and Communication Technology for Embedded Systems  2010 

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  • H.264/AVC Decoder SoC Towards the Low Cost Mobile Video Player

    IEEE SOC Conference  2007 

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  • Embedded Software Development Flow and Verification for a Heterogeneous MPSoC Based on Tightly Coupled Thread Model

    Embedded Systems Symposium 2007  2007 

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  • H.264/AVC Decoder SoC Towards the Low Cost Mobile Video Player

    IEEE SOC Conference  2007 

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  • Embedded Software Development Flow and Verification for a Heterogeneous MPSoC Based on Tightly Coupled Thread Model

    Embedded Systems Symposium 2007  2007 

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  • FPGA IP Design and Verification for SOC implementation

    2004 

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  • FPGA IP Design and Verification for SOC implementation

    2004 

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  • Embedded Fingerprint Authentication System by TIT Venture BeyondLSI Inc

    2004 

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  • Template-Statistical based Fingerprint Classification

    2003 

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  • A Fingerprint Authentication Programmable SoC Featuring Run-time Reconfigurable Interface

    2003 

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  • Embedded Fingerprint Authentication System by TIT Venture BeyondLSI Inc

    2004 

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  • Small Memory Minutia Matching Method

    2003 

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  • A Fingerprint Authentication Programmable SoC Featuring Run-time Reconfigurable Interface

    2003 

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  • Realization of Fingerprint Identification Module on DSP Board

    2002 

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  • Small Memory Minutia Matching Method

    2003 

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  • Template-Statistical based Fingerprint Classification

    2003 

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  • Realization of Fingerprint Identification Module on DSP Board

    2002 

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  • Face Focus Coding Under H.263+ Video Coding Standard

    Proceedings of 2000 IEEE Asia-Pacific Conference on Circuits and Systems  2000 

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  • Minutia Ridge Shape Algorithm For Fast on Line Fingerprint Identification System

    2000 

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  • Face Focus Coding Under H.263+ Video Coding Standard

    Proceedings of 2000 IEEE Asia-Pacific Conference on Circuits and Systems  2000 

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  • Minutia Ridge Shape Algorithm For Fast on Line Fingerprint Identification System

    2000 

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  • System-MSPA design of H.263+ Video Encoder LSI for Face Focused Videotele phony

    Proceedings of 2000 IEEE Asia-Pacific Conference on Circuits and Systems  2000 

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  • A Novel Personal Identification Method Based on Minutia-ridge Shape Algorithm

    2000 

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  • Motion Estimator LSI for MPEG2 High level Standard

    Proceedings of Asia and Sourth Pacific design Automation Conference (ASP-DAC)  1999 

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  • Multimedia LSI Design Based on Window-MSPA Architecture

    1999 IEEE Internatinal Symposium on Intelligent Signal Processing and Communication Systems, (ISPACS'99) Thailand  1999 

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  • System-MSPA design of H.263+ Video Encoder LSI for Face Focused Videotele phony

    Proceedings of 2000 IEEE Asia-Pacific Conference on Circuits and Systems  2000 

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  • A Novel Personal Identification Method Based on Minutia-ridge Shape Algorithm

    2000 

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  • Motion Estimator LSI for MPEG2 High level Standard

    Proceedings of Asia and Sourth Pacific design Automation Conference (ASP-DAC)  1999 

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  • Multimedia LSI Design Based on Window-MSPA Architecture

    1999 IEEE Internatinal Symposium on Intelligent Signal Processing and Communication Systems, (ISPACS'99) Thailand  1999 

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  • Towards One Chip HDTV MPEG2 Encoder LSI

    Proceedings of IEEE Custom Intergrated Circuits Conference  1998 

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  • Array Architecture and Design for Image Window Operation Processing ASICs

    Proceedings of IEEE 1998 International Symposium on Circuit and Systems  1998 

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  • Programmable Design for Memory Sharing Processor Array (MSPA)

    1997 

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  • Array Architecture and Design for Image Window Operation Processing ASICs

    Proceedings of IEEE 1998 International Symposium on Circuit and Systems  1998 

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  • Towards One Chip HDTV MPEG2 Encoder LSI

    Proceedings of IEEE Custom Intergrated Circuits Conference  1998 

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  • New Array Processor Architecture for MPEG2 Motion Estimation

    1997 

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  • ASIC Array Processor Design for Regular Algorithm

    1996 

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  • New Array Processor Architecture for MPEG2 Motion Estimation

    1997 

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Research Projects

  • 並列処理プロセッサアーキテクチャ

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    Grant type：Competitive

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  • Embedded Fingerprint Authentication Algorithm

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    Grant type：Competitive

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  • 生体認証SOC

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    Grant type：Competitive

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  • Biometrics authentication SOC

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    Grant type：Competitive

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  • Array Processor Architecture

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    Grant type：Competitive

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  • 組込指紋認証アルゴリズム

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    Grant type：Competitive

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