記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：PERGAMON-ELSEVIER SCIENCE LTD  

In this paper, we report on the structure and characteristics of an indium gallium arsenide (InGaAs) channel fin field effect transistor (FinFET) with a regrown source/drain. The fabrication process we propose is suitable for forming a channel with a high aspect ratio. In simulations, the subthreshold characteristics and drain current (I-d) were improved by reducing the fin width. Following the simulations, fabricated devices showed improved gate controllability after the fin width was reduced. A short-channel device (L-ch = 50 nm, H-fin = 50 nm, and W-fin = 20 nm) showed an I-d of 367 mu A/mu m and a minimum subthreshold swing (SSmin) of 211 mV/dec at V-d = 0.5 V. The maximum-to-minimum I-d ratio was 10(5). (C) 2016 Elsevier Ltd. All rights reserved.

DOI： 10.1016/j.sse.2016.09.009

Web of Science

researchmap

記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：IOP PUBLISHING LTD  

The subthreshold slope of a conventional FET is over 60mV/dec at room temperature. One of the proposed devices capable of overcoming this limitation is a superlattice FET (SLFET). In this study, we determined the feasibility of an SLFET experimentally. To overcome the limitations of conventional FETs, we proposed a "leaned" superlattice structure for an FET. With the help of calculations, we fabricated InGaAs/AlAs triple-barrier p-i-n diodes instead of FETs. By using measurements recorded at room and low temperatures, we confirmed the change in slope at the expected bias through calculations. (C) 2016 The Japan Society of Applied Physics.

DOI： 10.7567/JJAP.55.118004

Web of Science

researchmap

記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：IOP PUBLISHING LTD  

In this paper, we propose a method to classify the tunneling currents using simulations. The main objective is to investigate the effects of the direct source-to-drain tunneling, which is undesirable, in the case of devices with extremely short channels. We performed the classification of tunneling currents in InGaAs/GaAsSb heterojunction double-gate tunnel FETs based on this method, and we found that the direct-tunneling component increased dramatically in short-channel cases. The channel length must be 20nm or longer, in case of InGaAs/GaAsSb heterojunction doublegate tunnel FETs, to limit the off-current within 10 pA/mu m, which is required as per the ITRS LP. (C) 2016 The Japan Society of Applied Physics

DOI： 10.7567/JJAP.55.070303

Web of Science

researchmap

記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：NATURE PUBLISHING GROUP  

HfS2 is the novel transition metal dichalcogenide, which has not been experimentally investigated as the material for electron devices. As per the theoretical calculations, HfS2 has the potential for well-balanced mobility (1,800 cm(2)/V.s) and bandgap (1.2 eV) and hence it can be a good candidate for realizing low-power devices. In this paper, the fundamental properties of few-layer HfS2 flakes were experimentally evaluated. Micromechanical exfoliation using scotch tape extracted atomically thin HfS2 flakes with varying colour contrasts associated with the number of layers and resonant Raman peaks. We demonstrated the I-V characteristics of the back-gated few-layer (3.8 nm) HfS2 transistor with the robust current saturation. The on/off ratio was more than 10(4) and the maximum drain current of 0.2 mu A/mu m was observed. Moreover, using the electric double-layer gate structure with LiClO4: PEO electrolyte, the drain current of the HfS2 transistor significantly increased to 0.75 mA/mu m and the mobility was estimated to be 45 cm(2)/V.s at least. This improved current seemed to indicate superior intrinsic properties of HfS2. These results provides the basic information for the experimental researches of electron devices based on HfS2.

DOI： 10.1038/srep22277

Web of Science

researchmap

記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：IOP PUBLISHING LTD  

A 60-nm-thick E-mode In0.65Ga0.35As/InAs/In0.65Ga0.35As high-electron-mobility transistor (HEMT) was successfully fabricated and evaluated by using Au/Pt/Ti-based non-annealed ohmic technology for high-speed and low-power logic applications. The device exhibited a minimal SS of 69mV/decade, a lower DIBL of 30mV/V, an ION/IOFF ratio above 1.2 x 10(4) at V-DS = 0.5V and a high f(T) of 378GHz and f(max) of 214GHz at V-DS = 1.0V. These results demonstrate that non-annealed ohmic contacts can be used for fabricating E-mode In0.65Ga0.35As/InAs/In0.65Ga0.35As HEMTs with excellent electrical characteristics. The fabricated HEMTs are likely to find use in future high-speed and low-power logic applications. (C) 2016 The Japan Society of Applied Physics.

DOI： 10.7567/APEX.9.026502

Web of Science

researchmap

記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：IOP PUBLISHING LTD  

A normally-off AlGaN/GaN high-electron-mobility transistor (HEMT) with a recessed-gate structure fabricated by novel digital etching is reported. Digital etching consists of multiple cycles of oxidation and wet etching of the oxide, and has the merits of easy control of the recess depth and reduction of surface damage in comparison with conventional dry etching. However, in conventional digital etching, the oxidation process involves the possibility of undercutting. In the digital etching, a reactive ion etcher was used and recess etching without any undercut was confirmed. Normally-off operation and the improvement of transconductance were confirmed in an AlGaN/GaN HEMT fabricated by this technique. (C) 2015 The Japan Society of Applied Physics

DOI： 10.7567/JJAP.54.06FG04

Web of Science

researchmap

記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：IOP PUBLISHING LTD  

The tunnel field-effect transistor (FET) has emerged as an attractive candidate for next-generation low-power-consuming devices. In tunnel FETs, a steep subthreshold slope (SS) and a low off-current are expected. However, the tunnel FETs have a lower on-current than conventional MOSFETs. To obtain a high on-current, the use of a heterojunction at the location of tunneling is effective. In this study, we confirmed that it was indeed effective to use heterojunctions for the tunnel FETs, and we revealed the dependences of SS and on-current on two parameters, namely, the equivalent oxide thickness (EOT) and body width, in the GaAsSb/InGaAs tunnel FET by a simulation study. We also verified the results experimentally. (C) 2015 The Japan Society of Applied Physics

DOI： 10.7567/JJAP.54.04DF10

Web of Science

researchmap

記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：NATURE PUBLISHING GROUP  

Metamaterials are artificially structured materials that can produce innovative optical functionalities such as negative refractive index, invisibility cloaking, and super-resolution imaging. Combining metamaterials with semiconductors enables us to develop novel optoelectronic devices based on the new concept of operation. Here we report the first experimental demonstration of a permeability-controlled waveguide optical modulator consisting of an InGaAsP/InP Mach-Zehnder interferometer with 'tri-gate' metamaterial attached on its arms. The tri-gate metamaterial consists of metal resonator arrays and triple-gate field effect elements. It changes its permeability with a change in the controlling gate voltage, thereby changing the refractive index of the interferometer arm to switch the modulator with an extinction ratio of 6.9 dB at a wavelength of 1.55 mm. The result shows the feasibility of InP-based photonic integrated devices that can produce new functions by controlling their permeability as well as their permittivity.

DOI： 10.1038/srep08985

Web of Science

PubMed

researchmap

記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：ELECTROCHEMICAL SOC INC  

In this study, a 60-nm enhancement-mode (E-mode) In0.65Ga0.35As/InAs/In0.65Ga0.35As high electron mobility transistor (HEMT) was developed, and its potential for use inhigh-speed and low-power logic applications was investigated. When the E-mode device was biased at a drain-source voltage of 0.5 V, it demonstrated a cutoff frequency of 169 GHz, drain-induced barrier lowering of 70 mV/V, minimum subthreshold swing of 67 mV/decade, and ION/IOFF ratio greater than 1.6 x 10(4). The high performance of the E-mode device is attributed to the use of a thin barrier layer along with Pt gate sinking technology. These results confirm that E-mode In0.65Ga0.35As/InAs/In0.65Ga0.35As HEMTs have great potential for use inhigh-speed and low-power logic applications. (C) 2015 The Electrochemical Society. All rights reserved.

DOI： 10.1149/2.0171512jss

Web of Science

researchmap

記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：IOP PUBLISHING LTD  

Electron beam lithography shot-pattern design technologies and a dedicated algorithm for patterning and miniaturization of the exposure area were investigated. Beam step-size fracturing was used to optimize the fill pattern at the designed pattern edges, and propagation loss was reduced for a 500-nm-wide Si wire waveguide with a 30 degrees tilt angle from 4.7 to 3.0 dB/cm using a conventional process. Furthermore, proximity effect correction technology allowed the integration of different trench widths for a 5 mu m spot-size converter and 1 mu m Si wire waveguide. The propagation loss was reduced to 2.1 dB/cm due to optimization of the dose density for each exposure area, and runtime was reduced to less than half. (C) 2014 The Japan Society of Applied Physics

DOI： 10.7567/JJAP.53.06JB04

Web of Science

researchmap

記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG  

The delay time component (tau(s)) of an InGaAs MOSFET caused by dynamic source resistance is discussed. On the basis of the relationship between the current density (J) and the dynamic source resistance (r(s)), the value of r(s) is proportional to 1/J with some offset at low current densities, whereas the offset becomes smaller in a region of high current density. The value of r(s) depends on the current in a way similar to rs. Because the offset in the high-current-density region is proportional to the square root of the effective mass, an InGaAs MOSFET with a small mass has a shorter r(s) than a Si MOSFET.

DOI： 10.1587/transele.E97.C.419

Web of Science

researchmap

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

Web of Science

researchmap

記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG  

InGaAs is a promising material that can replace the current Si nMOSFET in CMOS because of its high electron mobility. To realize a high drain current density at a low supply voltage in InGaAs, the introduction of a heavily doped source is essential. We introduced an epitaxially grown n-InP source and obtained a high drain current density. However, short-channel effects were observed in a previous study; thus, we introduced extremely-thin-body III-V-OI InGaAs MOSFETs on a Si substrate. Accounting for the channel-thickness dependence, a drain current density of 2.04A/mm at V-D = 0.5V and clear suppression of the short-channel effects were observed for a channel thickness of 10 nm.

DOI： 10.1587/elex.11.20140567

Web of Science

researchmap

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

High on-currents (I-on) and low off-currents (I-off) under low supply voltage are important for logic applications. A heavily doped InP source was introduced to demonstrate the existence of high I-on in InGaAs MOSFETs, and I-D = 2.4 mA/mu m at V-D = 0.5 V was observed. GaAsSb source was introduced in InGaAs tunnel FET to realize low I-off. Narrow channel body was found to be essential for steep sub-threshold (SS) dependence, and a fabricated GaAsSb/InGaAs vertical tunnel FET with a 26 nm wide body showed steep SS. In addition, an InGaAs/InP super-lattice source was studied to consider the possibility of simultaneous high I-on and low I-off realization.

DOI： 10.1109/ICIPRM.2014.6880570

Web of Science

researchmap

記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：JAPAN SOC APPLIED PHYSICS  

Gate leakage current mechanism in GaN high electron mobility transistors (HEMTs) has been studied using a two-dimensional thin surface barrier (TSB) model to represent two unintentional donor thin layers that exit under and outside the gate electrode due to the existence of surface defects. The donor thin layer outside the gate affects the reverse gate current at the high gate voltage above the pinch-off voltage. Higher donor concentration of thin layer outside the gate results in larger ratio of lateral to vertical components of the electric field at the gate edge. On the other hand, the electric field at the center of the gate has only the vertical electric field component. As a result, the two-dimensional effects are only important for the reverse gate current above the pinch-off voltage. We have confirmed in this paper that the simulation results provided by our model correlate very well with the experimental reverse gate current characteristics of the device for a very wide range of reverse gate voltage from 0.1 to 90 V. (C) 2013 The Japan Society of Applied Physics

DOI： 10.7567/JJAP.52.04CF12

Web of Science

researchmap

記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：JAPAN SOC APPLIED PHYSICS  

We fabricated a vertical metal-insulator-semiconductor field-effect transistor (MISFET) with a heterostructure launcher and an undoped channel. Vertical MISFETs exhibit a high drain current density; however, their large output conductance is a disadvantage for the open-circuit voltage gain. In a previous study, a maximum voltage gain of 4.0 was found in a vertical MISFET with a heavily doped drain region and a 45-nm-wide channel mesa. The heavily doped drain region and a narrower channel width are effective in reducing the output conductance. In this study, we fabricated a device with the heavily doped drain region and a 23-nm-wide channel mesa structure. It was observed that the output conductance decreased from 120 to 57 mS/mm at a drain current density of 0.3 MA/cm(2) with a narrower channel mesa. The maximum open-circuit voltage gain increased from 4.0 to 5.7. (C) 2013 The Japan Society of Applied Physics

DOI： 10.7567/JJAP.52.04CF05

Web of Science

researchmap

記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：JAPAN SOC APPLIED PHYSICS  

60 nm InAs high-electron-mobility transistors (HEMTs) with a thin channel, a thin InAlAs barrier layer, and a very high gate stem structure have been fabricated and characterized. The thickness of the channel, as well as that of the InAlAs barrier layer, was reduced to 5 nm. A stem height of 250 nm with a Pt-buried gate was used in the device configuration to reduce the parasitics. A high DC transconductance of 2114 mS/mm and a current-gain cutoff frequency (f(T)) of 710 GHz were achieved at V-DS 0.5V. (C) 2013 The Japan Society of Applied Physics

DOI： 10.7567/APEX.6.034001

Web of Science

researchmap

記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：IOP PUBLISHING LTD  

In this study, we present the fabrication and characterization of InGaSb/AlSb p-channel high-hole-mobility-transistor devices using inductively coupled plasma (ICP) etching with BCl3 gas. Devices fabricated by the dry etching technique show good DC and RF performances. Radio-frequency (RF) performance for devices with different source-to-drain spacing (L-SD) and gate length (L-g) were investigated. The fabricated 80-nm-gate-length p-channel device with 2-mu m LSD exhibited a maximum drain current of 86.2mA/mm with peak transconductance (g(m)) of 64.5mS/mm. The current gain cutoff frequency (f(T)) was measured to be 15.8 GHz when the device was biased at V-DS = -1.2 V and V-GS = 0.4 V. (C) 2013 The Japan Society of Applied Physics

DOI： 10.7567/JJAP.52.020203

Web of Science

researchmap

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

We demonstrated a sub-50-nm InGaAs 5-nm/InP 5-nm MOSFET with an n-InP source on a Si substrate using a 5-nm Al2O3 dielectric. In the measurement of the fabricated device, the maximum drain current and the peak transconductance at V-D = 0.5 V were 0.9 mA/mu m and 0.8 mS/m, respectively. The threshold voltage was 0.09 V, and the drain-induced barrier lowering was 378 mV/V. From the channel length dependence, clear suppression of the short channel effect by the 5-nm-thick Al2O3 gate dielectric and the extremely thin body III-V-OI structure was confirmed.

DOI： 10.1109/ICIPRM.2013.6562631

Web of Science

researchmap

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

An electrically-driven permeability-controlled GaInAsP/InP optical modulator was experimentally demonstrated using Tri-gate metamaterial structure. An extinction ratio of 6.9 dB was obtained at 1550-nm wavelength with a gate swing of 2-12 V.

Web of Science

researchmap

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

We fabricated an InP heterojunction bipolar transistor (HBT) with a 55-nm-wide emitter. For an emitter width of 55 nm and that greater than 300 nm, the maximum gain was around 15 and around 120, respectively. To confirm the relationship between the acceptable current density and the emitter width, we measured the current density when the current gain was half its maximum value. The measured current density J(half) increased with a decrease in the emitter width. The highest observed current density was approximately 5 MA/cm(2) and was nearly equal to the highest reported current density of InP HBTs.

DOI： 10.1109/ICIPRM.2012.6403354

Web of Science

researchmap

記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：JAPAN SOC APPLIED PHYSICS  

In this paper, we present the fabrication and characterization of 40 nm InAs-channel high-electron-mobility-transistor (HEMT) devices. Both DC and RF measurements were performed under various bias conditions. We have also extracted bias-dependent intrinsic device parameters to determine the optimum conditions of operation. It is concluded that a high current-gain cutoff frequency (f(T)) of 615 GHz can be achieved when the device is biased near the occurrence of impact ionization. (C) 2012 The Japan Society of Applied Physics

DOI： 10.1143/JJAP.51.110203

Web of Science

researchmap

記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG  

With the aim of achieving heterogeneous integration of compound semiconductors with silicon technology, the fabrication of an InP/InGaAs transferred-substrate HBT (TS-HBT) on a Si substrate is reported. A current gain of 70 and a maximum current density of 12.3 mA/mu m(2) were confirmed in a TS-HBT with a 340-nm-wide emitter. From microwave characteristics of the TS-HBT obtained after deembedding, a cutoff frequency (f(T)) of 510 GHz and a 26% reduction of the base-collector capacitance were estimated. However, the observed f(T) was too high for an HBT with a 150-nm-thick collector. This discrepancy can be explained by the error in de-embedding, because an open pad is observed to have large capacitance and strong frequency dependence due to the conductivity of the Si substrate.

DOI： 10.1587/transele.E95.C.1323

Web of Science

researchmap

記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG  

In this paper, we report a reduction in the access resistance of InP/InGaAs composite-channel metal-oxide-semiconductor field-effect-transistors (MOSFETs) with a back-source electrode. The source region has two electrodes. The source electrode on the surface side is connected to the channel through a doped layer and supplies the electrons. The back-source electrode is constructed under the channel layer and is insulated from the doped layer in order to avoid current leakage. The function of the back-source electrode is to increase the carrier concentration in the channel layer of the source region. In the simulation, the electron density in the channel layer is almost doubled by the effect of the back-source voltage. The fabricated I I I-V MOSFET has a channel length of 6 mu m. A 6% increase in the maximum drain current density (I-d) and a 6.8% increase in the transconductance (g(m)) (V-d = 2 V) are observed. The increase in the carrier density in the channel is estimated to be 20% when the applied voltage of the back-source electrode is 6 V.

DOI： 10.1587/transele.E95.C.904

Web of Science

researchmap

記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG  

In this paper, we report the reduction in the base-collector capacitance (C-BC) of InP/InGaAs double heterojunction bipolar transistors with buried SiO2 wires (BG-HBT). In a previous trial, we could not confirm a clear difference between the C-BC of the conventional HBT and that of the BG-HBT because the subcollector layer was thicker than expected. In this study, the interface between the collector and the subcollector was shifted to the middle of the SiO2 wires by adjusting the growth temperature, and a reduction in C-BC with buried SiO2 wires was confirmed. The estimated C-BC of the BG-HBT was 7.6 fF, while that of the conventional HBT was 8.6 fF. This 12% reduction was in agreement with the 10% reduction calculated according to the designed size.

DOI： 10.1587/transele.E95.C.917

Web of Science

researchmap

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

We fabricated a vertical tunnel field-effect transistor (TFET) with a GaAsSb/InGaAs heterojunction using a 5-nm-thick Al2O3 dielectric. The 26-nm width of the narrow channel mesa structure was confirmed using citric acid solution. The minimum sub-threshold slope (SS) was 71 mV/dec. On the basis of our simulated and experimental results, the SS was estimated to be 54 mV/dec for an effective oxide thickness (EOT) of 1 nm. © 2012 IEEE.

DOI： 10.1109/ICIPRM.2012.6403309

Web of Science

Scopus

researchmap

記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：IOP PUBLISHING LTD  

The rapid growth of high-frequency wireless communication demands high-performance packaging structures at low cost. A flip-chip interconnect is one of the most promising technologies owing to its low parasitic effect and high performance at high frequencies. In this study, the in-house fabricated In-0.6Ga0.4As metamorphic high electron mobility transistor (mHEMT) device was flip-chip-assembled using a commercially available low-cost organic substrate. The packaged device with the optimal flip-chip structure exhibited almost similar DC and RF results to the bare die. An exopy-based underfill was applied to the improvement of reliability with almost no degradation of the electrical characteristics. Measurement results revealed that the proposed packaging structure maintained a low minimum noise figure of 3 dB with 6 dB associated gain at 62 GHz. Such a superior performance after flip-chip packaging demonstrates the feasibility of the proposed low-cost organic substrate for commercial high-frequency applications up to the W-band. (C) 2011 The Japan Society of Applied Physics

DOI： 10.1143/JJAP.50.096503

Web of Science

researchmap

記述言語：英語   出版者・発行元：JAPAN SOC APPLIED PHYSICS  

DOI： 10.1143/APEX.4.099202

Web of Science

researchmap

記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG  

In this paper, we report the fabrication and device characteristics of InP/InGaAs double heterojunction bipolar transistors (DHBTs) with buried SiO2 wires. The SiO2 wires were buried in the collector and subcollector layers by metalorganic chemical vapor deposition toward reduction of the base-collector capacitance under the base electrode. A current gain of 22 was obtained at an emitter current density of 1.25 MA/cm(2) for a DHBT with an emitter width of 400 nm. The DC characteristics of DHBTs with buried SiO2 wires were the same as those of DHBTs without buried SiO2 wires on the same substrate. A current gain cutoff frequency (f(T)) of 213 GHz and a maximum oscillation frequency (f(max)) of 100 GHz were obtained at an emitter current density of 725 kA/cm(2).

DOI： 10.1587/transele.E94.C.830

Web of Science

researchmap

記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：JAPAN SOC APPLIED PHYSICS  

We have realized InP/InGaAs composite-channel metal-oxide-semiconductor field-effect transistors with both selectively regrown n(+)-InGaAs source/drain regions and Al2O3 as a gate dielectric. A 100-nm-long channel was fabricated by laterally buried regrowth in a channel undercut by metalorganic vapor phase epitaxy. The carrier density of the regrown layer was 2.9 x 10(19) cm(-3). A drain current I-d of 1.34 mA/mu m was achieved at a drain voltage V-d of 1 V and a gate voltage V-g of 3 V. A transconductance g(m) of 817 mu S/mu m at V-d = 0.65 V was also observed at the same time. The improvement in the subthreshold slope can be explained by the decrease in dielectric/semiconductor interface trap density. (C) 2011 The Japan Society of Applied Physics

DOI： 10.1143/APEX.4.054201

Web of Science

researchmap

記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC  

We investigated the relationship between the emitter charging time and the inverse current of heterojunction bipolar transistors. A proportional relationship assuming the Boltzmann approximation and constant capacitances is often used to separate the components of the total delay time; however, without the aforementioned assumption, the theoretical calculations show that the relationship is not proportional but has an intercept. This deviation causes a nonnegligible error in the results obtained at high current densities. Additionally, we show the possibility of reducing the total delay time beyond that inferred from the conventional linear characteristics by a high-current-density operation.

DOI： 10.1109/LED.2011.2107497

Web of Science

researchmap

記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：JAPAN SOC APPLIED PHYSICS  

A high-speed transistor operation is expected from using an undoped channel region. We propose a vertical InGaAs-channel metal-insulator-semiconductor field effect transistor (MISFET) with an ultra-narrow mesa structure, an undoped channel, and a heterostructure launcher. According to a Monte Carlo simulation, a cutoff frequency of 1.5 THz is expected when a 20-nm-wide mesa structure, a 60-nm-long channel, and a 5 MA/cm(2) drain current density are achieved. We fabricated an ultra-narrow mesa structure by using selective undercut etching. In the fabricated device, the channel mesa was 15nm wide, and the observed drain current density was 0.95A/mm. Because the channel mesa width was 15 nm, the drain current density per unit area was 6.3 MA/cm(2). A high current density was achieved for a short charging time. By comparing the drain current density of the 60-nm-long channel device with that of a 100-nm-long channel device, we inferred that quasi-ballistic transportation can be achieved in our devices. (C) 2011 The Japan Society of Applied Physics

DOI： 10.1143/JJAP.50.014102

Web of Science

researchmap

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

In this paper, we report InGaAs channel MOSFETs with an InP source contact. InP source contact enables the suppression of carrier starvation and the easy shrinkage of the channel length by anisotropic etching. In fabricated 50-nm InGaAs channel MOSFETs, I-D = 2.4A/mm at V-D=0.5V were observed. On the other hand, degradations of V-th and SS by the short channel effect were also observed. Thinner channels will be required in order to suppress this effect.

DOI： 10.1109/IEDM.2011.6131545

Web of Science

researchmap

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

To realize high-current-density FETs, heavily doped source regions are essential; however, ion implantation of III-V materials cannot supply a sufficiently high level of doping. Our approach to the realization of heavily doped source regions is based on epitaxially grown sources. One approach is the use of an InP/InGaAs composite channel MISFET with regrown InGaAs source/drain. When a gate length of 170 nm was used, I-d at V-d = 1 V was 1.34 A/mm. Another approach is the fabrication of a vertical FET. In the case of the vertical FET, an electron launcher for the ballistic transportation of electrons was also introduced. In the fabricated device, the width of the channel mesa was 15 nm. The observed drain current density at V-d = 0.75 V was 1.1 A/mm.

DOI： 10.1109/irmmw-THz.2011.6105026

Web of Science

researchmap

記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：JAPAN SOC APPLIED PHYSICS  

We proposed a vertical In GaAs channel metal-insulator-semiconductor field effect transistor (MISFET) with an ultranarrow mesa structure, an undoped channel, and a heterostructure launcher With the aim of obtaining a narrow mesa structure, we proposed the concept of performing selective undercut etching after dry etching We fabricated the proposed device with a 60-nm-long and 15-nm-wide channel mesa structure In the fabricated device, the observed drain current density was 1 1 A/mm Because the channel mesa width was 15 nm, the drain current density per unit area was 7 MA/cm(2) Thus, a high current density was achieved for an ultranarrow mesa structure (C) 2010 The Japan Society of Applied Physics

DOI： 10.1143/APEX.3.084101

Web of Science

researchmap

記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC  

High-performance metamorphic high-electron mobility transistors (MHEMTs) using an (InxGa1-xAs)(m)/(InAs)(n) superlattice structure as a channel layer have been fabricated successfully. These HEMTs with 80-nm gate length exhibited a high drain current density of 392 mA/mm and a transconductance of 991 mS/mm at 1.2-V drain bias. Compared with a regular InxGa1-xAs channel, the superlattice-channel HEMTs showed an outstanding performance due to the high electron mobility and better carrier confinement in the (InxGa1-xAs)(m)/(InAs)(n) channel layer. When biased at 1.2 V, the current gain cutoff frequency (f(T)) and the maximum oscillation frequency (f(max)) were extracted to be 304 and 162 GHz, respectively. As for noise performance, the device demonstrated a 0.75-dB minimum noise figure(NFmin) with an associated gain of 9.6 dB at 16 GHz. Such superior performance has made the devices with a superlattice channel well suitable for millimeter-wave applications.

DOI： 10.1109/LED.2010.2048995

Web of Science

researchmap

記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG  

We investigated collector current spreading in In GaAs single heterojunction bipolar transistors (SHBTs) having a collector thickness of 75 nm. SHBTs were fabricated with three different emitter widths - 200, 400, and 600 nm - and the highest cutoff frequency that was obtained was 468 GHz. The relationship between the current density at the highest cutoff frequency and the emitter width could not be used to estimate the current spreading because it was independent of the collector-base voltage. However, the relationship between the current density with the increase in the total collector-base capacitance and the emitter width indicates current spreading in the collector. The current spreading was estimated to be approximately 90 nm.

DOI： 10.1587/transele.E93.C.644

Web of Science

researchmap

記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC  

We demonstrate a 100-nm-gate-recessed n-GaN/AlGaN/GaN high-electron mobility transistor (HEMT) with low-noise properties at 30 GHz. The recessed GaN HEMT exhibits a low ohmic-contact resistance of 0.28 Omega . mm and a low gate leakage current of 0.9 mu A/mm when biased at V(GS) = -3 V and V(DS) = 10 V. At the same bias point, a minimum noise figure of 1.6 dB at 30 GHz and an associated gain of 5 dB were achieved. To the best of our knowledge, this is the best noise performance reported at 30 GHz for gate-recessed AlGaN/GaN HEMTs.

DOI： 10.1109/LED.2009.2037167

Web of Science

researchmap

記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：JAPAN SOC APPLIED PHYSICS  

The base transit times of an InP/GaInAs heterojunction bipolar transistor (HBT) with an ultrathin and heavily doped base are investigated by carrying out a Monte Carlo (MC) simulation. The acceleration of electrons due to a conduction-band discontinuity between the emitter and base is taken into consideration. Scattering caused by the spontaneous emission of hole plasmons considerably increases the base transit time even when the thickness of the base is 20 nm. Band-gap grading in the base effectively sweeps slow electrons into the collector, and the increase in the base transit time is partially suppressed. The MC simulation shows that when the band-gap grading is just twice the thermal energy, the transit time of the 20-nm-thick base decreases by 40%. (C) 2010 The Japan Society of Applied Physics

DOI： 10.1143/JJAP.49.024302

Web of Science

researchmap

記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：JAPAN SOC APPLIED PHYSICS  

We have demonstrated an InP/InGaAs composite-channel metal-oxide-semiconductor field-effect transistor with a selectively regrown n(+)-InGaAs source/drain formed by metal organic vapor-phase epitaxy. A 150-nm-long channel was fabricated using a dummy gate and by laterally buried regrowth in the channel undercut. The gate stack was formed after regrowth by replacing the dummy gate. The carrier density of the regrown layer was 4.9 x 10(19) cm(-3). The maximum drain current at a drain voltage V-d = 1 V and a gate voltage V-g = 3 V was 0.93 mA/mu m and the maximum transconductance was 0.53 mS/mu m at V-d = 0.65 V. (C) 2010 The Japan Society of Applied Physics

DOI： 10.1143/APEX.3.094201

Web of Science

researchmap

記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：JAPAN SOC APPLIED PHYSICS  

A 70 nm InAs channel quantum well field effect transistor (QWFET) fabricated by a narrowing source-drain (S/D) spacing technique was realized for future high-speed and logic applications. The S/D spacing was decreased from 3 to 0.65 mu m through a simple fabrication process, which is an ameliorative redeposition ohmic technique. The drain-source current density and transconductance of the device were increased from 391 to 517 mA/mm and from 946 to 1348 mS/mm after the scaling of the S/D spacing, respectively. In addition, the current gain cutoff frequency (f(T)) was also increased from 185 to 205 GHz. These results show that the easy method can effectively improve the III-V QWFET device performance for high-frequency and high-speed applications. (C) 2010 The Japan Society of Applied Physics

DOI： 10.1143/JJAP.49.010212

Web of Science

researchmap

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

We demonstrated a high-mobility InP 5 nm/InGaAs 12 nm composite channel MOSFET with MOVPE regrown n(+)-source/drain region for low series resistance and high source injection current. A gate dielectric was SiO2 and thickness was 20 nm. A carrier density of regrown InGaAs source/drain layer was over 4 x 10(19) cm(-3). In the measurement of submicron (= 150 nm) device, the drain current was 0.93 mA/mu m at V-g = 3 V, V-d = 1 V and the peak transconductance was 0.53 mS/mu m at V-d = 0.65 V, respectively. The channel length dependence of transconductance indicated the good relativity.

Web of Science

researchmap

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

The fabrication process of an 80 nm In0.7Ga0.3As MHEMT device with flip-chip packaging on Al2O3 substrate is presented. The flip-chip packaged device exhibited good dc characteristics with high I-DS = 425 mA/mm and high g(m) = 970 mS/mm at V-DS = 1.5 V. Besides, the RF performances revealed high gain of 10 dB at 50 GHz and low minimum noise figure (NFmin)below 2 dB at 60 GHz, showing the feasibility of flip-chip packaged In0.7Ga0.3As MHEMT device for low noise applications at W-band.

Web of Science

researchmap

記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：JAPAN SOCIETY APPLIED PHYSICS  

An InAs-channel high-electron-mobility transistor (HEMT) with an 80 nm gate length for ultralow-power low-noise amplifier (LNA) applications has been fabricated and characterized on a 2-in. InP substrate. Small-signal S-parameter measurements performed on the InAs-channel HEMT at a low drain-source voltage of 0.2 V exhibited an excellent f(T) of 120 GHz and an f(max) of 157 GHz. At an extremely low level of dc power consumption of 1.2 mW, the device demonstrated an associated gain of 9.7 dB with a noise figure of less than 0.8 dB at 12 GHz. Such a device also demonstrated a higher associated gain and a lower noise figure than other InGaAs-channel HEMTs at extremely low dc power consumption. These results indicate the outstanding potential of InAs-channel HEMT technology for ultralow-power space-based radar, mobile millimeter-wave communications and handheld imager applications. (c) 2009 The Japan Society of Applied Physics

DOI： 10.1143/JJAP.48.04C094

Web of Science

researchmap

記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：JAPAN SOCIETY APPLIED PHYSICS  

In this paper, the device characteristics of an InP hot electron transistor with improved gate insulation are reported. The breakdown voltage of the gate was increased from 0.5 to 2.5 V by increasing the distance between the gate and the electron transport region. Consequently, the appropriate gate bias at which a clear transconductance peak could be observed was applied. The transconductance was increased from 55 to 130 mS/mm. When the output conductance was reduced, the open circuit voltage gain was about 10. (C) 2009 The Japan Society of Applied Physics DOI: 10.1143/APEX.2.034501

DOI： 10.1143/APEX.2.034501

Web of Science

researchmap

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

An InP/InGaAs composite channel MOSFET with InGaAs source is fabricated, this InGaAs source is selectively regrown by metalorganic vapor phase epitaxy. The maximum drain current of MOSFET (at V(D) = V(G) = 3 V) is 360 mA/mm at room temperature with the Si-doped channel, 20-nm-thick SiO(2) gate insulator and 2 mu m channel length. However, the drain current of regrown MOSFET is smaller than MOSFET without regrowth because of high access resistance which was caused by low doping concentration in regrown layer.

DOI： 10.1109/ICIPRM.2009.5012504

Web of Science

researchmap

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

High performance MHEMTs using (InxGa1-xAs)(m)/(InAs)(n) superlattice structure as a channel layer have been fabricated successfully. These HEMTs with 80 nm gate length exhibit high drain current density of 392 mA/mm at drain bias 1.0 V and transconductance of 991 mS/mm at drain bias 1.2 V. Comparison with regular InxGa1-xAs channel, the superlattice channel HEMTs show an outstanding performance because of high electron mobility, and better carrier confinement in the (InxGa1-xAs)(m)/(InAs)(n) channel layer. The current gain cutoff frequency (f(T)) and maximum oscillation frequency (f(max)) were extracted to be 304 GHz and 162 GHz, respectively. The device demonstrated a 0.75 dB noise figure with an associated gain 9.6 dB at 16 GHz. The excellent device performance shows that the superlattice channel can be practically used for high-frequency and millimeter-wave application.

Web of Science

researchmap

記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：ELECTROCHEMICAL SOC INC  

N-type metal-oxide-semiconductor high electron mobility transistor (MOS-HEMT) devices with an InAs-channel using atomiclayer-deposited (ALD) Al2O3 as a gate dielectric have been fabricated and characterized. The device performances of a set of scaled transistors with and without high-k gate dielectric Al2O3 have been compared to determine the optimum device structure for low power and high speed applications. The measurement results revealed that the high performance InAs-channel MOS-HEMTs with the ALD Al2O3 gate dielectric can be achieved if the structure is designed properly. (C) 2009 The Electrochemical Society. [DOI: 10.1149/1.3241014] All rights reserved.

DOI： 10.1149/1.3241014

Web of Science

researchmap

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

A 40-nm T-gate high-electron-mobility-transistor with InAs/In0.7Ga0.3As composite-channel has been fabricated. The device exhibits a transconductance (g.) of 2200 mS/mm, a cutoff frequency f(T) of 506 GHz and a minimum noise figure of 1.21 dB at a frequency of 58 GHz. These performances make the device well-suited for millimeter-wave or sub-millimeter-wave applications.

DOI： 10.1109/ICIPRM.2009.5012458

Web of Science

researchmap

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：ELECTROCHEMICAL SOC INC  

The performance of n-type metal-oxide-semiconductor HEMTs with an InAs-channel using atomic-layer-deposited Al2O3 as gate dielectric has been fabricated and evaluated. The device performances of a set of scaled transistors with different gate dielectric thicknesses of 3, 5 and 7 nm have been investigated to determine whether the architecture of Al2O3 dielectric on InAs-channel HEMT can demonstrate good properties at low bias conditions for high-speed, high performance CMOS applications. The results indicate that the high-performance InAs-channel MOS-HEMTs with an ALD Al2O3 gate dielectric are promising candidates for advanced post-Si CMOS applications.

DOI： 10.1149/1.3206609

Web of Science

researchmap

記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：JAPAN SOCIETY APPLIED PHYSICS  

To investigate wave propagation with an extended wavefront of a ballistic hot electron in a semiconductor, we estimate the possibility of observing electron wave diffraction. Such diffraction is caused by it phase shifter and observed using a scanning probe. By quantitative comparison between theoretically simulated signals and experimental noises, the structure of the device is optimized. The pattern is expected to have a peak characteristic of such diffraction. The height of the peak is 2 times higher than that of the noise in the current measurement and the spatial fluctuation caused by nonuniformity.Thus, it is possible to increase the probability of success and tolerance in the observation experiment by lowering the noise level ill the current measurement. [DOI: 10.1143/JJAP.47.8652]

DOI： 10.1143/JJAP.47.8652

Web of Science

researchmap

記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：JAPAN SOCIETY APPLIED PHYSICS  

An InAs/In(0.3)As composite channel high-electron-mobility transistor (HEMT) fabricated using the gate sinking technique was realized for ultralow-power-consumption low-noise application. The device has a very high transconductance of 100 mS/mm at at drain voltage of 0.5 V. The saturated drain-Source current of the device is 1066 mA/mm. A current grin cutoff frequency (f(T)) of 113 GHz and a maximum oscillation frequency (f(max)) of 110GHz were achieved at only drain bias volume V(ds) = 0.1V. The 0.08 x 40 mu m(2) device demonstrated a minimum noise figure of 0.82 dB and a 14 dB associated gain at 17GHz with 1.14mW DC power consumption.

DOI： 10.1143/JJAP.47.7119

Web of Science

researchmap

記述言語：中国語   掲載種別：研究論文（学術雑誌）   出版者・発行元：CHINESE PHYSICAL SOC  

One-dimensional periodic nanocrystalline silicon ( nc-Si) arrays were fabricated by laser interference crystallization combined with one- dimensional phase shifting grating mask ( PSGM The laser energy density irradiated on the surface of samples with different thicknesses of a-Si:H can be modulated by the PSGM with periodicity of 400 nm. Raman spectra confirmed the crystallization of the irradiated stripe-patterned area of the samples. The transmission electron microscopic and atomic force microscopic images demonstrate that the periodicity of one-dimensional nc-Si arrays is the same as that of the PSGM. And by controlling the laser energy density, a stripe width of 30 nm in each period was obtained as the thickness of a-Si: H decreased from 10 to 4 nm. The high resolution transmission electron microscope images show the clear crystalline lattice of nc-Si within the stripe patterns.

Web of Science

researchmap

記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC  

Eighty-nanometer-gate In0.7Ga0.3As/InAs/ In0.7Ga0.3As composite-channel high-electron mobility transistors (HEMTs), which are fabricated using platinum buried gate as the Schottky contact metal, were evaluated for RF and logic application. After gate sinking at 250 degrees C for 3 min, the device exhibited a high g(m) value of 1590 mS/mm at V-d = 0.5 V, the current-gain cutoff frequency f(T) was increased from 390 to 494 GHz, and the gate-delay time was decreased from 0.83 to 0.78 ps at supply voltage of 0.6 V. This is the highest f(T) achieved for 80-nm-gate-length HEMT devices. These superior performances are attributed to the reduction of distance between gate and channel and the reduction of parasitic gate capacitances during the gate-sinking process. Moreover, such superior performances were achieved through a very simple and straightforward fabrication process with optimal epistructure of the device.

DOI： 10.1109/LED.2008.917933

Web of Science

researchmap

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

The high-speed characteristics and off characteristics of a novel transistor with a hot-electron launcher and a transit layer of an intrinsic semiconductor whose current is controlled by an insulated gate are evaluated by Monte Carlo simulation. The dependences of the cutoff frequency fT on the gate insulator thickness, collector bias voltage, gate length and transit layer length are clarified. For the optimum stracture consisting of InP/InGaAs/W as the emitter/transit layer/collector, Au as the gate and bisbenzocyclobutene (BCB) as the gate insulator and the surrounding material, fT is 1.4 THz at the collector current density of 1.6 MA/cm2. The collector current can be controlled over four orders of magnitude by a gate voltage swing of 0.6 V. © 2008 WILEY-VCH Verlag GmbH &amp
Co. KGaA.

DOI： 10.1002/pssc.200776510

Scopus

researchmap

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

80-nm high electron mobility transistors (HEMTs) with different Indium content in InxGa1-xAs channel from 52%, 70% to 100% have been fabricated. Device performances degradation were observed on the DC measurement and RF characteristics caused by impact ionization at different drain bias, >0.8V (InAs/In0.7Ga0.3As), > 1V (In0.7Ga0.3As) and > 1.5V (In0.52Ga0.48As), respectively. The impact ionization phenomenon should be avoided for high speed, low power application because it limits the highest drain bias of the device which in turn limits the drift velocity under specific applied electric field.

Web of Science

researchmap

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

The emitter width of the hot electron transistor controlled by an insulated gate was reduced to 70 nm by an improved fabrication process. In a previous study, the observed output conductance was twofold higher than transconductance. In this study, the output conductance was reduced from 115 mS/mm to 20 mS/mm by the improved fabrication process and a clear current modulation was also confirmed.

Web of Science

researchmap

記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：WILEY-BLACKWELL PUBLISHING, INC  

Morphological characters of adults and immature stages of Pyloetis mimosae (Stainton 1859) are redescribed mainly on the basis of material collected from seed pods of Leucaena leucocephala (Lem.) in the Ryukyus, Japan. Although the systematic position of this species in the family Tineidae has been problematic, we conclude that it should be placed in the subfamily Erechthiinae based on morphological characters. Pyloetis mimosae is newly recorded from Japan.

DOI： 10.1111/j.1479-8298.2007.00235.x

Web of Science

researchmap

記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC  

An 80-nm InP high electron mobility transistor (HEMT) with InAs channel and InGaAs subchannels has been fabricated. The high current gain cutoff frequency (f(t)) of 310 GHz and the maximum oscillation frequency (f(max)) of 330 GHz were obtained at V-DS = 0.7 V due to the high electron mobility in the InAs channel. Performance degradation was observed on the cutoff frequency (f(t)) and the corresponding gate delay time caused by impact ionization due to a low energy bandgap in the InAs channel. DC and RF characterizations on the device have been performed to determine the proper bias conditions in avoidance of performance degradations due to the impact ionization. With the design of InGaAs/InAs/InGaAs composite channel, the impact ionization was not observed until the drain bias reached 0.7 V, and at this bias, the device demonstrated very low gate delay time of 0.63 ps. The high performance of the InAs/InGaAs HEMTs demonstrated in this letter shows great potential for high-speed and very low-power logic applications.

DOI： 10.1109/LED.2007.906083

Web of Science

researchmap

記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：INST PURE APPLIED PHYSICS  

Elimination of the base layer in conventional hot electron transistor has possibility to minimize the scattering in the propagation. In previous study, we fabricated InP/InGaAs hot electron transistors without a doped layer in the propagation region by fabricating a 25-nm-wide emitter and Schottky gate electrodes located at both sides of an emitter mesa. However, there were some problems in fabricated device. To solve these observed problems, we proposed and fabricated a new structure with hot electrons propagating only in the intrinsic semiconductor. An insulated gate was introduced in hot electron transistors, in which hot electrons are propagated only in the intrinsic region after extraction from a heterostructure launcher. Clear collector current modulation by the insulated gate and a current density of 160kA/cm(2) were confirmed.

DOI： 10.1143/JJAP.46.L617

Web of Science

researchmap

記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：INST PURE APPLIED PHYSICS  

A 70nm In0.52Al0.48As/In0.6Ga0.4As power metamorphic high electron mobility transistor (MHEMT) with a double delta-doping structure was fabricated and evaluated. The device has a high transconductance of 827mS/mm. The saturated drain-source current of the device is 890mA/mm. A current gain cutoff frequency (f(T)) of 200GHz and a maximum oscillation frequency (f(max)) of 300GHz were achieved owing to the nanometer gate length and high indium content in the channel. When measured at 32 GHz, the 0.07x160 mu m(2) device demonstrates a maximum output power of 14.5dBm (176mW/mm) and a P I dB of 11.1dBm (80mW/mm) with a 9.5dB power gain. The excellent DC and RF performance of the 70mn MHEMT are comparable to those of InP-based HEMTs and show the great potential for Ka-band power applications.

DOI： 10.1143/JJAP.46.3385

Web of Science

researchmap

記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：INST PURE APPLIED PHYSICS  

A current density of 90 kA/cm(2) was observed in hot-electron transistors controlled by gate bias. In these transistors, the base layer of a conventional hot-electron transistor was eliminated to minimize the scattering. Electron emission from the emitter was controlled by positively biased Schottky gate electrodes located on both sides of the emitter mesa. Using electron-beam lithography, emitters with an effective width of 25 nm and surrounded by gates were fabricated to obtain saturated I-V characteristics. In a previous study, the observed current density for current amplification was approximately 10 A/cm(2) at 30 K, although a resonant tunneling diode using the same epitaxial structure showed a 1 kA/cm(2) peak current density. Using a 1.75-nm-thick. AlAs barrier, the oxidation of the emitter barrier was prevented and a collector-current density of 90 kA/cm(2) and a clear negative differential resistance were observed at 30 K. A current gain of 7 and an open-circuit voltage gain of 10 were also confirmed when the collector-current density was 10 kA/cm(2).

DOI： 10.1143/JJAP.46.L202

Web of Science

researchmap

記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：ELSEVIER SCIENCE BV  

A new heterojunction bipolar transistor (HBT) structure with buried SiO2 wires is proposed. SiO2 wires were buried in the InP layer by metalorganic vapor-phase epitaxy (MOVPE). The insertion of SiO2 wires under the base electrodes reduces collector capacitance because of a small dielectric constant. Two SiO2 wires of 200 nm width and 60 nm height on the InP substrate were buried in an InP DHBT structure with a flat heterointerface when the buried growth temperature was 580 degrees C and the direction of the wire was < 010 >. (c) 2006 Elsevier B.V. All rights reserved.

DOI： 10.1016/j.jcrysgro.2006.10.215

Web of Science

researchmap

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

We investigated the influence of emitter doping level on the performance for high-speed InP HBTs with high reliability. The HBTs show high current gain and excellent reliability characteristics under stress current density of 5 mA/mu m(2).

DOI： 10.1109/ICIPRM.2007.381219

Web of Science

researchmap

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

An 80-nm InP HEMT with InAs channel and InGaAs sub-channels has been fabricated. The high current gain cutoff frequency (ft) of 350 GHz and maximum oscillation frequency (fmax) of 360 GRz were obtained at VDS = 0.7 V due to the high electron mobility in the InAs channel. DC and RF characterizations on the device have been performed and the on-sate breakdown voltage of the device was measured to be 1.75V. A 2-stage MMIC gain block was designed using such device. A simulated gain of better than 12 dB from 54 GHz to 71 GRz with only 14mW DC power consumption was achieved. Such high performance HEMTs demonstrated in this study shows great potential for very low power millimeter wave applications.

Web of Science

researchmap

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

A hot electron transistor controlled using an insulated gate was fabricated, and collector current modulation by the gate bias was observed at room temperature. In the fabricated devices, a current density of 160 kA/cm(2), clear modulation of the collector current, and the insulation properties of the gate were confirmed. The problems observed in our former hot electron transistors with Schottky gate electrodes, such as a low current density and a gate leakage current at room temperature, were solved.

DOI： 10.1109/ICIPRM.2007.381140

Web of Science

researchmap

記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：INST PURE APPLIED PHYSICS  

We theoretically examine the charging time of a double-layer emitter in heterojunction bipolar transistors (HBTs) on the basis of transmission formalism. It is indicated that the charging time is shorter in the double-layer emitter with an n(++)/n(+) combination than in the single-layer n(+) emitter. The nonparabolic band structure is responsible for this finding. Thus, the inclusion of a second layer in the emitter is essential for high-speed operation. The theory also explains the experimentally reported, charging times in state-of-the-art high-speed HBTs.

DOI： 10.1143/JJAP.45.L935

Web of Science

researchmap

記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG  

The feasibility of a new transistor structure was demonstrated through an experimental observation of current gain and voltage gain. The proposed transistor structure is a hot electron transistor without a base layer to minimize scattering. Electron emission from the emitter is controlled using positively biased Schottky gate electrodes located on both sides of the emitter mesa. Monte Carlo simulation shows an estimated delay time of 0.17 ps and low gate leakage current with open-circuit voltage gain over unity. To confirm the basic operation, the device with a 25 nm wide emitter was fabricated. To obtain saturated current-voltage characteristics, the emitter was surrounded by gates and parasitic regions were eliminated by electron beam lithography. The observed open-circuit voltage gain was 25. To obtain a low leakage current, an electron energy smaller than the F-L separation was necessary to maintain the ballistic nature of the electron. When the gate-emitter voltage was 0.8 V, the gate leakage current was only 4% of the collector current. Thus voltage amplification and current amplification were confirmed simultaneously.

DOI： 10.1093/ietele/e89-c.7.972

Web of Science

researchmap

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IOP PUBLISHING LTD  

Ultrafast operation of a transistor using ballistic electron concepts and its fabrication feasibility are shown by Monte Carlo simulation and experiment, respectively. The transistor consists of InP/GaInAs heterojunction launcher of 20 nm-width and a subsequent propagation layer of 80 nm-length intrinsic GaInAs. Schottky metal gates attached on both sides of the propagation layer are biased in the forward direction so that potential barriers at Schottky junctions are flattened and hot electrons are extracted from the launcher. Hot electron velocity is as fast as 7-8x10(7) cm/s through the whole propagation layer. From stationary and step-response simulations, the cutoff frequency is higher than one THz. The emitter charging and the transit times are discussed to confirm the simulation. Finally, fabrication and operation of the transistor with 25 nm-width emitter using GaInAs/InP organo-metallic vapor phase epitaxy, electron-beam lithography, ultrafine process are demonstrated.

DOI： 10.1088/1742-6596/38/1/050

Web of Science

researchmap

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

A 70-nm In0.52Al0.48As/In0.6Ga0.4As power MHEMT with double delta-doping was fabricated and evaluated. The device has a high transconductance of 827 mS/mm. The saturated drain-source current of the device is 890 mA/mm. A current gain cutoff frequency (f(T)) of 200 GHz and a maximum oscillation frequency of 300 GHz were achieved due to the nanometer gate length and the high Indium content in the channel. When measured at 32 GHz, the 4 x 40 mu m device demonstrates a maximum output power of 14.5 dBm with P1dB of 11.1 dBm and the power gain is 9.5 dB. The excellent DC and RF performance of the 70-nm MHEMT shows a great potential for Ka-band power applications.

DOI： 10.1109/SMELEC.2006.381095

Web of Science

researchmap

記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：JAPAN SOC APPLIED PHYSICS  

This is a detailed description of the first definite observation of the double-slit interference of a hot electron in a solid. The observation has been achieved by fabricating a double-slit with a 12 nm opening and a 25 nm center-to-center distance and a detection electrode with a 40 nm width. Various inspections are made theoretically to confirm the double-slit diffraction/interference. This achievement will open the door to the creation of solid-state devices with new functions based on the wave nature of electrons.

DOI： 10.1143/JJAP.44.2936

Web of Science

researchmap

記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：INST PURE APPLIED PHYSICS  

The impact of latent image quality on line edge roughness (LER) in 100, 50 and 2 keV electron beam lithography was investigated. There is a minimum LER of about 2 nm achievable with current resist systems though the LER increases as a result of the amplification of bandwidth of the threshold level by the slope of the quasi-beam profile (QBP), which is a latent image profile in which the line spread function is assumed to be Gaussian. A plausible cause of the minimum LER is the domain size of resist materials such as polymer/monomer aggregation. Analysis of the LER dependence on the 1/slope revealed the origins of the bandwidth of the threshold level: variation of the latent image profile in terms of image blur and intensity. Independent of the electron energies and resists used, the resolution of an isolated line was proportional to the blur of the QBP with an intrinsic resolution of the resists about 5 nm which has been ignored for photolithography.

DOI： 10.1143/JJAP.43.3739

Web of Science

researchmap

記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：INST PURE APPLIED PHYSICS  

The modulation of drain current by gate voltage in a self-assembled monolayer (SAM) of benzene-1,4-dithiol was confirmed on the basis of the transistor structure. A device was fabricated by the shadow mask technique with an air-bridge structure. By electron beam lithography, the top area of the Au/SAM/Au junction was fabricated to be 370 nm by 230 nm. The measured current-voltage characteristics showed an exponential increase in drain current when drain voltage was increased and a decrease in drain current when gate bias was increased. Because the modulated drain current was greater than the gate leakage current, modulation by the gate bias was confirmed. However, no bonding was expected in the upper SAM/Au junction because the magnitude of the drain current was less than 100 pA.

DOI： 10.1143/JJAP.43.L337

Web of Science

researchmap

記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：INST PURE APPLIED PHYSICS  

We proposed and fabricated a hot electron transistor in which an electron propagates only through an intrinsic semiconductor. In this transistor, an emitter mesa was fabricated between gate electrodes to reduce the gate leakage current from the emitter to the gate. To suppress the current leakage from the emitter and the gate pads, free-standing tungsten wires were also fabricated. The measured I-V characteristics at 20 K showed effective control of collector current by gate bias. When the device was operated, it was confirmed that the gate-leakage current from the emitter to the gate was smaller than the collector current. The calculated transconductance g(m) was approximately 10 mS/mm.

DOI： 10.1143/JJAP.43.L183

Web of Science

researchmap

記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：TECHNICAL ASSOC PHOTOPOLYMERS,JAPAN  

An ultra-thin resist process is indispensable for low-energy electron-beam proximity projection lithography (LEEPL) because it uses 2-kV-accelerated electrons with small penetration depth. 70-nm-thick chemically-amplified resists for a tri-layer process were developed with the consideration of the interaction of a polymer with a spin-on-glass material, showing the resolution of 140-nm-pitch contact holes. Application of the tri-layer process developed for LEEPL to making via holes in a 90-nm-node back-end-of-line process proved that the ultra-thin resist was lithographically useful in terms of resolution and etching tolerance. Exploring the resolution performance of electron beam lithography showed that line edge roughness and resolution limit of resist patterns was in linear relation with blur of latent image profile. Reducing the resist thickness is effective in enhancing the resolution of LEEPL because 47 % of the blur is attributed to electron scattering. A Monte Carlo simulation shows that the blur caused by the electron scattering decreases 41 %. to 20 nm from 34 nm, by reducing the resist thickness to 30 nm from 70 nm.

DOI： 10.2494/photopolymer.17.581

Web of Science

researchmap

記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：INST PURE APPLIED PHYSICS  

GaInAs/InP heterojunction bipolar transistors (HBTs) with a single 0.1-mum-wide tungsten wire were fabricated. The tungsten wire was buried in an undoped InP collector layer and functioned as a collector electrode. In a previous process of fabricating HBTs with buried wires, we could not achieve a device operation with only a single wire. One of the possible reasons for this failure was the insufficient growth of the buried wire, because this wire requires a long growth time. The nonuniformity of facet formation in a previous wet etching process used to fabricate an InP emitter also contributed to the failure. By increasing the growth time of the buried wire and changing the wet etching solution used to enable uniform fabrication of emitter mesas, we observed a transistor operation with a current gain of 20 in the fabricated HBT. The emitter area of the device was 0.1 x 0.5 mum(2).

DOI： 10.1143/JJAP.42.L1501

Web of Science

researchmap

記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：INST PURE APPLIED PHYSICS  

To apply the ballistic nature of hot electrons, an InP hot electron transistor with a buried metal (BM-HET) is reported. In this device, carriers are extracted from the emitter by an attractive potential originating from an embedded metal grating, and they propagate through intrinsic semiconductor material only. A simple estimation shows a high cutoff frequency and low output conductance. The estimated highest cutoff frequency is approximately 1 THz. Fabricated devices show that the collector current increased with the gate bias. After extraction of the leakage cur-rent, a clear saturation of the collector current in common-emitter characteristics was confirmed and the possibility of BM-HET as a candidate for high-speed electron devices was demonstrated.

DOI： 10.1143/JJAP.42.7221

Web of Science

researchmap

記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：INST PURE APPLIED PHYSICS  

We investigated the effects of low-oxygen-content metalorganic precursors on oxygen impurities and Hall mobility. The oxygen concentration in the AlInAs layer was less than 2 x 10(17) cm(-3) under all growth conditions. We confirmed the high mobility of the AlInAs/InP high electron mobility transistors (HEMT) structure with the AlInAs buffer layer (5,500 cm(2)/V.s at 300K, and 110,000 cm(2)/V.s at 77K). For the AlInAs/GalnAs HEMT Structure with the same buffer layer, weobtamed the high mobility (12,000cm(2) /V.s at 300 K, and 92,000 cm(2) /V.s at 77 K).

DOI： 10.1143/JJAP.42.L993

Web of Science

researchmap

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：Institute of Electrical and Electronics Engineers Inc.  

In this paper, LER of resist patterns is investigated using various EB lithography. LER strongly depended on latent image quality.

DOI： 10.1109/IMNC.2003.1268599

Scopus

researchmap

記述言語：英語   掲載種別：研究論文（学術雑誌）  

InP/GaInAs double heterojunction bipolar transistors (DHBTs) with a 0.1-μm-wide emitter along the 〈010〉 direction were fabricated by the self-aligned process. A DC current gain of β = 51 as a maximum value was observed. Current amplification was confirmed even when an emitter current was 1 μA. A 0.1-μm-wide emitter was formed by the combination of CH4/H2-reactive ion etching and two kinds of wet etching based on HCl. To our knowledge, this HBT has the narrowest emitter that has ever been reported.

DOI： 10.1143/JJAP.41.L121

Web of Science

researchmap

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：Institute of Electrical and Electronics Engineers Inc.  

When carriers are propagated only through intrinsic semiconductor, high-speed transistors can be realized due to reduction of scattering. We proposed hot electron transistor with a buried metallic gate (BM-HET) using double barrier as an emitter. In this device, gate metal buried in intrinsic semiconductor works as Schottky barrier to make attractive potential. Potential of the gate metal modulates the barrier height, resulting in modulation of the emitter current. In this report, we present freestanding wires fabricated by etching after buried growth to reduce a leakage current of BM-HET.

DOI： 10.1109/IMNC.2002.1178534

Scopus

researchmap

A buried metal heterojunction bipolar transistor with a 0.5-μm-wide emitter was fabricated by electron-beam lithography, in which three tungsten wires of 100 nm width, 100 nm height and 200 nm period were buried in the InP collector layer. For the device with an emitter area of 0.5 × 2.5 μm2, total base-collector capacitance was reduced to about 30% of that calculated from the physical dimensions of a conventional heterojunction bipolar transistor, and a current gain cutoff frequency of 86 GHz and a maximum oscillation frequency higher than 135 GHz were obtained.

DOI： 10.1143/jjap.40.L735

researchmap

記述言語：英語   出版者・発行元：公益社団法人 応用物理学会  

We report a novel approach for improving the performance of InP-based heterojunction bipolar transistors (HBTs). A buried-metal heterojunction bipolar transistor (BM-HBT), in which tungsten stripes of the same area as the emitter metal were buried in an i-InP collector layer, was fabricated for the first time. The aim in fabricating this structure is to realize a reduction in the total base-collector capacitance (CBCT). In the measurement of microwave S-parameters, CBCT of 10.3 fF was evaluated. The effective base-collector junction area of the BM-HBT was estimated to be 22% that of conventional-HBT considering the difference in collector thickness.

DOI： 10.1143/jjap.39.L503

researchmap

記述言語：英語   出版者・発行元：公益社団法人 応用物理学会  

We studied the peak width of current vs voltage (I-V) characteristics of triple-barrier resonant tunneling diodes (TBRTDs) experimentally and theoretically. A GaInAs/InP TBRTD was fabricated by organo metallic vapor phase epitaxy (OMVPE). A theory of I-V characteristics of TBRTDs was developed by taking the structural inhomogeneity into account to explain the experimental peak width. The fluctuation of the well width in a TBRTD grown by OMVPE was estimated as two atomic layers. ? 2000 The Japan Society of Applied Physics.

DOI： 10.1143/JJAP.39.3314

researchmap

記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：Elsevier Science B.V.  

We studied the buried growth of a GaAs layer over a tungsten stripe using organometallic vapor-phase epitaxy. Triethylgallium (TEG) and trimethylgallium (TMG) were used as group III sources. For growth without polycrystal-like deposition on tungsten surface, the required growth temperature using TMG was lower than that using TEG. For 2-μm-thick growth over a 1-μm-wide tungsten stripe, the flatness of the surface grown using TMG was better than that using TEG. Therefore, the migration length of TMG on tungsten and GaAs must be longer than that of TEG. For a heterojunction bipolar transistor with a tungsten stripe as the collector electrode, a 70-nm-wide tungsten stripe was buried under a 0.77-μm-thick layer of GaAs with a flat surface using TMG. A current gain of 4 was measured although the active region was grown over tungsten stripe.

DOI： 10.1016/S0022-0248(00)00688-6

Scopus

researchmap

記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：Elsevier Science Publishers B.V.  

To conduct Young's double slit experiment using a semiconductor, fabrication techniques for 80 to 100-nm-period fine electrodes with 30 to 40-nm thickness are reported. To obtain a resist pattern suitable for the lift-process, we used a double-layer resist with ZEP-520 and PMMA. The mixing of C60 into both layers and rinsing by perfluorohexane (PFH) prevented pattern collapse. As a result, a Au/Cr pattern with a 80-nm period over 30-nm steps was obtained. Using the developed process, we fabricated a device for observing the interference pattern. Unfortunately, the collector current from each electrode was not uniform. Moreover, the current showed anomalous behavior. The current occasionally converged in two different points and sudden jumps from the lower converged point to the upper converged point were also observed in time-dependent measurements. Such anomalous behavior might be explained in terms of a change in the ionization of an impurity near the metal-semiconductor interface.

DOI： 10.1016/S0169-4332(00)00113-6

Scopus

researchmap

記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：Elsevier Sci B.V.  

Toward nano-metal buried structure in InP, we studied the fabrication process of nano-tungsten wire and the InP buried growth of tungsten stripes. A tungsten wire with a 20 nm width was fabricated by the proposed metal-stencil liftoff, in which gold/chromium and SiO2 replace resist to prevent thermal deformation in a conventional liftoff process. The buried growth of tungsten stripes with 1 μm widths and 2 μn pitch by organometallic vapor phase epitaxy (OMVPE) was studied. Tungsten stripes were buried under the flat InP layer of 1.1 μm thickness, and the ratio of grown InP thickness to buried tungsten width was about 1.

DOI： 10.1016/S1386-9477(00)00084-9

Scopus

researchmap

記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：Elsevier Science Ltd  

GaInAs/AlAs/InP resonant tunnelling diodes with three different barrier thicknesses (3.5, 5.3, and 7 nm) were fabricated by metalorganic vapor phase epitaxy and the barrier thickness dependence of the peak current density was measured. The range of peak current was from 100 to 0.1 A/cm2. In the measurement of peak current density distribution, the deviations of peak current density became larger when the barrier became thicker. This fluctuation of peak current density can be explained by the thickness fluctuation of the barrier in the wafer's millimeter range.

DOI： 10.1016/S0038-1101(99)00079-9

Scopus

researchmap

記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：Elsevier Ltd  

Sub-micron hot electron transistors (HETs) fabricated by electron beam lithography (EBL) and the size dependence of current gain in HETs are described. The key process to fabricate small HETs is the small opening of the polyimide layer by dry-etching with bi-layer (PMMA/LS-SOG) resist. In this etching, removal of scum by slight wet etching and release of stress are essential to make a small opening (160 × 350 nm2). The smallest emitter size of fabricated HET was (0.3 × 1.5 + 0.6 × 1) μm2 and a Gummel plot with a current gain of 4 was observed. This gain was almost the same as that of large HETs (20 × 50 μm2). In comparison with previously fabricated small HETs with SiO2 layer, small HETs with polyimide layer show higher current gain. © 1998 Elsevier Science Ltd. All rights reserved.

DOI： 10.1016/S0038-1101(98)00051-3

Scopus

researchmap

A complete method for parameter extraction from small-signal measurements of InP-based heterojunction bipolar transistors (HBT's) is presented. Employing analytically derived equations, a numerical solution is sought for the best fit between the model and the measured data. Through parasitics extraction and an optimization process, a realistic model for a self-aligned HBT technology is obtained. The results of the generated sparameters from the model for a 2 x 10 /urn2 emitter area device are presented over a frequency range of 250 MHz-36 GHz with excellent agreement to the measured data. ? 1997 IEEE.

DOI： 10.1109/22.552030

researchmap

記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：AMER INST PHYSICS  

The influence of electron energy width in the hot electron double-slit experiment is investigated quantitatively. The required condition on the Fermi level in the emitter and the slit-spacing is derived for the experiment. In order to achieve a coherent electron source, a single-barrier graded emitter structure is discussed and its characteristics are considered. For application to the hot electron double-slit experiment, the graded emitter diode is fabricated and the current-voltage relation is measured in a supplementary experiment. (C) 1997 American Institute of Physics.

DOI： 10.1063/1.365749

Web of Science

researchmap

記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：JAPAN J APPLIED PHYSICS  

As an Al-free material system, the GaInAs/GaInP heterostructure has a large conduction-band discontinuity. We,report the fabrication of GaInAs/GaInP resonant tunneling diodes which exhibit current density-voltage characteristics with a peak-to-valley current ratio of 7.8 at 4.2K. To our knowledge, this is the highest value obtained for this material system.

DOI： 10.1143/JJAP.36.5079

Web of Science

researchmap

記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：AMER INST PHYSICS  

We report a double-slit experiment of hot electrons in a semiconductor under a magnetic field, The pitch of the double slit buried in the semiconductor is 40 nm and the electron energy is of the order of 100 meV. By applying a magnetic field, the change in current that passes through the slits is observed at the segmented collector. The measured current shows a clear minimum around B=0 T, with this behavior agreeing with a theoretical calculation based on double-slit interference. Quantitative estimation is consistent with this order of current variation. We think that these results show evidence of the observation of hot electron interference by a double slit in a semiconductor (C) 1997 American Institute of Physics.

DOI： 10.1063/1.119318

Web of Science

researchmap

記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：Elsevier  

The topography of InP and Ga0.47In0.53As surfaces grown by organometallic vapor phase epitaxy (OMVPE) was investigated using atomic force microscopy (AFM). Monolayer steps with atomically flat terraces, several hundred nanometers width, were formed for both InP and GaInAs. The boundary growth condition between step flow mode and 2D-nucleation mode was studied for InP and GaInAs, respectively. Applying step flow mode to the growth of GalnAs/InP resonant tunneling diodes, a remarkable reduction of the energy level width fom 51 to 18 meV was observed.

DOI： 10.1016/S0022-0248(97)00103-6

Scopus

researchmap

記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC  

The total base-collector capacitance (C-BC) of GaInAs/InP double heterojunction bipolar transistors (DHBT's) has been reduced by the etching away of the semiconductor layers below the extrinsic base region, resulting in an undercut structure, The reduction was further enhanced by using a novel composite subcollector structure. A 54% reduction of total CBC and improvement of microwave characteristics (an increase of 20% in f(T) and 38% in f(max)) were observed as a result of the undercut process.

DOI： 10.1109/55.485179

Web of Science

researchmap

記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：IEE-INST ELEC ENG  

A novel approach for realising a double heterojunction bipolar transistor (DHBT) with a low base resistance, which incorporates a thick extrinsic bass and a regrown emitter, is proposed and demonstrated. A combination of selective MOVPE regrowth and selective wet chemical etching resulted in a new self-aligned DHBT structure. Fabricated microwave transistors exhibited good DC and microwave characteristics.

DOI： 10.1049/el:19951020

Web of Science

researchmap

記述言語：英語   掲載種別：研究論文（学術雑誌）  

An ultrafine fabrication technique for hot electron interference/diffraction devices was developed. The alignment of two nanostructures by e-beam direct writing before and after crystal growth was reported for the first time. The aligned structure consists of 70 nm pitch grating GalnAs/InP buried structure and 70 nm pitch stripe electrode of Cr/Au. © 1995 The Japan Society of Applied Physics.

DOI： 10.1143/JJAP.34.4436

Scopus

researchmap

記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：ELSEVIER SCIENCE BV  

Buried growth and selective growth techniques by organometallic vapor phase epitaxy (OMVPE) of GaInAs have been developed for the realization of electron diffraction devices. We have obtained a 50 mm pitch buried GaInAs/InP corrugation, which is the world's smallest, using TMI.

DOI： 10.1016/0022-0248(94)91129-0

Web of Science

researchmap

記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：JAPAN J APPLIED PHYSICS  

We proposed a device for observing hot electron interference by a double slit. For this purpose we had refined and improved the fabrication techniques, especially electron beam lithography; the alignment of electron beam lithography before and after crystal growth with accuracy of 100nm was reported for the first time. We could form detection electrodes of fine pitch on a narrow mesa structure. The formation of a 50-nm-pitch InP buried structure was also reported.

DOI： 10.1143/JJAP.33.925

Web of Science

researchmap

記述言語：英語   掲載種別：研究論文（学術雑誌）  

The highest current gain (more than 100 at 77 K) is reported in GalnAs/lnP hot electron transistor (HET) grown by organo-metallic vapour-phase epitaxy. This result shows the promise of the GalnAs/lnP material system for ballistic electron devices. A sudden increase of the collector current in the common-emitter characteristics was observed, which would have been caused by the quantum-interference effect. © 1990, The Institution of Electrical Engineers. All rights reserved.

DOI： 10.1049/el:19900683

Scopus

researchmap

記述言語：英語   掲載種別：研究論文（学術雑誌）  

We have observed dips with negative values in the curve of the differential conductance of the base versus the base-emitter voltage dIB/dV BE at 77 K in GaInAs/InP hot-electron transistors grown by organometallic vapor phase epitaxy. The efficiency of the hot-electron transmission across the 40-nm-thick base was more than 0.99. In comparison with a theoretical model considering that observed dips should have been caused by the resonant states in the base well, the phase relaxation time of the hot electron is estimated to be in the order of 0.1 ps or longer.

DOI： 10.1063/1.103956

Scopus

researchmap

記述言語：英語   掲載種別：研究論文（学術雑誌）  

Rectangular InP corrugations of 70 nm pitch and 40 nm depth were buried with GalnAs by OMVPE so as to preserve the rectangular shape. A low regrowth temperature and short heating up time in an atmosphere of high PH3 partial pressure are effective in the suppression of thermal deformation during regrowth. © 1990, The Institution of Electrical Engineers. All rights reserved.

DOI： 10.1049/el:19900572

Scopus

researchmap

記述言語：英語   掲載種別：研究論文（学術雑誌）  

The laser threshold of Threedimensional GalnAsP/InP quantum-box lasers is analyzed. The optimized quantum-box array laser structure for the lowest threshold current density at room temperature is obtained theoretically, taking into account the effect of carrier leakage. The lowest threshold current densities are 14, 27, and 61 A/cm2 for 10, 20, and 40 cm 1 of cavity loss, respectively. The threshold current density taking into account fluctuation in quantum-box size is also calculated. The ideal structure of the quantum-box laser is discussed and the modulation-doped structure looks attractive for the suppression of carrier leakage. © 1989 IEEE

DOI： 10.1109/3.35225

Scopus

researchmap

記述言語：英語   出版者・発行元：IEEE  

We demonstrated an excellent output power (Pout) density performance using a novel InAlGaN/GaN-HEMT with an 80-nm gate for a W-band amplifier. To eliminate current collapse, a unique double-layer silicon nitride (SiN) passivation film with oxidation resistance was adopted. The developed discrete GaN-HEMT achieved a Pout density of 3.0 W/mm at 96 GHz, and we fabricated W-band amplifier MMIC using the air-bridge wiring technology. The Pout density of the MMIC reached 3.6 W/mm at 86 GHz. We proved the potential of the developed InAlGaN/GaN-HEMT experimentally using our unique device technology. With the aim of future applications, we developed a novel wiring-inter-layer technology. It consists of a cavity structure and a moisture-resistant dielectric film technology. We demonstrated excellent high-frequency performances and low current collapse originating in humidity-degradation using AlGaN/GaN-HEMT. This is also a valuable technology for InAlGaN/GaN-HEMT.

DOI： 10.1109/LEC.2016.7578927

Web of Science

Scopus

researchmap

記述言語：英語   出版者・発行元：IEEE  

Hafnium Disulfide (HfS2) is one of the transition metal dichalcogenides which is expected to have high electron mobility and finite bandgap. However, the fabrication process for HfS2 based electron devices has not been established, and it is required to bring out the superior transport properties of HfS2. In this report, we have investigated the effects of ALD HfO2 passivation on the current properties of HfS2 Transistors. HfO2 passivation of HfS2 surface achieved the improvement in drain current and significant reduction of hysteresis. The charge trapping at the outermost surface seems to be the dominant factor for degradation of the current stability.

DOI： 10.1109/NANO.2016.7751508

Web of Science

Scopus

researchmap

記述言語：日本語   出版者・発行元：Institute of Electrical Engineers of Japan  

We report the dependence of I-V characteristics on doping concentration in a GaAsSb/InGaAs Double-Gate Tunnel FET (GaAsSb/InGaAs DG TFET) by simulation. Increase of doping concentration at source region is effective to achieve high on-current. However, it leads degradation of off-current. To suppreb off-current, low doping concentration at drain region is effective, although on-current is decreased by high series resistance in the drain when drain concentration is too low. As a result of optimization, we obtain ION of 466 μA/μm and IOFF of 10 pA/μm at VDD 0.5 V in a GaAsSb/InGaAs DG TFET.

DOI： 10.1541/ieejeiss.136.467

Scopus

researchmap

© 2015 IEEE. In this work, we demonstrated an excellent output power (Pout) density of 3.0 W/mm at 96 GHz using a novel collapse-free InAlGaN/GaN-HEMT with an 80-nm gate for a millimeter-wave amplifier. The developed devices showed basic reliability for commercial products. To eliminate the current collapse, a unique double-layer silicon nitride (SiN) passivation film that has oxidation resistance was adopted. We proved the potential of InAlGaN/GaN-HEMT using our unique device technology experimentally and analytically.

DOI： 10.1109/IEDM.2015.7409659

Scopus

researchmap

記述言語：英語   出版者・発行元：IEEE  

© 2015 IEEE. In conclusion, we demonstrated the fabrication and I-V characteristics of HfS2FETs. For the channel thickness of less than 7.5 nm, a clear saturation behavior and drain current of 0.2 μA/μm were observed with reasonably good on/off current ratio. These results provide basic knowledge of HfS2as a channel material for FET.

DOI： 10.1109/DRC.2015.7175643

Web of Science

Scopus

researchmap

To obtain high performance in nMOSFETs, the introduction of high-mobility channel material such as InGaAs is a promising approach. However, the required source doping concentration for a high driving current cannot be obtained by ion implantation in InGaAs. One method of achieving a heavily doped source in III-V semiconductor MOSFETs is by growing an epitaxial source/drain structure. 1 For realizing such a source, we used a regrown InGaAs source 2,3 and an InP source.4 The regrown sources are also important for high current drivability of 3D or multi-gate devices. The other advantage of regrowth in multi-gate devices is a smooth surface for high electron mobility.5 In this report, we describe the growth process for high-performance InGaAs MOSFETs. © 2014 IEEE.

DOI： 10.1109/DRC.2014.6872380

Scopus

researchmap

Triangular In0.53Ga0.47As-OI nMOSFETs with smooth (111)B side surfaces on Si have been successfully fabricated. Triangular shaped channels with bottom width down to 30 nm were formed by MOVPE growth on narrow InGaAs-OI fins. The formed (111)B surface was demonstrated to provide higher mobility compared with reference InGaAs-OI tri-gate (1.9×) as well as bulk (100) InGaAs nMOSFETs (1.6×), which is possibly due to reduced D it in conduction band and resultant suppressed carrier trapping at the MOS interface. Lower noise and hysteresis in triangular device supported this model. High Ion value of 930 μA/μm at Lg = 300 nm indicates the potential of the triangular InGaAs-OI nMOSFETs for ultra-low power and high performance CMOS applications. © 2013 IEEE.

DOI： 10.1109/IEDM.2013.6724542

Scopus

researchmap

記述言語：英語  

DOI： 10.1155/2013/596065

Scopus

researchmap

The two-dimensional effect in the reverse gate leakage current of GaN HEMTs is studied by using the TCAD simulation. At the high voltage region, the extension of the potential from the gate to the drain latterly is important role for the reverse gate leakage current characteristics. On the other hands, the electrons flow vertically from the gate electrode to the GaN channel layer at the low gate voltage. Our model explained excellently the experimental results on wide voltage range from low to 80 V. In addition, we studied the gate annealing process as one of the gate current reduction method. © 2012 IEEE.

DOI： 10.1109/CSICS.2012.6340088

Scopus

researchmap

We fabricated an InP heterojunction bipolar transistor (HBT) with a 55-nm-wide emitter. For an emitter width of 55 nm and that greater than 300 nm, the maximum gain was around 15 and around 120, respectively. To confirm the relationship between the acceptable current density and the emitter width, we measured the current density when the current gain was half its maximum value. The measured current density Jhalf increased with a decrease in the emitter width. The highest observed current density was approximately 5 MA/cm2 and was nearly equal to the highest reported current density of InP HBTs. © 2012 IEEE.

DOI： 10.1109/ICIPRM.2012.6403354

Scopus

researchmap

記述言語：英語   出版者・発行元：IOP PUBLISHING LTD  

In this paper, the reduction in the output conductance (g(o)) of a vertical InGaAs channel metal-insulator-semiconductor field-effect transistor (MISFET) is reported. While vertical InGaAs channel MISFETs exhibit a high drain current density, their large go is a disadvantage. Monte Carlo simulation suggests that the large go might be caused by conduction band bending due to many space charges between the gate and drain. To prevent conduction band bending, a device in which the gate electrode overlaps with the drain region was proposed and fabricated. Consequently, go was decreased from 3.2 to 1 S/mm. (C) 2012 The Japan Society of Applied Physics

DOI： 10.1143/APEX.5.024101

Web of Science

Scopus

researchmap

記述言語：英語  

We fabricated a vertical tunnel field-effect transistor (TFET) with a GaAsSb/InGaAs heterojunction using a 5-nm-thick Al2O3 dielectric. The 26-nm width of the narrow channel mesa structure was confirmed using citric acid solution. The minimum sub-threshold slope (SS) was 71 mV/dec. On the basis of our simulated and experimental results, the SS was estimated to be 54 mV/dec for an effective oxide thickness (EOT) of 1 nm. © 2012 IEEE.

DOI： 10.1109/ICIPRM.2012.6403309

Scopus

researchmap

In this paper, we report InGaAs channel MOSFETs with an InP source contact. InP source contact enables the suppression of carrier starvation and the easy shrinkage of the channel length by anisotropic etching. In fabricated 50-nm InGaAs channel MOSFETs, I D = 2.4A/mm at V D=0.5V were observed. On the other hand, degradations of V th and SS by the short channel effect were also observed. Thinner channels will be required in order to suppress this effect. © 2011 IEEE.

DOI： 10.1109/IEDM.2011.6131545

Scopus

researchmap

We previously reported that a vertical InGaAs MISFET with an electron launcher, undoped channel to prevent electron scattering, and 15-nm-wide mesa achieved a high current density of 7 MA/cm 2. However, the reported structure was designed only for DC operation, as it had a large parasitic capacitance between the gate electrode and source. Here we report on the impact of this parasitic capacitance on high-speed operation and the effectiveness of a BCB insulating layer in mitigating the capacitance. In measurements on a test element group, insertion of a BCB layer reduced the parasitic capacitance from 27.6 pF/cm to 1.68 pF/cm, and transistor operation with an inserted BCB layer was confirmed. © VDE VERLAG GMBH.

Scopus

researchmap

DOI： 10.1109/ISLC.2010.5642741

Scopus

researchmap

The fabrication process of an 80 nm In0.7Ga0.3As MHEMT device with flip-chip packaging on Al2O3substrate is presented. The flip-chip packaged device exhibited good dc characteristics with high IDS= 425 mA/mm and high gm= 970 mS/mm at VDS= 1.5 V. Besides, the RF performances revealed high gain of 10 dB at 50 GHz and low minimum noise figure (NFmin)below 2 dB at 60 GHz, showing the feasibility of flip-chip packaged In0.7Ga0.3As MHEMT device for low noise applications at W-band.

DOI： 10.1109/ICIPRM.2010.5516317

Scopus

researchmap

We demonstrated a high-mobility InP 5 nm/InGaAs 12 nm composite channel MOSFET with MOVPE regrown n+-source/drain region for low series resistance and high source injection current. A gate dielectric was SiO 2 and thickness was 20 nm. A carrier density of regrown InGaAs source/drain layer was over 4 × 1019 cm-3. In the measurement of submicron (= 150 nm) device, the drain current was 0.93 mA/μm at Vg = 3 V, Vd = 1 V and the peak transconductance was 0.53 mS/μm at Vd = 0.65 V, respectively. The channel length dependence of transconductance indicated the good relativity.

DOI： 10.1109/ICIPRM.2010.5515922

Scopus

researchmap

It is important for shrinking the mesa width of a channel region in a vertical InGaAs channel MISFET for carrying out high-speed operation and for obtaining a steep sub-threshold slope. Therefore, we introduced selective undercut etching after the dry etching of the mesa structure. In the fabricated device with 60-nm-long channel, the channel mesa width became 15 nm. The maximum drain current density at Vds= 0.75 V and Vg= 1.5 V was 1.1 A/mm and the maximum transconductance at Vds= 0.75 V and Vg= 0 V was 530 mS/mm.

DOI： 10.1109/ICIPRM.2010.5516014

Scopus

researchmap

記述言語：英語   出版者・発行元：JAPAN SOC APPLIED PHYSICS  

We proposed a vertical In GaAs channel metal-insulator-semiconductor field effect transistor (MISFET) with an ultranarrow mesa structure, an undoped channel, and a heterostructure launcher With the aim of obtaining a narrow mesa structure, we proposed the concept of performing selective undercut etching after dry etching We fabricated the proposed device with a 60-nm-long and 15-nm-wide channel mesa structure In the fabricated device, the observed drain current density was 1 1 A/mm Because the channel mesa width was 15 nm, the drain current density per unit area was 7 MA/cm(2) Thus, a high current density was achieved for an ultranarrow mesa structure (C) 2010 The Japan Society of Applied Physics

DOI： 10.1143/APEX.3.084101

Web of Science

Scopus

J-GLOBAL

researchmap

記述言語：英語   出版者・発行元：IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC  

High-performance metamorphic high-electron mobility transistors (MHEMTs) using an (InxGa1-xAs)(m)/(InAs)(n) superlattice structure as a channel layer have been fabricated successfully. These HEMTs with 80-nm gate length exhibited a high drain current density of 392 mA/mm and a transconductance of 991 mS/mm at 1.2-V drain bias. Compared with a regular InxGa1-xAs channel, the superlattice-channel HEMTs showed an outstanding performance due to the high electron mobility and better carrier confinement in the (InxGa1-xAs)(m)/(InAs)(n) channel layer. When biased at 1.2 V, the current gain cutoff frequency (f(T)) and the maximum oscillation frequency (f(max)) were extracted to be 304 and 162 GHz, respectively. As for noise performance, the device demonstrated a 0.75-dB minimum noise figure(NFmin) with an associated gain of 9.6 dB at 16 GHz. Such superior performance has made the devices with a superlattice channel well suitable for millimeter-wave applications.

DOI： 10.1109/LED.2010.2048995

Web of Science

Scopus

J-GLOBAL

researchmap

記述言語：英語   出版者・発行元：IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC  

We demonstrate a 100-nm-gate-recessed n-GaN/AlGaN/GaN high-electron mobility transistor (HEMT) with low-noise properties at 30 GHz. The recessed GaN HEMT exhibits a low ohmic-contact resistance of 0.28 Omega . mm and a low gate leakage current of 0.9 mu A/mm when biased at V(GS) = -3 V and V(DS) = 10 V. At the same bias point, a minimum noise figure of 1.6 dB at 30 GHz and an associated gain of 5 dB were achieved. To the best of our knowledge, this is the best noise performance reported at 30 GHz for gate-recessed AlGaN/GaN HEMTs.

DOI： 10.1109/LED.2009.2037167

Web of Science

Scopus

J-GLOBAL

researchmap

記述言語：英語   出版者・発行元：JAPAN SOC APPLIED PHYSICS  

The base transit times of an InP/GaInAs heterojunction bipolar transistor (HBT) with an ultrathin and heavily doped base are investigated by carrying out a Monte Carlo (MC) simulation. The acceleration of electrons due to a conduction-band discontinuity between the emitter and base is taken into consideration. Scattering caused by the spontaneous emission of hole plasmons considerably increases the base transit time even when the thickness of the base is 20 nm. Band-gap grading in the base effectively sweeps slow electrons into the collector, and the increase in the base transit time is partially suppressed. The MC simulation shows that when the band-gap grading is just twice the thermal energy, the transit time of the 20-nm-thick base decreases by 40%. (C) 2010 The Japan Society of Applied Physics

DOI： 10.1143/JJAP.49.024302

Web of Science

Scopus

J-GLOBAL

researchmap

記述言語：英語   出版者・発行元：Institute of Electronics, Information and Communication, Engineers, IEICE  

We investigated collector current spreading in InGaAs single heterojunction bipolar transistors (SHBTs) having a collector thickness of 75 nm. SHBTs were fabricated with three different emitter widths-200, 400, and 600 nm-and the highest cutoff frequency that was obtained was 468 GHz. The relationship between the current density at the highest cutoff frequency and the emitter width could not be used to estimate the current spreading because it was independent of the collector-base voltage. However, the relationship between the current density with the increase in the total collector-base capacitance and the emitter width indicates current spreading in the collector. The current spreading was estimated to be approximately 90 nm. Copyright © 2010 The Institute of Electronics, Information and Communication Engineers.

DOI： 10.1587/transele.E93.C.644

Scopus

J-GLOBAL

researchmap

記述言語：英語   出版者・発行元：JAPAN SOC APPLIED PHYSICS  

We have demonstrated an InP/InGaAs composite-channel metal-oxide-semiconductor field-effect transistor with a selectively regrown n(+)-InGaAs source/drain formed by metal organic vapor-phase epitaxy. A 150-nm-long channel was fabricated using a dummy gate and by laterally buried regrowth in the channel undercut. The gate stack was formed after regrowth by replacing the dummy gate. The carrier density of the regrown layer was 4.9 x 10(19) cm(-3). The maximum drain current at a drain voltage V-d = 1 V and a gate voltage V-g = 3 V was 0.93 mA/mu m and the maximum transconductance was 0.53 mS/mu m at V-d = 0.65 V. (C) 2010 The Japan Society of Applied Physics

DOI： 10.1143/APEX.3.094201

Web of Science

Scopus

J-GLOBAL

researchmap

記述言語：英語  

We would like to report our approaches to realize epitaxially grown source toward high drain current in III-V MISFET. One approach is an InP/InGaAs composite channel MISFET with regrown InGaAs source/drain. When gate length of 150 nm was fabricated, Id at Vd = 0.8 V was 0.8 A/mm and maximum gm was 0.38 S/mm at Vd = 0.5 V. The other approach is vertical FET. In case of vertical FET with dual gate, shrinking the mesa width of channel region is important for high speed operation. Thus we introduced undercut etching after fabrication of the mesa. In fabricated device, the width of channel mesa was 15 nm. Channel length was 60 nm. Observed drain current density at Vd = 0.75 V was 1.1 A/mm. Maximum gm was 0.53 S/mm. ©2010 IEEE.

DOI： 10.1109/ICSICT.2010.5667647

Scopus

researchmap

記述言語：英語  

Due to the rapid growth of wireless communication systems, high frequency packages become very important and they require compactness, low cost and high performances even at frequency up to 60 GHz. Flip-chip assembly using organic substrate at very high frequency has become a cost competitive packaging method in semiconductor industries. ©2010 IEEE.

DOI： 10.1109/ESCINANO.2010.5700949

Scopus

researchmap

記述言語：英語   出版者・発行元：JAPAN SOCIETY APPLIED PHYSICS  

An InAs-channel high-electron-mobility transistor (HEMT) with an 80 nm gate length for ultralow-power low-noise amplifier (LNA) applications has been fabricated and characterized on a 2-in. InP substrate. Small-signal S-parameter measurements performed on the InAs-channel HEMT at a low drain-source voltage of 0.2 V exhibited an excellent f(T) of 120 GHz and an f(max) of 157 GHz. At an extremely low level of dc power consumption of 1.2 mW, the device demonstrated an associated gain of 9.7 dB with a noise figure of less than 0.8 dB at 12 GHz. Such a device also demonstrated a higher associated gain and a lower noise figure than other InGaAs-channel HEMTs at extremely low dc power consumption. These results indicate the outstanding potential of InAs-channel HEMT technology for ultralow-power space-based radar, mobile millimeter-wave communications and handheld imager applications. (c) 2009 The Japan Society of Applied Physics

DOI： 10.1143/JJAP.48.04C094

Web of Science

Scopus

J-GLOBAL

researchmap

記述言語：英語  

In this paper, the device characteristics of an InP hot electron transistor with improved gate insulation are reported. The breakdown voltage of the gate was increased from 0.5 to 2.5 V by increasing the distance between the gate and the electron transport region. Consequently, the appropriate gate bias at which a clear transconductance peak could be observed was applied. The transconductance was increased from 55 to 130 mS/mm. When the output conductance was reduced, the open circuit voltage gain was about 10. © 2009 The Japan Society of Applied Physics.

DOI： 10.1143/APEX.2.034501

Scopus

J-GLOBAL

researchmap

記述言語：英語   出版者・発行元：ELECTROCHEMICAL SOC INC  

N-type metal-oxide-semiconductor high electron mobility transistor (MOS-HEMT) devices with an InAs-channel using atomiclayer-deposited (ALD) Al2O3 as a gate dielectric have been fabricated and characterized. The device performances of a set of scaled transistors with and without high-k gate dielectric Al2O3 have been compared to determine the optimum device structure for low power and high speed applications. The measurement results revealed that the high performance InAs-channel MOS-HEMTs with the ALD Al2O3 gate dielectric can be achieved if the structure is designed properly. (C) 2009 The Electrochemical Society. [DOI: 10.1149/1.3241014] All rights reserved.

DOI： 10.1149/1.3241014

Web of Science

Scopus

J-GLOBAL

researchmap

記述言語：英語   出版者・発行元：IEEE  

We propose a vertical InGaAs MOSFET with hetero-launcher and undoped channel. In a previous trial of this particular MISFET innovation, the number of devices that achieved current modulation by gate bias was only 10% of the total number of the fabricated devices. This poor result was caused by loss of thickness of the gate dielectric. In the new version of this device, the gate stuck was fabricated by successive depositions of SiO(2) and gate metal. The number of devices achieving current modulation by gate bias now increased to 50% of the total number of the fabricated devices. Moreover, the drain current density was observed to increase from 100 mA/mm to 270 mA/mm.

DOI： 10.1109/ICIPRM.2009.5012503

Web of Science

Scopus

researchmap

記述言語：英語  

An eighty nanometer gate length InAs quantum well field effect transistors has been fabricated and the digital characteristics were evaluated. The devices show a drain-source current of 1015 mA/mm and a peak gm of 1920 mS/mm at VDS = 0.5 V. The fT and fmax are 340 GHz and 220 GHz at VDS = 0.4 V, respectively. A low delay time (C totalV/ION) of 0.54 ps was also achieved. These excellent results indicate the InAs devices are the great potential option for the future low-power logic applications at post-Si CMOS technology. ©The Electrochemical Society.

DOI： 10.1149/1.3096547

Scopus

researchmap

記述言語：英語   出版者・発行元：IEEE  

High performance MHEMTs using (InxGa1-xAs)(m)/(InAs)(n) superlattice structure as a channel layer have been fabricated successfully. These HEMTs with 80 nm gate length exhibit high drain current density of 392 mA/mm at drain bias 1.0 V and transconductance of 991 mS/mm at drain bias 1.2 V. Comparison with regular InxGa1-xAs channel, the superlattice channel HEMTs show an outstanding performance because of high electron mobility, and better carrier confinement in the (InxGa1-xAs)(m)/(InAs)(n) channel layer. The current gain cutoff frequency (f(T)) and maximum oscillation frequency (f(max)) were extracted to be 304 GHz and 162 GHz, respectively. The device demonstrated a 0.75 dB noise figure with an associated gain 9.6 dB at 16 GHz. The excellent device performance shows that the superlattice channel can be practically used for high-frequency and millimeter-wave application.

DOI： 10.1109/APMC.2009.5384333

Web of Science

Scopus

researchmap

80-nm high electron mobility transistors (HEMTs) with different Indium content in InxGa1-xAs channel from 52%, 70% to 100% have been fabricated. Device performances degradation were observed on the DC measurement and RF characteristics caused by impact ionization at different drain bias, >0.8V (InAs/In0.7Ga0.3As), > 1V (In0.7Ga0.3As) and > 1.5V (In0.52Ga0.48As), respectively. The impact ionization phenomenon should be avoided for high speed, low power application because it limits the highest drain bias of the device which in turn limits the drift velocity under specific applied electric field. © 2008 IEEE.

DOI： 10.1109/ICIPRM.2008.4702949

Scopus

researchmap

記述言語：英語   出版者・発行元：JAPAN SOCIETY APPLIED PHYSICS  

To investigate wave propagation with an extended wavefront of a ballistic hot electron in a semiconductor, we estimate the possibility of observing electron wave diffraction. Such diffraction is caused by it phase shifter and observed using a scanning probe. By quantitative comparison between theoretically simulated signals and experimental noises, the structure of the device is optimized. The pattern is expected to have a peak characteristic of such diffraction. The height of the peak is 2 times higher than that of the noise in the current measurement and the spatial fluctuation caused by nonuniformity.Thus, it is possible to increase the probability of success and tolerance in the observation experiment by lowering the noise level ill the current measurement. [DOI: 10.1143/JJAP.47.8652]

DOI： 10.1143/JJAP.47.8652

Web of Science

Scopus

J-GLOBAL

researchmap

記述言語：英語   出版者・発行元：JAPAN SOCIETY APPLIED PHYSICS  

An InAs/In(0.3)As composite channel high-electron-mobility transistor (HEMT) fabricated using the gate sinking technique was realized for ultralow-power-consumption low-noise application. The device has a very high transconductance of 100 mS/mm at at drain voltage of 0.5 V. The saturated drain-Source current of the device is 1066 mA/mm. A current grin cutoff frequency (f(T)) of 113 GHz and a maximum oscillation frequency (f(max)) of 110GHz were achieved at only drain bias volume V(ds) = 0.1V. The 0.08 x 40 mu m(2) device demonstrated a minimum noise figure of 0.82 dB and a 14 dB associated gain at 17GHz with 1.14mW DC power consumption.

DOI： 10.1143/JJAP.47.7119

Web of Science

Scopus

J-GLOBAL

researchmap

記述言語：英語   出版者・発行元：IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC  

Eighty-nanometer-gate In0.7Ga0.3As/InAs/ In0.7Ga0.3As composite-channel high-electron mobility transistors (HEMTs), which are fabricated using platinum buried gate as the Schottky contact metal, were evaluated for RF and logic application. After gate sinking at 250 degrees C for 3 min, the device exhibited a high g(m) value of 1590 mS/mm at V-d = 0.5 V, the current-gain cutoff frequency f(T) was increased from 390 to 494 GHz, and the gate-delay time was decreased from 0.83 to 0.78 ps at supply voltage of 0.6 V. This is the highest f(T) achieved for 80-nm-gate-length HEMT devices. These superior performances are attributed to the reduction of distance between gate and channel and the reduction of parasitic gate capacitances during the gate-sinking process. Moreover, such superior performances were achieved through a very simple and straightforward fabrication process with optimal epistructure of the device.

DOI： 10.1109/LED.2008.917933

Web of Science

Scopus

J-GLOBAL

researchmap

記述言語：英語  

The high-speed characteristics and off characteristics of a novel transistor with a hot-electron launcher and a transit layer of an intrinsic semiconductor whose current is controlled by an insulated gate are evaluated by Monte Carlo simulation. The dependences of the cutoff frequency fT on the gate insulator thickness, collector bias voltage, gate length and transit layer length are clarified. For the optimum stracture consisting of InP/InGaAs/W as the emitter/transit layer/collector, Au as the gate and bisbenzocyclobutene (BCB) as the gate insulator and the surrounding material, fT is 1.4 THz at the collector current density of 1.6 MA/cm2. The collector current can be controlled over four orders of magnitude by a gate voltage swing of 0.6 V. © 2008 WILEY-VCH Verlag GmbH &amp
Co. KGaA.

DOI： 10.1002/pssc.200776510

Scopus

J-GLOBAL

researchmap

記述言語：英語  

An insulated gate was introduced in hot electron transistors, in which hot electrons are propagated only in the intrinsic region after extraction from a heterostructure launcher. Voltage gain is increased by improved fabrication process. ©2008 IEEE.

DOI： 10.1109/INOW.2008.4634575

Scopus

researchmap

An 80-nm InP HEMT with InAs channel and InGaAs sub-channels has been fabricated. The high current gain cutoff frequency (ft) of 350 GHz and maximum oscillation frequency (fmax) of 360 GHz were obtained at VDS = 0.7 V due to the high electron mobility in the InAs channel. DC and RF characterizations on the device have been performed and the onsate breakdown voltage of the device was measured to be 1.75V. A 2-stage MMIC gain block was designed using such device. A simulated gain of better than 12 dB from 54 GHz to 71 GHz with only 14mW DC power consumption was achieved. Such high performance HEMTs demonstrated in this study shows great potential for very low power millimeter wave applications. Keywords-InP HEMT; InGaAs; gain block; MMIC.

DOI： 10.1109/APMC.2007.4554851

Scopus

researchmap

記述言語：英語   出版者・発行元：IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC  

An 80-nm InP high electron mobility transistor (HEMT) with InAs channel and InGaAs subchannels has been fabricated. The high current gain cutoff frequency (f(t)) of 310 GHz and the maximum oscillation frequency (f(max)) of 330 GHz were obtained at V-DS = 0.7 V due to the high electron mobility in the InAs channel. Performance degradation was observed on the cutoff frequency (f(t)) and the corresponding gate delay time caused by impact ionization due to a low energy bandgap in the InAs channel. DC and RF characterizations on the device have been performed to determine the proper bias conditions in avoidance of performance degradations due to the impact ionization. With the design of InGaAs/InAs/InGaAs composite channel, the impact ionization was not observed until the drain bias reached 0.7 V, and at this bias, the device demonstrated very low gate delay time of 0.63 ps. The high performance of the InAs/InGaAs HEMTs demonstrated in this letter shows great potential for high-speed and very low-power logic applications.

DOI： 10.1109/LED.2007.906083

Web of Science

Scopus

J-GLOBAL

researchmap

記述言語：英語   出版者・発行元：IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG  

In this paper, we describe the effect of p-regions on the I-V kink in GaAs FETs. A kink-free p-pocket-type self-aligned gate GaAs MESFET (PP-MESFET), which does not include p-regions under the channel, has been analyzed and compared with a conventional buried-p-type self-aligned gate GaAs MESFET (BP-MESFET) using two-dimensional device simulation. The relation between the I-V kink and the layout of pregions has been demonstrated by numerical simulation for the first time. For both the BP-MESFET and PP-MESFET, impact ionization produces holes in high-field regions. The holes accumulate under the channel, widen the channel, and cause an abrupt increase in drain current in turn in the BP-MESFET. On the other hand, in the PP-MESFET, holes generated in the high-field region are transported to the source region easily over the lower barrier owing to the absence of p-regions under the channel. Holes do not accumulate under the channel, leading to kink-free I-V characteristics of the PP-MESFET. P-regions should be located so as not to cause the accumulation of holes in GaAs FETs where p-regions are required for high-frequency performance.

DOI： 10.1093/ietele/e90-c.8.1643

Web of Science

researchmap

記述言語：英語   出版者・発行元：INST PURE APPLIED PHYSICS  

A 70nm In0.52Al0.48As/In0.6Ga0.4As power metamorphic high electron mobility transistor (MHEMT) with a double delta-doping structure was fabricated and evaluated. The device has a high transconductance of 827mS/mm. The saturated drain-source current of the device is 890mA/mm. A current gain cutoff frequency (f(T)) of 200GHz and a maximum oscillation frequency (f(max)) of 300GHz were achieved owing to the nanometer gate length and high indium content in the channel. When measured at 32 GHz, the 0.07x160 mu m(2) device demonstrates a maximum output power of 14.5dBm (176mW/mm) and a P I dB of 11.1dBm (80mW/mm) with a 9.5dB power gain. The excellent DC and RF performance of the 70mn MHEMT are comparable to those of InP-based HEMTs and show the great potential for Ka-band power applications.

DOI： 10.1143/JJAP.46.3385

Web of Science

Scopus

J-GLOBAL

researchmap

記述言語：英語   出版者・発行元：INST PURE APPLIED PHYSICS  

A current density of 90 kA/cm(2) was observed in hot-electron transistors controlled by gate bias. In these transistors, the base layer of a conventional hot-electron transistor was eliminated to minimize the scattering. Electron emission from the emitter was controlled by positively biased Schottky gate electrodes located on both sides of the emitter mesa. Using electron-beam lithography, emitters with an effective width of 25 nm and surrounded by gates were fabricated to obtain saturated I-V characteristics. In a previous study, the observed current density for current amplification was approximately 10 A/cm(2) at 30 K, although a resonant tunneling diode using the same epitaxial structure showed a 1 kA/cm(2) peak current density. Using a 1.75-nm-thick. AlAs barrier, the oxidation of the emitter barrier was prevented and a collector-current density of 90 kA/cm(2) and a clear negative differential resistance were observed at 30 K. A current gain of 7 and an open-circuit voltage gain of 10 were also confirmed when the collector-current density was 10 kA/cm(2).

DOI： 10.1143/JJAP.46.L202

Web of Science

Scopus

J-GLOBAL

researchmap

記述言語：英語   出版者・発行元：ELSEVIER SCIENCE BV  

A new heterojunction bipolar transistor (HBT) structure with buried SiO2 wires is proposed. SiO2 wires were buried in the InP layer by metalorganic vapor-phase epitaxy (MOVPE). The insertion of SiO2 wires under the base electrodes reduces collector capacitance because of a small dielectric constant. Two SiO2 wires of 200 nm width and 60 nm height on the InP substrate were buried in an InP DHBT structure with a flat heterointerface when the buried growth temperature was 580 degrees C and the direction of the wire was < 010 >. (c) 2006 Elsevier B.V. All rights reserved.

DOI： 10.1016/j.jcrysgro.2006.10.215

Web of Science

Scopus

J-GLOBAL

researchmap

The minimum emitter charging time for heterojunction bipolar transistors with a single n+ doped emitter layer was derived on the basis of transmission formalism. The obtained minimum charging time is almost equal to that from charge-control analysis using TCAD software. Since the calculation time based on our theory is very short, the process of emitter design is significantly simplified. © 2006 IEEE.

Scopus

researchmap

記述言語：英語   出版者・発行元：INST PURE APPLIED PHYSICS  

We theoretically examine the charging time of a double-layer emitter in heterojunction bipolar transistors (HBTs) on the basis of transmission formalism. It is indicated that the charging time is shorter in the double-layer emitter with an n(++)/n(+) combination than in the single-layer n(+) emitter. The nonparabolic band structure is responsible for this finding. Thus, the inclusion of a second layer in the emitter is essential for high-speed operation. The theory also explains the experimentally reported, charging times in state-of-the-art high-speed HBTs.

DOI： 10.1143/JJAP.45.L935

Web of Science

Scopus

J-GLOBAL

researchmap

記述言語：英語   出版者・発行元：IOP PUBLISHING LTD  

Ultrafast operation of a transistor using ballistic electron concepts and its fabrication feasibility are shown by Monte Carlo simulation and experiment, respectively. The transistor consists of InP/GaInAs heterojunction launcher of 20 nm-width and a subsequent propagation layer of 80 nm-length intrinsic GaInAs. Schottky metal gates attached on both sides of the propagation layer are biased in the forward direction so that potential barriers at Schottky junctions are flattened and hot electrons are extracted from the launcher. Hot electron velocity is as fast as 7-8x10(7) cm/s through the whole propagation layer. From stationary and step-response simulations, the cutoff frequency is higher than one THz. The emitter charging and the transit times are discussed to confirm the simulation. Finally, fabrication and operation of the transistor with 25 nm-width emitter using GaInAs/InP organo-metallic vapor phase epitaxy, electron-beam lithography, ultrafine process are demonstrated.

DOI： 10.1088/1742-6596/38/1/050

Web of Science

Scopus

J-GLOBAL

researchmap

記述言語：英語   出版者・発行元：JAPAN SOC APPLIED PHYSICS  

This is a detailed description of the first definite observation of the double-slit interference of a hot electron in a solid. The observation has been achieved by fabricating a double-slit with a 12 nm opening and a 25 nm center-to-center distance and a detection electrode with a 40 nm width. Various inspections are made theoretically to confirm the double-slit diffraction/interference. This achievement will open the door to the creation of solid-state devices with new functions based on the wave nature of electrons.

DOI： 10.1143/JJAP.44.2936

Web of Science

Scopus

J-GLOBAL

researchmap

Scopus

researchmap

記述言語：英語   出版者・発行元：IEEE  

To realize small C-BC, condition of buried growth of tungsten wire in InP was studied. By increase of flow speed (50 cm/s to 3 m/s), HBT with tungsten wire showed small C-BC (0.6fF).

DOI： 10.1109/ICIPRM.2005.1517427

Web of Science

Scopus

researchmap

記述言語：英語   出版者・発行元：IEEE  

Recently, InP HBTs with submicron emitter showed high cutoff frequency. In this simulation, cutoff frequency when emitter width was around collector thickness is analyzed and possibility of smaller transit time in narrower emitter is pointed out.

DOI： 10.1109/ICIPRM.2005.1517531

Web of Science

Scopus

researchmap

20 nm periodical patterns were drawn on Si substrates by using two calixarene resists, p-chloromethyl-methoxy-calix[4]arene (CMC[4]AOMe) and p-methylacetoxycalix[6] arene (MC[6]AOAc). CMC[4]AOMe was developed as high-resolution negative resist and reported sub-10-nm resolution. MC[6]AOAc was reported as negative resist with su8b-10-nm resolution. The pattern collapses were fewer when the thickness was thinner. The results show that the minimum line edge roughness (LER) of CMC[4]AOMe was two times smaller than that of MC[6]AOAc.

Scopus

researchmap

A high-density optical disk system with super parallel optical heads using a vertical cavity surface emitting laser (VCSEL) array is described for higher data transfer rate and technological capability. Optical heads of the VCSEL array and microlens array play key roles for obtaining higher evanescent light from small apertures with the optical disk, which is coated with lubricant and protective films on the flat surface in order to keep the gap between the super parallel optical head and the disk surface within 20 nm. Higher throughput efficiency has been obtained in the near-field semiconductor optical probe array head. However, the obtained evanescent light power is about 10 μW from a 100 nm probe aperture and 1 m W VCSEL power, which is still not enough to write a bit on the phase change optical disk. One solution to improve the optical power more than 10 times is to develop a special nanofabricated optical probe array of higher throughput efficiency. A metal fine grating fabrication method to get evanescent light wave resonant enhancement has been studied along with a 2-dimensional finite difference time domain simulation technique.

Scopus

researchmap

記述言語：英語   出版者・発行元：INST PURE APPLIED PHYSICS  

The impact of latent image quality on line edge roughness (LER) in 100, 50 and 2 keV electron beam lithography was investigated. There is a minimum LER of about 2 nm achievable with current resist systems though the LER increases as a result of the amplification of bandwidth of the threshold level by the slope of the quasi-beam profile (QBP), which is a latent image profile in which the line spread function is assumed to be Gaussian. A plausible cause of the minimum LER is the domain size of resist materials such as polymer/monomer aggregation. Analysis of the LER dependence on the 1/slope revealed the origins of the bandwidth of the threshold level: variation of the latent image profile in terms of image blur and intensity. Independent of the electron energies and resists used, the resolution of an isolated line was proportional to the blur of the QBP with an intrinsic resolution of the resists about 5 nm which has been ignored for photolithography.

DOI： 10.1143/JJAP.43.3739

Web of Science

Scopus

J-GLOBAL

researchmap

記述言語：英語   出版者・発行元：INST PURE APPLIED PHYSICS  

The modulation of drain current by gate voltage in a self-assembled monolayer (SAM) of benzene-1,4-dithiol was confirmed on the basis of the transistor structure. A device was fabricated by the shadow mask technique with an air-bridge structure. By electron beam lithography, the top area of the Au/SAM/Au junction was fabricated to be 370 nm by 230 nm. The measured current-voltage characteristics showed an exponential increase in drain current when drain voltage was increased and a decrease in drain current when gate bias was increased. Because the modulated drain current was greater than the gate leakage current, modulation by the gate bias was confirmed. However, no bonding was expected in the upper SAM/Au junction because the magnitude of the drain current was less than 100 pA.

DOI： 10.1143/JJAP.43.L337

Web of Science

Scopus

J-GLOBAL

researchmap

記述言語：英語   出版者・発行元：INST PURE APPLIED PHYSICS  

We proposed and fabricated a hot electron transistor in which an electron propagates only through an intrinsic semiconductor. In this transistor, an emitter mesa was fabricated between gate electrodes to reduce the gate leakage current from the emitter to the gate. To suppress the current leakage from the emitter and the gate pads, free-standing tungsten wires were also fabricated. The measured I-V characteristics at 20 K showed effective control of collector current by gate bias. When the device was operated, it was confirmed that the gate-leakage current from the emitter to the gate was smaller than the collector current. The calculated transconductance g(m) was approximately 10 mS/mm.

DOI： 10.1143/JJAP.43.L183

Web of Science

Scopus

J-GLOBAL

researchmap

記述言語：英語   出版者・発行元：TECHNICAL ASSOC PHOTOPOLYMERS,JAPAN  

An ultra-thin resist process is indispensable for low-energy electron-beam proximity projection lithography (LEEPL) because it uses 2-kV-accelerated electrons with small penetration depth. 70-nm-thick chemically-amplified resists for a tri-layer process were developed with the consideration of the interaction of a polymer with a spin-on-glass material, showing the resolution of 140-nm-pitch contact holes. Application of the tri-layer process developed for LEEPL to making via holes in a 90-nm-node back-end-of-line process proved that the ultra-thin resist was lithographically useful in terms of resolution and etching tolerance. Exploring the resolution performance of electron beam lithography showed that line edge roughness and resolution limit of resist patterns was in linear relation with blur of latent image profile. Reducing the resist thickness is effective in enhancing the resolution of LEEPL because 47 % of the blur is attributed to electron scattering. A Monte Carlo simulation shows that the blur caused by the electron scattering decreases 41 %. to 20 nm from 34 nm, by reducing the resist thickness to 30 nm from 70 nm.

DOI： 10.2494/photopolymer.17.581

Web of Science

Scopus

J-GLOBAL

researchmap

記述言語：英語   出版者・発行元：IEEE  

InP hot electron transistor with reduced emitter width was fabricated for controllability of collector current by gate bias. In our hot electron transistor, an electron propagates only through an intrinsic semiconductor. To reduce emitter width and remove the leak pass, InP regrowth process for metal gate was eliminated. As a result, the two-terminal emitter-gate current-voltage characteristics showed negative differential resistance and the emitter current passed through the double barrier structure was confirmed. Furthermore gate-collector leakage current could be reduced as a result of reducing gate electrodes area. In common-gate characteristics, linear increase of collector current due to resonant tunneling emitter structure was confirmed.

Web of Science

Scopus

researchmap

記述言語：英語   出版者・発行元：INST PURE APPLIED PHYSICS  

To apply the ballistic nature of hot electrons, an InP hot electron transistor with a buried metal (BM-HET) is reported. In this device, carriers are extracted from the emitter by an attractive potential originating from an embedded metal grating, and they propagate through intrinsic semiconductor material only. A simple estimation shows a high cutoff frequency and low output conductance. The estimated highest cutoff frequency is approximately 1 THz. Fabricated devices show that the collector current increased with the gate bias. After extraction of the leakage cur-rent, a clear saturation of the collector current in common-emitter characteristics was confirmed and the possibility of BM-HET as a candidate for high-speed electron devices was demonstrated.

DOI： 10.1143/JJAP.42.7221

Web of Science

Scopus

J-GLOBAL

researchmap

記述言語：英語   出版者・発行元：INST PURE APPLIED PHYSICS  

GaInAs/InP heterojunction bipolar transistors (HBTs) with a single 0.1-mum-wide tungsten wire were fabricated. The tungsten wire was buried in an undoped InP collector layer and functioned as a collector electrode. In a previous process of fabricating HBTs with buried wires, we could not achieve a device operation with only a single wire. One of the possible reasons for this failure was the insufficient growth of the buried wire, because this wire requires a long growth time. The nonuniformity of facet formation in a previous wet etching process used to fabricate an InP emitter also contributed to the failure. By increasing the growth time of the buried wire and changing the wet etching solution used to enable uniform fabrication of emitter mesas, we observed a transistor operation with a current gain of 20 in the fabricated HBT. The emitter area of the device was 0.1 x 0.5 mum(2).

DOI： 10.1143/JJAP.42.L1501

Web of Science

Scopus

J-GLOBAL

researchmap

A clear observation of the double-slit interference of the hot electron in the devices fabricated using the mentioned techniques was reported. Such an observation was different from previous works on 2 dimensional electron gas (2DEG) with respect to the electron state and the structure causing the interference. Thus, the interference was caused by the nanometer-size double slit prepared by top-down fabrication processes, instead of the constriction due to the split-gate or impurity atoms included unintentionally.

Scopus

researchmap

記述言語：英語  

We have carried out Young’s double-slit experiment for the hot-electron wave in man-made semiconductor structures with a 25-nm-space double slit in an InP layer buried within GaInAs, a 190-nm-thick GaInAsP hot-electron wave propagation layer, and a collector array of 80 nm pitch. At 4.2 K, dependences of the collector current on the magnetic field were measured and found to agree clearly with the double-slit interference theory. The present results show evidence for the wave front spread of hot electrons using the three-dimensional state in materials, for the first time, and the possibility of using top-down fabrication techniques to achieve quantum wave front control in materials. © 2003 The American Physical Society.

DOI： 10.1103/PhysRevLett.91.216803

Web of Science

Scopus

researchmap

A self-assembled monolayer (SAM) molecule is attractive as an active region of an electron device because of its inherent small thickness (∼l-2 nm) between each electrode. We reported processes to fabricate small Au/SAM/Au junctions by using electron beam lithography. As a SAM molecule, we used benzene-1,4-dithiol on Au. To obtain an atomically flat Au electrode without deformation of shape, lower deposition rate, lower sample temperature, and adequate annealing temperature were required. By using a SiO2pattern as a shadow mask, twice oblique evaporations made small Au/SAM/Au junctions. A minimum feature size of slit of a SiO2pattern was 160 nm by using electron beam lithography. Si substrate isolated by SiO2works as a gate electrode of three terminal devices by the Au/SAM/Au junctions. Observed current-voltage characteristics between the drain and the source showed nonlinear characteristics and weak modulation by gate bias was observed. The processes to improve device characteristics are also discussed.

DOI： 10.1117/12.479602

Scopus

researchmap

記述言語：英語   出版者・発行元：INST PURE APPLIED PHYSICS  

We investigated the effects of low-oxygen-content metalorganic precursors on oxygen impurities and Hall mobility. The oxygen concentration in the AlInAs layer was less than 2 x 10(17) cm(-3) under all growth conditions. We confirmed the high mobility of the AlInAs/InP high electron mobility transistors (HEMT) structure with the AlInAs buffer layer (5,500 cm(2)/V.s at 300K, and 110,000 cm(2)/V.s at 77K). For the AlInAs/GalnAs HEMT Structure with the same buffer layer, weobtamed the high mobility (12,000cm(2) /V.s at 300 K, and 92,000 cm(2) /V.s at 77 K).

DOI： 10.1143/JJAP.42.L993

Web of Science

Scopus

J-GLOBAL

researchmap

researchmap

researchmap

researchmap

researchmap

researchmap

記述言語：英語   出版者・発行元：IEEE  

An AlInAs layer and high electron mobility transistor (HEMT) structures were grown using low-oxygen-content metalorganic precursors by metalorganic vapor phase epitaxy (MOVPE). The oxygen concentration in the AlInAs layer measured by secondary ion mass spectrometry (SIMS) was 7 x 10(15) cm(-3). Moreover, the mobility and sheet carrier concentrations of the AlInAs/InP HEMT structure in which a 2.5 mum-thick AlInAs buffer layer was inserted to reduce the diffusion of impurities from the substrate surface, were 5,500 cm(2)/Vs and 1.0x10(12) cm(-2) at 300 K, and 110,000 cm(2)/Vs and 8.7x10(11) cm(-2) at 77 K, respectively. For the AlInAs/GaInAs HEMT structure with the same buffer layer, mobility and sheet carrier concentrations were 12,000 cm(2)/Vs and 1.2x10(12) cm(-2) at 300 K, and 92,000 cm(2)/Vs and 1.2x10(12) cm(-2) at 77 K, respectively.

Web of Science

Scopus

researchmap

記述言語：英語   出版者・発行元：Institute of Electrical and Electronics Engineers Inc.  

In this paper, LER of resist patterns is investigated using various EB lithography. LER strongly depended on latent image quality.

DOI： 10.1109/IMNC.2003.1268599

Scopus

J-GLOBAL

researchmap

researchmap

記述言語：英語  

InP/GaInAs double heterojunction bipolar transistors (DHBTs) with a 0.1-μm-wide emitter along the 〈010〉 direction were fabricated by the self-aligned process. A DC current gain of β = 51 as a maximum value was observed. Current amplification was confirmed even when an emitter current was 1 μA. A 0.1-μm-wide emitter was formed by the combination of CH4/H2-reactive ion etching and two kinds of wet etching based on HCl. To our knowledge, this HBT has the narrowest emitter that has ever been reported.

DOI： 10.1143/JJAP.41.L121

Web of Science

Scopus

J-GLOBAL

researchmap

We attempted to observe interference pattern of hot electron passing through 25 nm pitch GaInAs/InP buried double slit by 80 nm periodical electrodes. To get sufficient isolation of fine electrodes one another, we inserted small conduction band discontinuity and etched surface of spaces between the electrodes. We made five period fine electrodes. Unfortunately, three electrodes did not show the current and observed current from one electrode was too large. However, the one electrode showed the modulation of the current on magnetic field. The result was compared with theoretical pattern by interference of hot electrons.

Scopus

researchmap

記述言語：英語   出版者・発行元：Institute of Electrical and Electronics Engineers Inc.  

Summary form only given. We fabricate Au/SAM/Au devices by using an EB lithography and demonstrate the current-voltage (IDS-VDS) characteristics.

DOI： 10.1109/IMNC.2002.1178537

Scopus

researchmap

記述言語：英語   出版者・発行元：Institute of Electrical and Electronics Engineers Inc.  

Transistors with vertical heterostructures are attractive because of their inherent controllability of the propagating distance. However, a heavily doped layer introduces impurity scattering and carrier-carrier scattering in the base layer. To eliminate the doped layer from the active region, we proposed a hot electron transistor (HET) with a buried metallic gate. In this device, the base layer in the hot electron transistor is replaced by an embedded metal grating, which is forward biased in order to extract carriers from the emitter. Data for the conduction band edge when the device is operated is given. An attractive potential in the undoped region is clearly different from a permeable base transistor, which uses doped channel depletion. In this report, we present an InP HET with a buried metallic gate. To reduce leakage current between emitter and gate, we used freestanding tungsten wire. A simple estimation of the device speed is also presented.

DOI： 10.1109/DRC.2002.1029531

Scopus

researchmap

researchmap

記述言語：英語   出版者・発行元：Institute of Electrical and Electronics Engineers Inc.  

When carriers are propagated only through intrinsic semiconductor, high-speed transistors can be realized due to reduction of scattering. We proposed hot electron transistor with a buried metallic gate (BM-HET) using double barrier as an emitter. In this device, gate metal buried in intrinsic semiconductor works as Schottky barrier to make attractive potential. Potential of the gate metal modulates the barrier height, resulting in modulation of the emitter current. In this report, we present freestanding wires fabricated by etching after buried growth to reduce a leakage current of BM-HET.

DOI： 10.1109/IMNC.2002.1178534

Scopus

J-GLOBAL

researchmap

researchmap

記述言語：英語  

Fabrication process for narrow emitter along <010> direction in heterojunction bipolar transistor fully drawn by electron beam lithography was studied. Emitter structure of a 100 nm width was formed by using epitaxial structure with 30-nm-thick InP layer of emitter. Transistor operation of devices with 0.5-μm-wide emitter was confirmed. This process can be applied to a buried metal heterojunction bipolar transistor (BM-HBT) with narrow emitter, resulting in high-speed operation of BM-HBT.

Web of Science

Scopus

researchmap

A buried metal heterojunction bipolar transistor with a 0.5-μm-wide emitter was fabricated by electron-beam lithography, in which three tungsten wires of 100 nm width, 100 nm height and 200 nm period were buried in the InP collector layer. For the device with an emitter area of 0.5 × 2.5 μm2, total base-collector capacitance was reduced to about 30% of that calculated from the physical dimensions of a conventional heterojunction bipolar transistor, and a current gain cutoff frequency of 86 GHz and a maximum oscillation frequency higher than 135 GHz were obtained.

DOI： 10.1143/jjap.40.L735

Scopus

J-GLOBAL

researchmap

InP based double heterojunction bipolar transistors (DHBTs) with emitter width of 0.1 μm were reported. Emitter mesa with vertical facet was formed by combination of CH4/H2-reactive ion etching (RIE) and wet etching using two different HCl based solutions. Self-aligned base electrode was formed with 0.1 μm thick InP emitter layer, by control of the lateral extent of undercut etching less than 0.1 μm.

Scopus

researchmap

researchmap

researchmap

researchmap

researchmap

researchmap

researchmap

記述言語：英語   出版者・発行元：公益社団法人 応用物理学会  

We report a novel approach for improving the performance of InP-based heterojunction bipolar transistors (HBTs). A buried-metal heterojunction bipolar transistor (BM-HBT), in which tungsten stripes of the same area as the emitter metal were buried in an i-InP collector layer, was fabricated for the first time. The aim in fabricating this structure is to realize a reduction in the total base-collector capacitance (CBCT). In the measurement of microwave S-parameters, CBCT of 10.3 fF was evaluated. The effective base-collector junction area of the BM-HBT was estimated to be 22% that of conventional-HBT considering the difference in collector thickness.

DOI： 10.1143/jjap.39.L503

Scopus

J-GLOBAL

researchmap

記述言語：英語   出版者・発行元：公益社団法人 応用物理学会  

We studied the peak width of current vs voltage (I-V) characteristics of triple-barrier resonant tunneling diodes (TBRTDs) experimentally and theoretically. A GaInAs/InP TBRTD was fabricated by organo metallic vapor phase epitaxy (OMVPE). A theory of I-V characteristics of TBRTDs was developed by taking the structural inhomogeneity into account to explain the experimental peak width. The fluctuation of the well width in a TBRTD grown by OMVPE was estimated as two atomic layers. © 2000 The Japan Society of Applied Physics.

DOI： 10.1143/JJAP.39.3314

Scopus

J-GLOBAL

researchmap

As preliminary trial to make a vacuum emitter based on double barrier structure, hetero-structure with 5.3 nm-thick AlAs double barriers and a 6.5 nm GaInAs well layer was grown on an InP substrate by MOVPE. After growth, mesa with an area of 2×5 μm2 were formed and half of top of mesa was covered by Au/Cr metal for contact while the other was exposed for the emission. When emitter applied voltage was over 14V, an emission. current was observed. Efficiency emission was about 10-3.

Scopus

researchmap

記述言語：英語   出版者・発行元：Elsevier Science B.V.  

We studied the buried growth of a GaAs layer over a tungsten stripe using organometallic vapor-phase epitaxy. Triethylgallium (TEG) and trimethylgallium (TMG) were used as group III sources. For growth without polycrystal-like deposition on tungsten surface, the required growth temperature using TMG was lower than that using TEG. For 2-μm-thick growth over a 1-μm-wide tungsten stripe, the flatness of the surface grown using TMG was better than that using TEG. Therefore, the migration length of TMG on tungsten and GaAs must be longer than that of TEG. For a heterojunction bipolar transistor with a tungsten stripe as the collector electrode, a 70-nm-wide tungsten stripe was buried under a 0.77-μm-thick layer of GaAs with a flat surface using TMG. A current gain of 4 was measured although the active region was grown over tungsten stripe.

DOI： 10.1016/S0022-0248(00)00688-6

Scopus

J-GLOBAL

researchmap

researchmap

researchmap

researchmap

記述言語：英語   出版者・発行元：Elsevier Science Publishers B.V.  

To conduct Young's double slit experiment using a semiconductor, fabrication techniques for 80 to 100-nm-period fine electrodes with 30 to 40-nm thickness are reported. To obtain a resist pattern suitable for the lift-process, we used a double-layer resist with ZEP-520 and PMMA. The mixing of C60 into both layers and rinsing by perfluorohexane (PFH) prevented pattern collapse. As a result, a Au/Cr pattern with a 80-nm period over 30-nm steps was obtained. Using the developed process, we fabricated a device for observing the interference pattern. Unfortunately, the collector current from each electrode was not uniform. Moreover, the current showed anomalous behavior. The current occasionally converged in two different points and sudden jumps from the lower converged point to the upper converged point were also observed in time-dependent measurements. Such anomalous behavior might be explained in terms of a change in the ionization of an impurity near the metal-semiconductor interface.

DOI： 10.1016/S0169-4332(00)00113-6

Scopus

J-GLOBAL

researchmap

記述言語：英語   出版者・発行元：Elsevier Sci B.V.  

Toward nano-metal buried structure in InP, we studied the fabrication process of nano-tungsten wire and the InP buried growth of tungsten stripes. A tungsten wire with a 20 nm width was fabricated by the proposed metal-stencil liftoff, in which gold/chromium and SiO2 replace resist to prevent thermal deformation in a conventional liftoff process. The buried growth of tungsten stripes with 1 μm widths and 2 μn pitch by organometallic vapor phase epitaxy (OMVPE) was studied. Tungsten stripes were buried under the flat InP layer of 1.1 μm thickness, and the ratio of grown InP thickness to buried tungsten width was about 1.

DOI： 10.1016/S1386-9477(00)00084-9

Scopus

J-GLOBAL

researchmap

記述言語：英語   出版者・発行元：IEEE  

We fabricated GaInAs/lnP based buried metal heterojunction bipolar transistors (BM-HBTs), in which tungsten stripe with the same area as the emitter was buried with an intrinsic collector layer. In this device, there was no conductive layer under the extrinsic base region to reduce total base-collector capacitance (C-BCT) Though tungsten was embedded in an active region of HBTs, flat surface of base layer and no void formation around buried tungsten were confirmed by the observation of cross section. C-BCT Of 10.3 fF; was calculated from Y-12 parameters and an effective base-collector junction area of BM-HBT was estimated at 22% of conventional-HBT.

Web of Science

Scopus

researchmap

記述言語：英語   出版者・発行元：Elsevier Sci B.V.  

A versatile hot electron emitter of InGaAs/AlAs heterostructure with wide energy range at high current density has been designed theoretically and fabricated experimentally. Such an emitter can supply a high current density up to 2.5 kA/cm2 at 3 eV hot electron energy. A good agreement between the theoretical calculation results and experimental results has been obtained. It leads to an initially important application for studying the hot electron dynamics in the scanning hot electron microscopy (SHEM) experiment.

DOI： 10.1016/S1386-9477(00)00075-8

Scopus

researchmap

We propose a buried metal heterojunction bipolar transistor (BM-HBT), in which buried metal in the collector layer could reduce the total base-collector capacitance. To show the possibility of making BM-HBT, we fabricated an InP-based HBT with buried tungsten mesh replacing the subcollector layer, where tungsten mesh works as a schottky collector electrode. A flat heterostructure on the InP collector layer of the buried tungsten mesh was confirmed by a cross-sectional SEM view. A DC current gain of 12 was measured from the common-emitter collector I-V characteristics.

Scopus

researchmap

記述言語：英語   出版者・発行元：Elsevier Science Ltd  

GaInAs/AlAs/InP resonant tunnelling diodes with three different barrier thicknesses (3.5, 5.3, and 7 nm) were fabricated by metalorganic vapor phase epitaxy and the barrier thickness dependence of the peak current density was measured. The range of peak current was from 100 to 0.1 A/cm2. In the measurement of peak current density distribution, the deviations of peak current density became larger when the barrier became thicker. This fluctuation of peak current density can be explained by the thickness fluctuation of the barrier in the wafer's millimeter range.

DOI： 10.1016/S0038-1101(99)00079-9

Scopus

J-GLOBAL

researchmap

Deflectron as sub-millimeter-wave amplifier is theoretically analyzed. The input stage of the deflectron consists of parallel plates applied modulated signal. Wider width of two plates provides higher efficiency of deflection, while the transit time in the plates must be shorter than the inverse of angular frequency of modulation. On the other hand, narrower gap between the plates provides higher efficiency of deflection, while the narrower gap increases the loss of waveguide by the parallel plates. To get higher current passing through the narrow gap, line-shaped beam is preferred. Electron beam is designed to pass through around parallel plates waveguide and modulation is carried out by change of distance between the parallel plates.

Scopus

researchmap

To achieve a fine periodic semiconductor structure by electron beam (EB) lithography, calixarene was used as an EB resist. A 25 nm pitch InP pattern was formed successfully and 40 nm pitch InP structures were achieved with good reproducibility. A shorter developing time, precise stage motion, accurate control of the widths of lines and spaces, and slight O2 ashing were important to ob am a fine InP pattern by a two-step wet chemical etching process. Furthermore, the fabricated periodic InP pattern was buried in a GaInAs structure by organometallic vapor phase epitaxy. The introduction of tertiarybutylphosphine as the phosphorus source prevented the fine structure from deforming when the temperature was raised and a 25 nm pitch periodic structure was buried successfully © 1998 American Vacuum Society.

DOI： 10.1116/1.590430

Scopus

researchmap

To realize a fine periodical pattern by electron beam lithography, a stady for using calixarene as a resist was carried out. A 25-nm-pitch resist pattern was fabricated and transferred to a thin InP layer by two-step wet chemical etching. Precise slight O2 ashing, to eliminate residual matter was essential to transfer the pattern by wet etching. The controllability of the width was improved when using calixarene, when the period was 40 nm. Furthermore, a 25-nm-pitch InP pattern was buried in a GaInAs structure by organometallic vapor phase epitaxy. This technology could be applied to realize electron wave devices.

DOI： 10.1143/jjap.37.L827

Scopus

researchmap

An 8-nm-thick epitaxial CaF2 layer grown on an n+ -Si substrate was used as the insulator in a metal-insulator-semiconductor cathode with a 10 μm2 emitter region. The fabricated cathodes exhibited two different types of I-V characteristics. The first type showed conventional tunnel emission current of 22 pA at an emitter current of 2.4 mA and an emitter voltage of 7 V. The emitter with the other type of characteristics showed an emission current of 5.6 n A at an emitter current of 2.2 mA and an emitter voltage of 4.5 V but it showed current instability. © 1998 American Vacuum Society.

DOI： 10.1116/1.589918

Scopus

researchmap

記述言語：英語   出版者・発行元：JAPAN J APPLIED PHYSICS  

A wrapped alignment mark structure is proposed for a nano-fabrication process by e-beam lithography (EBL) with organometallic vapor phase epitaxy regrowth. To protect the alignment marks during regrowth, a SiO2 layer covers the surface of the gold mark and a thin tungsten layer is inserted between the mark and the substrate. The waveform serving as a mark detection signal is not significantly reduced after regrowth. By employing this mark system in EEL, an aligned nanostructure with a buried double-slit heterostructure and fine multi-electrodes is fabricated successfully to show the feasibility of this alignment mark method of wrapping. The center to center spacings of the double-slit and the fine electrodes are 40 nm and 50 nm, respectively.

DOI： 10.1143/JJAP.37.1518

Web of Science

Scopus

researchmap

記述言語：英語   出版者・発行元：JAPAN J APPLIED PHYSICS  

We studied the effect of spacer layer thickness on the resonant level width in resonant tunneling diodes (RTDs). GaInAs/InP RTDs were fabricated with various spacer layer thicknesses using organo-metallic vapor phase epitaxy; and the resonant level width was estimated. As a result, the resonant level width was found to decrease with increasing spacer layer thickness. To discuss this tendency, a theoretical model of the interface fluctuation between spacer layers and electrodes, caused by the random distribution of the impurity ions in electrodes, was proposed.

DOI： 10.1143/JJAP.37.445

Web of Science

Scopus

researchmap

DOI： 10.1143/jjap.37.L827

researchmap

DOI： 10.1143/JJAP.37.1518

researchmap

DOI： 10.1116/1.589918

researchmap

記述言語：英語   出版者・発行元：Elsevier Ltd  

Sub-micron hot electron transistors (HETs) fabricated by electron beam lithography (EBL) and the size dependence of current gain in HETs are described. The key process to fabricate small HETs is the small opening of the polyimide layer by dry-etching with bi-layer (PMMA/LS-SOG) resist. In this etching, removal of scum by slight wet etching and release of stress are essential to make a small opening (160 × 350 nm2). The smallest emitter size of fabricated HET was (0.3 × 1.5 + 0.6 × 1) μm2 and a Gummel plot with a current gain of 4 was observed. This gain was almost the same as that of large HETs (20 × 50 μm2). In comparison with previously fabricated small HETs with SiO2 layer, small HETs with polyimide layer show higher current gain. © 1998 Elsevier Science Ltd. All rights reserved.

DOI： 10.1016/S0038-1101(98)00051-3

Scopus

J-GLOBAL

researchmap

researchmap

DOI： 10.1143/JJAP.37.445

researchmap

A complete method for parameter extraction from small-signal measurements of InP-based heterojunction bipolar transistors (HBT's) is presented. Employing analytically derived equations, a numerical solution is sought for the best fit between the model and the measured data. Through parasitics extraction and an optimization process, a realistic model for a self-aligned HBT technology is obtained. The results of the generated sparameters from the model for a 2 x 10 /urn2 emitter area device are presented over a frequency range of 250 MHz-36 GHz with excellent agreement to the measured data. © 1997 IEEE.

DOI： 10.1109/22.552030

Scopus

J-GLOBAL

researchmap

記述言語：英語   出版者・発行元：AMER INST PHYSICS  

The influence of electron energy width in the hot electron double-slit experiment is investigated quantitatively. The required condition on the Fermi level in the emitter and the slit-spacing is derived for the experiment. In order to achieve a coherent electron source, a single-barrier graded emitter structure is discussed and its characteristics are considered. For application to the hot electron double-slit experiment, the graded emitter diode is fabricated and the current-voltage relation is measured in a supplementary experiment. (C) 1997 American Institute of Physics.

DOI： 10.1063/1.365749

Web of Science

Scopus

J-GLOBAL

researchmap

記述言語：英語   出版者・発行元：JAPAN J APPLIED PHYSICS  

As an Al-free material system, the GaInAs/GaInP heterostructure has a large conduction-band discontinuity. We,report the fabrication of GaInAs/GaInP resonant tunneling diodes which exhibit current density-voltage characteristics with a peak-to-valley current ratio of 7.8 at 4.2K. To our knowledge, this is the highest value obtained for this material system.

DOI： 10.1143/JJAP.36.5079

Web of Science

Scopus

J-GLOBAL

researchmap

記述言語：英語   出版者・発行元：JAPAN J APPLIED PHYSICS  

To estimate the phase coherent length (L(C)) of electrons in semiconductor, triple-barrier resonant tunneling diodes (TBRTDs) with GaInAs/InP heterostructures were fabricated by using organo-metallic vapor phase epitaxy (OMVPE). The current density-voltage (J-V) characteristics were measured at 4.2 K and 77 K. Moreover method of comparison between experimental and theoretical results is proposed. By comparing experimental result with theoretical result, the coherent lengths are estimated to be longer than 90 nm and 55 nm at 4.2 K and 77 K respectively.

DOI： 10.1143/JJAP.36.1846

Web of Science

Scopus

researchmap

記述言語：英語   出版者・発行元：ELSEVIER SCIENCE BV  

The electrical properties of fine-pitch Cr/Au electrodes for the observation of the hot electron interference/diffraction is presented. Using three wire electrodes of 100 nm-pitch, 20 nm thickness, 4 mu m length and 40 nm width, contact currents through the metal-semiconductor junction with area of 40 nm x 500 nm were measured. The current passing through each metal wire was measured to show the connection of the wire. This shows the possibility of observation of the hot electron interference by a double slit in semiconductor. In a preliminary experiment, the contact size dependence of the current characteristics was also investigated. As the contact size is reduced, the contact resistance per area at 0 V was found to increase.

DOI： 10.1016/S0167-9317(96)00119-0

Web of Science

Scopus

researchmap

記述言語：英語   出版者・発行元：AMER INST PHYSICS  

We report a double-slit experiment of hot electrons in a semiconductor under a magnetic field, The pitch of the double slit buried in the semiconductor is 40 nm and the electron energy is of the order of 100 meV. By applying a magnetic field, the change in current that passes through the slits is observed at the segmented collector. The measured current shows a clear minimum around B=0 T, with this behavior agreeing with a theoretical calculation based on double-slit interference. Quantitative estimation is consistent with this order of current variation. We think that these results show evidence of the observation of hot electron interference by a double slit in a semiconductor (C) 1997 American Institute of Physics.

DOI： 10.1063/1.119318

Web of Science

Scopus

J-GLOBAL

researchmap

記述言語：英語   出版者・発行元：Elsevier  

We report a double-slit experiment of hot electrons in semiconductor under a magnetic field. The pitch of the double slit buried in the semiconductor is 40 nm, and the electron energy is in the order of 100 meV. By applying a magnetic field, the change in current which passes through the slits is observed at the segmented collector. The measured current shows a minimum around B = 0 T. A simulation is presented which is based on the Fraunhofer diffraction and the path integral method. The simulation predicts the variation of current, and quantitative estimation is consistent with the order of measured current variation. We think that these results imply the hot electron interference by a double slit in a semiconductor.

DOI： 10.1016/S0167-9317(96)00084-6

Scopus

researchmap

DOI： 10.1143/JJAP.36.1846

researchmap

記述言語：英語   出版者・発行元：Elsevier  

The topography of InP and Ga0.47In0.53As surfaces grown by organometallic vapor phase epitaxy (OMVPE) was investigated using atomic force microscopy (AFM). Monolayer steps with atomically flat terraces, several hundred nanometers width, were formed for both InP and GaInAs. The boundary growth condition between step flow mode and 2D-nucleation mode was studied for InP and GaInAs, respectively. Applying step flow mode to the growth of GalnAs/InP resonant tunneling diodes, a remarkable reduction of the energy level width fom 51 to 18 meV was observed.

DOI： 10.1016/S0022-0248(97)00103-6

Scopus

J-GLOBAL

researchmap

記述言語：英語   出版者・発行元：ELECTRONIC DISPLAY INDUSTRIAL RESEARCH ASSOCIATION KOREA  

MIS emitter with epitaxial CaF2 insulator layer is presented. A 8nm thick epitaxial CaF2 layer was grown on n(+)-Si substrate and MIS cathode with 10 mu m(2) emitter region was fabricated by evaporation of 10nm-thick gold and semiconductor process. Two different type of I-V characteristics was observed. The conventional tunnel emission shows emission current of 22pA at 2.4mA as emitter current and 7V as emitter voltage. The other I-V characteristics shows emission current of 5.6nA at 2.2mA as emitter current and 4.5V as emitter voltage although it has instability of the current.

Web of Science

Scopus

researchmap

記述言語：英語   出版者・発行元：JAPAN J APPLIED PHYSICS  

We report fine pitch patterns of polycrystalline CaF2 film deposited on an InP substrate formed by e-beam exposure. Ten periods of 70-nm-pitch line patterns were fabricated. The linewidth fluctuation was found to depend on the grain size of the CaF2 film.

DOI： 10.1143/JJAP.35.6342

Web of Science

Scopus

researchmap

記述言語：英語   出版者・発行元：AMER INST PHYSICS  

Scanning hot electron microscopy (SHEM) has been proposed as an experimental technique which allows for detection of hot electrons emitted from a subsurface semiconductor structure, thus making it possible to obtain the spatial distribution of hot electrons in a device. Here we present the experimental evidence of SHEM operation. Hot electrons with energies of 3 eV are injected by means of a Si/CaF2/Au heterostructure and subsequently detected at the tip of a scanning tunneling microscope in the SHEM configuration. The measured hot electron current was approximately 4 pA for a tunnel current of 5 nA. These results, although still of a preliminary nature, show the potential of SHEM as a technique suitable for the visualization of electron wave effects in semiconductor structures. (C) 1996 American Institute of Physics.

DOI： 10.1063/1.117163

Web of Science

Scopus

researchmap

The electrical properties of Cr/Au electrodes with fine-pitch and small contact area are reported. Using three wire electrodes of 100 nm-pitch, 20 nm thickness, 4 μm length and 40 nm width, contact currents through the metal-semiconductor junction with area of 40 nm X 500 nm were measured. The current passing through each metal wire was measured to show the connection of the wire. The contact size dependence of the current characteristics was also investigated. As the contact size is reduced, the contact resistance per area at 0 V was found to increase.

DOI： 10.1143/jjap.35.L964

Scopus

researchmap

記述言語：英語   出版者・発行元：JAPAN J APPLIED PHYSICS  

The electrical properties of Cr/Au electrodes with fine-pitch and small contact area are reported. Using three wire electrodes of 100 nm-pitch, 20 nm thickness, 4 mu m length and 40 nm width, contact currents through the metal-semiconductor junction with area of 40 nm x 500 nm were measured. The current passing through each metal wire was measured to show the connection of the wire. The contact size dependence of the current characteristics was also investigated. As the contact size is reduced, the contact resistance per area at 0 V was found to increase.

DOI： 10.1143/jjap.35.L964

Web of Science

researchmap

記述言語：英語   出版者・発行元：IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC  

The total base-collector capacitance (C-BC) of GaInAs/InP double heterojunction bipolar transistors (DHBT's) has been reduced by the etching away of the semiconductor layers below the extrinsic base region, resulting in an undercut structure, The reduction was further enhanced by using a novel composite subcollector structure. A 54% reduction of total CBC and improvement of microwave characteristics (an increase of 20% in f(T) and 38% in f(max)) were observed as a result of the undercut process.

DOI： 10.1109/55.485179

Web of Science

Scopus

J-GLOBAL

researchmap

Current-voltage characteristics of triple-barrier resonant tunneling diodes are theoretically analyzed taking phase breaking into account. The peak current in predicted using conventional theories is much smaller, typically by a factor of 1/3000 for a coherent length of 100 nm, than that measured because the incoherent tunneling process is neglected. We take both the coherent and the incoherent tunneling processes into account in the analysis and show that the product of the peak current and the voltage width at half maximum of the peak current is almost constant even when the phase coherent length varies between 50 and 1000 nm. The peak current density increases by two orders of magnitude in the model developed here.

Scopus

researchmap

DOI： 10.1143/JJAP.35.6342

researchmap

記述言語：英語   出版者・発行元：IEE-INST ELEC ENG  

A novel approach for realising a double heterojunction bipolar transistor (DHBT) with a low base resistance, which incorporates a thick extrinsic bass and a regrown emitter, is proposed and demonstrated. A combination of selective MOVPE regrowth and selective wet chemical etching resulted in a new self-aligned DHBT structure. Fabricated microwave transistors exhibited good DC and microwave characteristics.

DOI： 10.1049/el:19951020

Web of Science

Scopus

J-GLOBAL

researchmap

記述言語：英語  

An ultrafine fabrication technique for hot electron interference/diffraction devices was developed. The alignment of two nanostructures by e-beam direct writing before and after crystal growth was reported for the first time. The aligned structure consists of 70 nm pitch grating GalnAs/InP buried structure and 70 nm pitch stripe electrode of Cr/Au. © 1995 The Japan Society of Applied Physics.

DOI： 10.1143/JJAP.34.4436

Scopus

J-GLOBAL

researchmap

記述言語：英語   出版者・発行元：ELSEVIER SCIENCE BV  

Buried growth and selective growth techniques by organometallic vapor phase epitaxy (OMVPE) of GaInAs have been developed for the realization of electron diffraction devices. We have obtained a 50 mm pitch buried GaInAs/InP corrugation, which is the world's smallest, using TMI.

DOI： 10.1016/0022-0248(94)91129-0

Web of Science

Scopus

J-GLOBAL

researchmap

We proposed a device for observing hot electron interference by a double slit. For this purpose we had refined and improved the fabrication techniques, especially electron beam lithography; the alignment of electron beam lithography before and after crystal growth with accuracy of 100nm was reported for the first time. We could form detection electrodes of fine pitch on a narrow mesa structure. The formation of a 50-nm-pitch InP buried structure was also reported. © 1994 Japanese Journal of Applied Physics. All rights reserved.

DOI： 10.1143/JJAP.33.925

Scopus

J-GLOBAL

researchmap

記述言語：英語  

The relationship between the resonant level width of resonant tunneling diodes (RTD) and the coherent length of electrons is investigated theoretically. The resonant level widths were measured using the second derivative of the J-V characteristics of GaInAs/InP RTDs. Measured data are compared with theory, and it is estimated that the coherent length of hot electrons is longer than 50 to 90 nm. © 1994 IOP Publishing Ltd.

DOI： 10.1143/JJAP.33.6491

Scopus

researchmap

This paper reviews progress in the development of fabrication technologies for long-wavelength GaInAs(P)/InP quantum-wire lasers. In fabrication employing an EBX direct writing method followed by wet chemical etching and OMVPE regrowth, we found several techniques to be very effective, including heating in H2 atmosphere, thin InP layer growth prior to GaInAsP optical confinement, and the use of p-type InP substrate to eliminate a p-n junction from the regrowth interface. As the result, a room-temperature CW operation of lattice-matched GaInAs/InP MQW lasers with quasi-quantum-wire size (10-30 nm wide in the period of 70 nm) active region was achieved. Similarly, room-temperature CW operations of quasi-quantum-wire lasers, consisting of compressive- or tensile-strained quantum-well structures, were realized for the first time. Threshold current as low as 16 mA (Jth = 816 A/cm2, L = 980 μm, λ = 1.46 μm) was obtained with Ga0.66In0.34As/InP tensile-strained single-quantum-well BH laser (30-40 nm wide in the period of 70 nm). Comparing the threshold current of these three kinds of lasers shows that the increase in the optical confinement factor of the active region is still an important issue. The spontaneous emission peak wavelength shift from that of quantum-film lasers made on the same wafer was largest (approximately 20 meV in energy for the wire width of 30-60 nm) in the compressively strained quasi-quantum-wire lasers; that of lattice-matched and tensile-strained lasers was only approximately 10 meV, which may be attributed to a reduced effective mass of holes along the in-plane direction.

Scopus

researchmap

記述言語：英語   出版者・発行元：IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC  

Improvements in the fabrication process of GaInAs(P)/InP devices consisting of an ultrafine structure by using two-step organometallic vapor phase epitaxy growth, electron beam exposure direct writing, and wet chemical etching are reported.
This improved process enabled us to achieve, for the first time, a room-temperature continuous-wave operation of GaInAs/InP quantum-wire lasers consisting of 5-nm-thick and 10-30 nm-wide vertically stacked triple quantum-wire active region within the period of 70 nm. A large blue shift of approximately 40 nm was observed in both the lasing and the electroluminescence spectra of Ga0.3In0.7As/InP compressively strained multi-quantum-well wirelasers consisting of a 3 nm-thick and 30-60 nm-wide five-wire active region, which suggests a reduced effective mass of holes along the in-plane direction.

DOI： 10.1109/3.234478

Web of Science

researchmap

The influence of well impurity doping on the performance of GalnAs/lnP resonant tunneling diodes (RTDs) was investigated. For undoped diodes, the peak-to-valley (P/V) current ratio was 9.7, at 2 x 1017 cm-3 it was 10.8, and at 2xi018cm-3it was 4.0. The maximum at 2xi017cm-3can be explained by potential bending, and the decrease at 2xl018cm-3can be explained by scattering. A change in the current-voltage characteristics at a doping level of 2 x 1018 cm-3can be explained by potential bending in the well. Moreover, the variation in the observed width of the resonance level can explain the change in P/V ratios. © 1993 The Japan Society of Applied Physics.

DOI： 10.1143/JJAP.32.L243

Scopus

researchmap

researchmap

記述言語：英語  

InP surfaces after (NH4)2Sxtreatment were observed by a scanning tunneling microscope (STM) in air. The stabilized image of the flat surface was observed on the sample after (NH4)2Sxtreatment for 30 s. The rms roughness was measured as 0.08 nm. When no surface treatment was applied, the surface was very rough when observed in the constant current mode. Since the STM image of the same sample with Au/Pd coating showed a flat surface and the current-voltage characteristics at the convex and concave portions were different, fluctuation of electron states on the InP surface is concluded to be the cause of the observed roughness. This result shows that a stable InP surface can be obtained by (NH4)2Sxtreatment. © 1993 The Japan Society of Applied Physics.

DOI： 10.1143/JJAP.32.L444

Scopus

researchmap

researchmap

記述言語：英語   出版者・発行元：ELSEVIER SCIENCE BV  

This paper reports higher peak-to-valley current (P/V) ratio in GaInAs/InP resonant tunneling diode (RTD) than ever. In organometallic vapor phase epitaxy, the P/V ratio depends strongly on the partial pressure of the group V gas. The obtained P/V ratios are 9.7 and 7.4 at 4 and 77 K, respectively. The width of the resonance level is 11 meV at 4 K.

DOI： 10.1016/0022-0248(92)90555-W

Web of Science

Scopus

researchmap

記述言語：英語   出版者・発行元：IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC  

Threshold current of GaInAs / GaInAsP / InP SCH quantum-well lasers with narrow (70-160 nm) wire-like active region, which were fabricated by two-step LP-OMVPE growths and wet chemical etching, was much reduced (< 1 kA / cm2 ) by using p-type InP substrates. This result indicates the importance of eliminating the p-n junction from the regrowth interface to enhance injection of holes into the active region.

DOI： 10.1109/68.157116

Web of Science

Scopus

researchmap

記述言語：英語  

Fabrication of an ultrafine pitch mask for X-ray lithography by precise crystal growth is proposed. With the use of a precise crystal growth technique, a grating pattern with nanometer pitch and/or a precision of the atomic spacing can be transferred. As a preliminary experiment, masks of GaInAs/InP layered structure were grown by organometallic vapor phase epitaxy (OMVPE) and patterns were transferred by Cu-L X-ray. One-hundred-nm patterns were transferred onto resist layers. © 1992 IOP Publishing Ltd.

DOI： 10.1143/JJAP.31.L432

Scopus

researchmap

researchmap

記述言語：英語   出版者・発行元：IOP PUBLISHING LTD  

Fabrication possibility of X-ray masks with nanometer size patterns by precise crystal growth techniques is discussed. As a preliminary experiment, using GaInAs/InP layered structure grown by OMVPE, 100nm-patterns were transferred by X-ray.

Web of Science

Scopus

researchmap

It is shown that the combined surface treatment of a (NH4)2SXtreatment and preheating improves the regrown heterointerface of n-GalnAs/i-InP in organometallic vapor phase epitaxy (OMYPE). Properties of the regrown heterointerface were evaluated from voltage-current (V-I) characteristics of the n-GalnAs/i-InP/n-GalnAs tunneling diode. This surface treatment is useful for the fabrication of ultrafine-size structures of quantum-wire, -box and electron wave devices. © 1991, IOP Publishing Ltd.

DOI： 10.1143/JJAP.30.L1702

Scopus

researchmap

記述言語：英語  

It is shown that a preheating process in a pure hydrogen atmosphere with a (NH4)2SX treatment was effective for improvement of the regrown interface in InP organometallic vapor phase epitaxy (OMVPE). The carrier concentration was under 5 x 1015 cm-3 in the entire region after the regrowth, even if we carried out various dummy processes of fabrication between the first growth and the surface treatment for improvement. Thus, this improvement will be useful for the device-required regrowth process after fabrication of an ultrafine-size structure. © 1991, IOP Publishing Ltd.

DOI： 10.1143/JJAP.30.L672

Scopus

researchmap

記述言語：日本語   出版者・発行元：The Crystallographic Society of Japan  

Fabrication of quantum wire structure is reviewed. Until now, two different approaches are reported. One is using lithography for writing pattern and regrowth for burying. The other is fabrication by single-growth using adequate processed substrate. Principles and important points of these methods are pointed out in this review. Preliminary results of quantum wire laser is also reported as application of quantum wire structure for devices.

DOI： 10.5940/jcrsj.33.141

CiNii Books

researchmap

その他リンク： https://jlc.jst.go.jp/DN/JALC/00010255810?from=CiNii

記述言語：英語   出版者・発行元：I E E E, ELECTRON DEVICES SOC & RELIABILITY GROUP  

The control of electron transport by using the coherent interaction between the electron and artificially formed potential structure is discussed. The principle of the electron wave diffraction transistor is explained. Fabrication of GaInAs/InP nanometer grating for coherent electron devices is described. Extending the concept of the coherent interaction between the electron and the potential structure, the use of the coherent interaction between the electron and impurity ions placed in the semiconductor crystal according to a design is proposed.

Web of Science

Scopus

researchmap

The highest current gain more than 100 at 77K was obtained in GaInAs/InP Hot Electron Transistor (HET) grown by organo-metallic vapour phase epitaxy. This result shows the promising of the GaInAs/InP material system for ballistic electron devices. An interesting phenomenon, that is a sudden increase of the collector current in the emitter-common characteristics was observed, which would be caused by the quantum interference effect.

DOI： 10.1049/el:19900683

Scopus

researchmap

記述言語：英語  

The highest current gain (more than 100 at 77 K) is reported in GalnAs/lnP hot electron transistor (HET) grown by organo-metallic vapour-phase epitaxy. This result shows the promise of the GalnAs/lnP material system for ballistic electron devices. A sudden increase of the collector current in the common-emitter characteristics was observed, which would have been caused by the quantum-interference effect. © 1990, The Institution of Electrical Engineers. All rights reserved.

DOI： 10.1049/el:19900683

Scopus

J-GLOBAL

researchmap

記述言語：英語   出版者・発行元：JAPAN J APPLIED PHYSICS  

This paper reports the results of crystal growth of InP on a Gd3Ga5O12(GGG) substrate. Effectiveness of the In-P/GaInAsP superlattice is shown. Substrate orientations of (100) and (111) are compared. By using the GGG(100) substrate and introducing the superlattice, the best result was obtained for growing an InP layer. From X-ray diffraction analysis, it was found that the grown InP layer was preferentially (111) oriented along the film normal. SEM and RHEED observation revealed that the grown layer was composed of polycrystalline grains with random orientation in the film plane. © 1990 IOP Publishing Ltd.

DOI： 10.1143/JJAP.29.53

Web of Science

Scopus

researchmap

記述言語：英語  

High-quality n-GaInAs grown by OMVPE using Si2H6is reported. The crystal quality was improved by high-velocity flow and was evaluated based on the sharp peak in X-ray diffraction measurement and large small-signal current gain of the hot electron transistor. © 1990 IOP Publishing Ltd.

DOI： 10.1143/JJAP.29.1910

Scopus

researchmap

記述言語：英語  

We have observed dips with negative values in the curve of the differential conductance of the base versus the base-emitter voltage dIB/dV BE at 77 K in GaInAs/InP hot-electron transistors grown by organometallic vapor phase epitaxy. The efficiency of the hot-electron transmission across the 40-nm-thick base was more than 0.99. In comparison with a theoretical model considering that observed dips should have been caused by the resonant states in the base well, the phase relaxation time of the hot electron is estimated to be in the order of 0.1 ps or longer.

DOI： 10.1063/1.103956

Scopus

J-GLOBAL

researchmap

記述言語：英語  

Rectangular InP corrugations of 70 nm pitch and 40 nm depth were buried with GalnAs by OMVPE so as to preserve the rectangular shape. A low regrowth temperature and short heating up time in an atmosphere of high PH3 partial pressure are effective in the suppression of thermal deformation during regrowth. © 1990, The Institution of Electrical Engineers. All rights reserved.

DOI： 10.1049/el:19900572

Scopus

J-GLOBAL

researchmap

記述言語：英語  

This paper describes fabrication methods for nanometer-pitch grating buried in the semiconductor for the future electron wave devices. Both wet chemical etching and selective growth are promising methods of grating formation on the surface of the semiconductor and also are damage-free processes. In the regrowth process to embed the grating, it is important to suppress the thermal deformation. Experimentally, InP corrugations 70nm-pitch grating were formed on InP surface in two ways - wet chemical etching and selective growth by OMVPE. InP gratings of 70nm pitch and 100nm depth were buried by OMVPE in GaInAs. © 1990.

DOI： 10.1016/0167-9317(90)90079-9

Scopus

researchmap

Summary form only given. The authors report the quantum coherence properties of hot electrons for GaInAs/InP systems. They obtained these properties along a path length as long as 280 nm at 77 K, the longest coherent length ever reported. The device used for the observation was a hot-electron transistor. The common-base emitter current-voltage characteristic was observed at 77 K when the collector-base voltage VCBis zero. To confirm the quantum interference effect, the authors evaluated this characteristic by the first derivative. Three obvious peaks at 0.04, 0.08, and 0.15 V were observed under 0.2 V, and oscillations with a short period were observed when the applied voltage was over 0.2 V. Forty-eight oscillations were observed between 0.2 and 0.4 V. Three peaks under 0.2 V occurred due to the quantum interference effect in the base region. The period of peaks above 0.2 V was very short in comparison with those below 0.2 V. This threshold voltage, 0.2 V, agrees with the band discontinuity of GaInAs/InP systems. Thus it was judged that the oscillation above 0.2 V occurred due to the quantum interference effect in the InP collector barrier.

Scopus

researchmap

記述言語：英語   出版者・発行元：JAPAN J APPLIED PHYSICS  

Web of Science

researchmap

記述言語：英語  

A 1·5 μm-wavelength dynamic-single-mode laser with highlow reflection grating structure aiming at high output and one-directional output operation has been obtained for the first time using a selective etching process and low-pressure MOVPE regrowth. A front/rear output power ratio exceeding 50 and side-mode suppression ratio (SMSR) greater than 39 dB were obtained at 1·3 times the threshold. © 1989, The Institution of Electrical Engineers. All rights reserved.

DOI： 10.1049/el:19891106

Scopus

researchmap

記述言語：英語  

Corrugations of 70 nm pitch and 100 nm depth were formed on InP using electron beam lithography and wet chemical etching having the material selective and anisotropic qualities. For this purpose, a thin GaInAs layer grown by MOVPE was used as an etching mask to suppress the undercut etching so as to form very fine structures. © 1989, The Institution of Electrical Engineers. All rights reserved.

DOI： 10.1049/el:19890169

Scopus

researchmap